MG2RT ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Full Range of Matrices with up to 480K Gates
  • 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
  • RAM and DPRAM Compilers
  • Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
  • 3 and 5 Volts Operation; Single or Dual Supply Mode
  • High Speed Performances: – 450 ps Max NAND2 Propagation Delay at 4.5V, 720 ps at 2.7V and FO = 5 – Min 610 MHz Toggle Frequency at 4.5V, 320 MHz at 2.7V
  • Programmable PLL Available upon Request
  • High System Frequency Skew Control through Clock Tree Synthesis Software
  • Low Power Consumption: – 1.96 µW/Gate/MHz at 5V – 0.6 µW/Gate/MHz at 3V
  • Integrated Power On Reset
  • Matrices with a Max of 484 Fully Programmable Pads
  • Standard 3, 6, 12 and 24 mA I/Os
  • Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
  • CMOS/TTL/PCI Interface
  • ESD (2 kV) and Latch-up Protected I/O
  • High Noise and EMC Immunity: – I/O with Slew Rate Control – Internal Decoupling – Signal Filtering between Periphery and Core – Application Dependent Supply Routing and Several Independant Supply Sources
  • Wide Selection of MQFPs and MCGA Packages up to 472 Pins
  • Delivery in Die Form with 94.6 µm Pad Pitch
  • Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
  • Cadence®, Mentor®, Vital® and Synopsys® Reference Platforms
  • EDIF and VHDL Reference Formats
  • Available in Military and Space Quality Grades (SCC, MIL-PRF-38535)
  • No Single Event Latch-up below an LET threshold of 80MeV/mg/cm2
  • Tested up to a Total Dose of 60 Krad (Si) according to MIL STD 883 Method 1019
  • QML Q and V with SMD 5962-00B02

Description

The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays up to 480K gates cover most system inte gration needs. The MG2RT is manufactured using a 0.5 micron drawn, 3 metal layer CMOS process, called SCMOS 3/2RT. The base cell architecture of the MG2RT seri es provides high routability of logic with extremely dense compiled memories: RA M and DPRAM. ROM can be generated using synthesis tools. Accurate control of clock distribution ca n be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: three or mo re independent supplies , internal decoupling, customiszation depende nt supply routing, noise filter ing, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. The MG2RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog, Modelsym and Design Compiler are the reference front-end tool s. Floor planning associated with timing- driven layout provides a short back-end cycle. Rad Tolerant 350K Used Gates 0.5 µm CMOS Sea of Gates MG2RT

The MG2RT library allows straight forward migration from the MG1RT and MG1 Sea of Gates. ulated as MG2 provided there are no SEU hardened cells. Note: Not available for new designs. logic and test synthesis tools. cell for RAM and DPRAM. The main characteristics of these generators are summarised below. Table 1. List of Available MG2RT Matrices

4115L–AERO–06/05 MG2RT I/O Buffer Interfacing I/O Flexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer. Inputs Input buffers with CMOS or TTL thresholds are non-inverting and feature versions with and with- out hysteresis. The CMOS and TTL input bu ffers may incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available. Outputs Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA drive at 5V, low noise buffers with 12 mA drive at 5V. Clock Generation and PLL Clock Generation Atmel offers 6 different types of oscillators: 4 high frequency crystal oscillators and 2 RC oscilla- tors. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms. PLL Contact factory. Oscillators Frequency (MHz) Typical Consumption (mA) Max 5V Max 3V 5V 3V Xtal 7M 12 7 1.2 0.4 Xtal 20M 28 17 2.5 0.8 Xtal 50M 70 40 7 2 Xtal 100M 130 75 16 5 RC 10M 10 10 2 1 RC 32M 32 32 3 1.5

4115L–AERO–06/05 MG2RT Power Supply and Noise Protection The speed and density of the SCMOS3/2RT technology cause large switching current spikes for example when:

  • either 16 high current output buffers switch simultaneously,
  • or 10% of the 480,000 gates are switching within a window of 1 ns. Sharp edges and high currents cause some parisit ic elements in the packaging to become sig- nificant. In this frequency range, the package in ductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O Buffers Switching Protection Three features are implemented to limit the noise generated by the switching current:
  • The power supplies of the input and output buffers are separated.
  • The rise and fall times of the output buffers can be controlled by an internal regulator.
  • A design rule concerning the number of buffers connected on the same power supply line has been imposed. Matrix Switching Current Protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added:
  • Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop.
  • A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells.
  • A low pass filter has been added between the ma trix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers.

4115L–AERO–06/05 MG2RT Packaging Atmel offers a wide range of packaging options which are listed below: Note: 1. Contact Atmel local design centers to check the availability of the matrix/package combination. Package Type(1) Pins min/max Lead Spacing (mils) MQFP 100 132 196 256 352

4115L–AERO–06/05 MG2RT Design Flows and Tools Design Flows and Modes A generic design flow for an MG2RT array is illustrated below. A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step , structural verification is performed which includes the following tasks:

  • Gate level logic simulation and compar ison with high level simulation results.
  • Design and test rules check.
  • Power consumption analysis.
  • Timing analysis (only after floor plan). The main design stages are:
  • System specification, preferably in VHDL form.
  • Functional description at RTL level.
  • Logic synthesis.
  • Floor planning and bonding diagram generation.
  • Test/Scan insertion, ATG and/or fault simulation.
  • Physical cell placement, JTAG in sertion and clock tree synthesis.
  • Routing. To meet the various requirements of designers, several interface levels between the customer and Atmel are possible. For each of the possible design modes a review me eting is required for data transfer from the user to Atmel. In all cases the final routing and verifications are performed by Atmel. The design acceptance is formalized by a design review which authorizes Atmel to proceed with sample manufacturing.

Figure 1. MG2RT Design Flow

The basic content of a design kit is described in the table below.

  • VHDL for functional descriptions
  • VHDL or EDIF for netlists
  • Tabular, log or .VCD for simulation results
  • SDF (VITAL format) and SPF for back annotation
  • LEF and DEF for physical floor plan information The design kits supported for several commercial tools are listed below. Design Kit Support • Cadence/Verilog (RTL and gate), Logic Design Planner
  • Mentor/Modelsim (RTL and gate), Velocity, BSD Architect, Flex Test
  • Synopsys, Design Compiler, PrimeTime
  • V i t a l

Table 2. Design Kit Description

4115L–AERO–06/05 MG2RT

Electrical Characteristics

Ambient temperature under bias (TA) TTL/CMOS: Note: Stresses above those listed may cause permanent damage to the device. Exposure to absolute maxi- mum rating conditions for extended period may affect device reliability. Table 3. DC Characteristics - Specified at VDD = +5V ± 10% Notes: 1. According buffer: Bo ut24, Bout12, Bout6, Bout3.

  1. Supplied as a design limit but not guarant eed or tested. No more than one output at a time may be shorted for a maximum

Table 4. DC Characteristics - Specified at VDD = +3V ± 0.3V

0.3 VDD

0.7 VDD

Notes: 1. According buffer: Bo ut24, Bout12, Bout6, Bout3.

  1. Supplied as a design limit but not guarant eed or tested. No more than one output at a time may be shorted for a maximum

Table 5. AC Characteristics - TJ = 25°C, Process typical (all values in ns)

Table 6. AC Characteristics - TJ = 25°C, Process typical (all values in ns)

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