Power Management

MFS2401AVBA0ES

NXP Semiconductors

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Rev. 4 - 23 October 2024

Manufacturer: NXP Semiconductors

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Technical content

Datasheet sections

1 General description
2 Features and benefits
3 Applications
4 Ordering information
4.1 Part numbers definition
4.2 Part numbers list
5 Block diagram
5.1 Internal block diagram
5.2 Simplified application diagram
6 Pinning information
6.1 Pinning
6.2 Pin description
6.2.1 Connection of unused pins
7 Functional description
7.1 Main state machine description
7.2 Detailed functional state diagram
7.3 INIT state machine
7.4 Power sequencing
7.5 Debug and OTP modes
7.5.1 Electrical characteristics
7.6 MCU programming
7.7 Best of supply (BOS)
7.7.1 Functional description
7.7.2 Best of supply (BOS) electrical
8 Limiting values
9 Static characteristics
10 Thermal characteristics
11 Application information
12 EMC compliancy
13 Operating range and current
13.1 Supply voltage
13.2 Operating range
13.3 Current consumption
14 Power management
14.1 V1 HVBUCK: High-voltage buck regulator
14.1.1 Functional description
14.1.2 HVBUCK clock management
14.1.2.1 Description
14.1.2.2 Spread spectrum
14.1.2.3 Pseudo-random modulation
14.1.3 Application schematic
14.1.4 Electrical characteristics
14.1.5 HVBUCK efficiency
14.2 V3 HVLDO: High-voltage linear regulator
14.2.1 Functional description
14.2.2 Application schematic
14.2.3 Electrical characteristics
15 AMUX: Analog multiplexer
15.1 Functional description
15.2 AMUX schematic diagram
15.3 Channel selection
15.4 Electrical characteristics
16 I/O interface pins
16.1 WAKE2/HID0, WAKE3/HID1
16.1.1 WAKE feature
16.1.2 Hardware ID feature
16.1.3 Electrical characteristics
16.2 HVIO1
16.2.1 HVIO1 used as input
16.2.2 HVIO1 used as output
16.2.3 Electrical characteristics
16.3 INTB
16.3.1 Interrupts and wake-up events
16.3.2 Electrical characteristics
17 Long duration timer (LDT)
17.1 Calibration procedure
17.2 Timer functions
17.3 Electrical characteristics
18 Physical layer
18.1 CAN FD transceiver
18.1.1 CAN operating modes
18.1.1.1 CAN off mode
18.1.1.2 CAN Wake-capable mode
18.1.1.3 CAN wake-up
18.1.1.4 CAN Listen-only mode
18.1.1.5 CAN Active mode
18.1.2 Electrical characteristics
19 Safety
19.1 Functional description
19.2 Watchdog
19.2.1 Watchdog selection
19.2.1.1 Timeout watchdog
19.2.1.2 Window watchdog
19.2.2 Watchdog error counter
19.2.3 Watchdog refresh counter
19.2.4 Watchdog error impact
19.2.5 Watchdog electrical characteristics
19.3 Voltage supervisor
19.3.1 V0MON (VMON_EXT) monitoring
19.3.2 VxMON monitoring (x = 1, 3)
19.3.3 VxMON UV/OV threshold
19.3.4 VxMON deglitch time
19.3.5 VxMON safety reaction (impact)
19.3.6 V1UVLP monitoring
19.3.7 Electrical characteristics
19.4 External IC monitoring
19.5 Fault management
19.5.1 Fault error counter
19.5.2 Fault source and reaction
19.5.3 Fail-safe mode
19.6 RSTB, LIMP0
19.6.1 RSTB
19.6.2 LIMP0 as a safety output
19.6.3 LIMP0 as a safety output release
19.6.4 LIMP0 as a GPO
19.7 Analog built-in self-test (ABIST)
19.8 Cyclic CRC check
19.9 Clock monitoring
20 MCU communication

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Rev. 4 — 23 October 2024 Product data sheet Document information Information Content Keywords Fail-safe system basis chip, SMPS, LDO, CAN FD transceiver, ultra-wide band (UWB), Near Field Communication (NFC), Bluetooth Low Energy (BLE) devices, small applications, low power Abstract The FS2400 is a family of automotive safety system basis chip devices with multiple power supplies designed to support secure car-access application while maintaining flexibility to fit other small applications requiring low power and CAN FD communication.

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

1 General description

FS2400 is a family of automotive safety system basis chip (SBC) devices with multiple power supplies designed to support secure car access application using ultra-wide band (UWB), near-field communication (NFC) and Bluetooth Low Energy (BLE) devices. The FS2400 can also fit other small applications requiring low power and CAN FD communication. This family of devices supports a wide range of applications, offering choice of output voltage settings, physical interface, integrated system-level features to address low-power and noise-sensitive applications with automotive safety integrity levels (ASIL) up to ASIL B. The FS2400 integrates a battery-connected switched-mode regulator (V1) and a battery-connected linear regulator (V3) to supply microcontroller, communication devices and others. V1 offers a high-performance switching regulator capable of operating in Pulse Frequency Modulation (PFM) mode and Force Pulse Width Modulation (FPWM) mode. The mode of operation can be changed using wake pins to optimize noise management. The FS2400 is developed in compliance with the ISO 26262:2018 standard. It includes enhanced safety features, with fail-safe output, becoming part of a full safety-oriented system, covering ASIL B safety integrity level. The FS2400 is offered in a 5 mm x 5 mm, 32-Ld HVQFN package with wettable flanks. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

2 Features and benefits

40 V DC maximum input voltage
Low-power off mode with very low sleep current and multiple wake-up sources
Low-power on mode with HVBUCK (V1) active, HVLDO (V3) selectable by OTP and multiple wake-up sources Power supplies
V1: High-voltage synchronous buck converter with integrated FETs. Configurable output voltage (1.9 V to 5 V) and switching frequency, output DC current capability up to 400 mA and PFM mode for Low-power on mode operation
V3: High-voltage LDO regulator for microcontroller I/O support with selectable output voltage between 3.3 V or

5 V and up to 150 mA current capability

One CAN FD supporting up to 5 Mbps communication following ISO 11898-2:2016 and SAE J2284 standards
Four wake-up inputs (40 V capable): WAKEx pins, HVIO1 pin, CAN FD or SPI command
Hardware ID detection capability
One high-voltage I/O with wake-up capability (40 V capable): HVIO1
Device control via 32 bits SPI interface, with CRC
Integrated long duration timer (LDT) for system shutdown and wake-up control, programmable up to 194 days
12-channel analog multiplexer (AMUX) for system monitoring (temperature, battery voltage, internal voltages) Functional safety
Developed following ISO 26262:2018 standard to fit for ASIL B applications
Internal monitoring circuitry with its own reference.
Additional input for external voltage monitoring
Window or timeout watchdog function to monitor the MCU software failure
Analog built-in self-test (ABIST) on demand
Safety outputs (RSTB, LIMP0)
Safety input to monitor external IC state (ERRMON) Configuration and enablement
HVQFN32EP: QFN, 32 pins with exposed pad for optimized thermal management, wettable flanks, 5 mm x 5 mm x 0.85 mm, 0.5 mm pitch
Permanent device customization via one time programmable (OTP) fuse memory
OTP emulation mode for system development and evaluation FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

3 Applications

UWB anchors
NFC anchors
BLE anchors
Combo anchors (UWB + BLE)
UWB radar
All small applications requiring low power and CAN FD
UWB master anchors FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

4 Ordering information

describes how the part number reference is built.

4.1 Part numbers definition

Figure 1 describes how the FS24 part numbers are built. Figure 1. FS24 product numbering scheme FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

4.2 Part numbers list

Table 1. Device segmentation [1] Exact orderable part numbers are defined in Table 2. MFS2400AVMA0ES[2] Superset covering FS2400M devices. MFS2401AVMA0ES[2] Superset covering FS24001M devices. MFS2400AVBA0ES[2] Superset covering FS2400B devices. MFS2401AVBA0ES[2] Superset covering FS2401B devices. MFS2400AVMA1ES Configuration given as an example for Ranger 5 attach, V1 at 3.3 V and V3 at 5 V. QM, LDT disabled. MFS2401AVBA1ES Configuration given as an example for Ranger 5 attach, V1 at 3.3 V and V3 at 5 V. ASIL B, LDT enabled. MFS2401AVMAFES Configuration given as an example for S32K1xx + NCF3321 attach, V1 at 5 V and V3 at 3.3 V. QM, LDT enabled. Table 2. Orderable part numbers [1] To order parts in tape and reel, add the R2 suffix to the full part number reference. configuration, please contact a local NXP sales representative. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

5 Block diagram

5.1 Internal block diagram

5.2 Simplified application diagram

6 Pinning information

6.1 Pinning

Figure 6. FS2400 pin configuration Figure 7. FS2400 pin configuration legend

6.2 Pin description

1 WAKE3/HID1 Analog input Wake-up input 3 / Hardware ID 1

2 V3_IN Analog input V3 regulator input voltage

3 V3 Analog output V3 regulator output voltage

4 VCC5CAN Analog input CAN input supply pin

7 GNDCAN Ground CAN bus ground

8 HVIO1 Digital input/output High-voltage IO 1, with wake-up capability

9 CANTXD Digital input Transceiver input from the MCU, which controls the state of the CAN bus. 10 CANRXD Digital output Receiver output, which reports the state of the CAN bus to the MCU.

11 DEBUG Analog input Debug mode entry and OTP input supply

12 VDIG Analog output Internal digital supply

13 GND_IO Ground IOs ground connection

input voltage is monitored in order to detect external reset and fault condition.

19 INTB Digital output Interrupt output

20 PGND Ground Power ground connection (V1 HVBUCK)

21 V1_SW Analog input/output Switching node (V1 HVBUCK)

22 V1_IN Analog input V1 regulator input voltage

23 BOOT Analog input/output V1 bootstrap capacitor (V1 HVBUCK)

25 VMON_EXT Analog input External voltage monitoring input

26 VBOS Analog output Best of supply output voltage

27 V1 Analog output V1 regulator output voltage

28 VDDIO Analog input Input voltage for SPI and AMUX

29 AMUX Analog output Multiplexed output to be connected to an MCU ADC

with selection of the analog parameter though SPI.

30 NC Not connected Not connected

31 VSUP Analog input Power supply of the device

32 WAKE2/HID0 Analog input Wake-up input 2 / Hardware ID 0

Table 3. Pin description...continued

6.2.1 Connection of unused pins

1 WAKE3/HID1 Analog input Open (WAKE3PUPD_OTP = 01)

2 V3_IN Analog input Grounded

3 V3 Analog output Grounded or open

4 VCC5CAN Analog input Grounded

5 CANH Analog input/output Open

6 CANL Analog input/output Open

7 GNDCAN Ground Connection mandatory

8 HVIO1 Digital input/output Open (HVIO1PUPD_OTP = 01)

9 CANTXD Digital input Open (200 kΩ internal pull up to VDDIO)

10 CANRXD Digital output Open (push-pull structure)

11 DEBUG Analog input Connection mandatory to GND in application mode

12 VDIG Analog output Connection mandatory

13 GND_IO Ground Connection mandatory

14 MISO Digital output Open

15 MOSI Digital input Open (200 kΩ internal pull up to VDDIO)

16 SCK Digital input/output Connection mandatory

17 CSB Digital input/output Connection mandatory

18 RSTB Digital input/output Connection mandatory

19 INTB Digital output Open

20 PGND Ground Connection mandatory

21 V1_SW Analog input/output Connection mandatory

22 V1_IN Analog input Connection mandatory

23 BOOT Analog input/output Connection mandatory

24 LIMP0/GPO Digital output Open

25 VMON_EXT Analog input GND

26 VBOS Analog output Connection mandatory

27 V1 Analog output Connection mandatory

28 VDDIO Analog input Connection mandatory

29 AMUX Analog output Open

30 NC Not connected Open

31 VSUP Analog input Connection mandatory

32 WAKE2/HID0 Analog input Open (WAKE2PUPD_OTP = 01)

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

7 Functional description

The FS24 device has one main state machine. The main state machine manages the power management, the Low-power modes, and the wake-up sources. It also manages the monitoring of the power management, the monitoring of the MCU and the monitoring of an external IC. In parallel, an INIT state machine is implemented to manage the INIT state of the device. This state is used for the configuration of the device per SPI. The safety pins RSTB and LIMP0 are managed independently of on another, in parallel of the main state machine.

7.1 Main state machine description

Power-on reset and power-up sequence The FS24 starts when VBOS > VBOS_POR and VDIG_OV > VDIG > VDIG_POR. VBOS is the first supply to start. The internal 1.6 V supply of the digital circuitry, VDIG, is generated from VBOS. When VBOS > VBOS_UV, the high power (HP) analog circuitry is enabled and the OTP registers content is loaded into mirror registers. When VSUP > VSUP_UVH, the power-up sequence starts in Slot 0, with V1 (HVBUCK) at least, and power-up sequencing follows the OTP programming for V3 (HVLDO) and HVIO1 if used as an output. Transition to fail-safe during the power up During the power-up sequence, if VBOS < VBOS_UV, the device goes to Fail-safe mode and all regulators are disabled. If an overvoltage or an overtemperature is detected, the device goes to fail-safe, depending on the OTP configuration. Normal mode When the power up is finished, the main state machine is in Normal mode. Normal mode is the application running mode and VSUP_UVH has no effect even if VSUP < VSUP_UVH, except generating an interruption. If VBOS < VBOS_UV, the device goes to Fail-safe mode. See Figure 10 for the minimum operating voltage. Transitions to Low-power modes The device can go to Low-power modes via an SPI command from the MCU. A GO2LPOFF command starts the power-down sequence to go in LPOFF mode. A GO2LPON command will start the power-down sequence to go in LPON mode. The device goes in Low-power mode after the power-down sequence. During power-down sequence, the device stops all the regulators in the reverse order of the power-up sequence. In case the device goes in LPON, V1 regulator is kept ON but switches from FPWM to PFM mode. Transition to Fail-safe from Normal mode In case of loss of VBOS (VBOS < VBOS_UV), the device goes directly to Fail-safe mode without power-down sequence. In case of overvoltage detection, or thermal shutdown detection (TSD) on a regulator, depending on OTP configuration, or when the fault error counter reaches its maximum value, the device stops and goes directly to Fail-safe mode without power-down sequence. Fail-safe state exit Two behaviors are configurable by OTP to exit the Fail-safe state:

Automatic restart after TFS_DUR (autoretry feature, configurable by OTP at 100 ms or 4 s)
Semi-automatic restart after TFS_DUR: The device exits Fail-safe state and enters LPOFF state, then waits for a wake-up source to transition to M2 and restarts (FS_LPOFF_OTP = 1). FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

7.2 Detailed functional state diagram

1 MHz oscillator enabled

20 MHz oscillator enabled

20 MHz oscillator disabled

7.3 INIT state machine

Figure 9. Simplified INIT state diagram is equivalent to disabling the watchdog, for MCU programming for example. See Section 7.6. The INIT state can be accessed again from Normal mode by sending a GO2INIT request by SPI.

7.4 Power sequencing

register if they were enabled by OTP. is set to 1, the TSLOT timer between SLOT_2 and SLOT_1 will be bypassed, as well. Figure 10. Power sequencing FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 11. Power-up sequence example

7.5 Debug and OTP modes

7.5.1 Electrical characteristics

Table 5. Electrical characteristics

7.6 MCU programming

opened). If the watchdog is not disabled, the user must refresh it during the MCU programming. voltage to the DEBUG pin before M4 state.

7.7 Best of supply (BOS)

7.7.1 Functional description

the device, in all device modes. VBOS is also the supply of V1 High-Side and Low-Side gate drivers. powers down the device by going into fail-safe state. biasing, and VBOS_LP used to supply the internal biasing in Low-power modes. (State #M2). Both VBOS_LP and VBOS_HP are generated from VSUP. disabled by OTP using VBOS2V1_SW_LP_EN_OTP bit. When waking up from LPON mode, VBOS transition to VBOS_LP than immediately to VBOS_HP. In LPOFF mode, only VBOS_LP is enabled. The behavior of the VBOS regulator is summarized in Figure 15. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 15. Simplified VBOS state diagram

7.7.2 Best of supply (BOS) electrical characteristics

8 Limiting values

9 Static characteristics

10 Thermal characteristics

Table 9. Thermal ratings application-specific environment. [2] Thermal resistance between the die and the printed-circuit board. Board temperature is measured on the top surface of the board near the package. the exposed pad without contact resistance. [4] Thermal test board meets JEDEC specification for this package (JESD51-7). FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

2.2 MHz

Figure 16. Application schematic, 2.2 MHz HVBUCK, SPI interface Optional components depend on the application EMC and battery voltage ISO 7637-2 pulses requirements. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

12 EMC compliancy

The FS24 EMC performance is verified against BISS generic IC EMC Test Specification version 2.0 from 07.2012 and FMC1278 Rev3 Electromagnetic Compatibility Specification for Electrical/Electronic Components and Subsystems from 2018. In addition, EMC performance is verified against SAE J2962-2 (2019) and IEC 62228-3 (2019) for CAN performances. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

13 Operating range and current consumption

13.1 Supply voltage

Electrical characteristics

TA = –40 °C to 115 °C, unless otherwise specified. VSUP from 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Device power supply VSUP Device input supply voltage VSUP_UVH - 40 V VSUP_OV VSUP overvoltage threshold 20 - 22 V VSUP_UVHL VSUP undervoltage rising threshold, low configuration VSUP_UVTH_OTP = 0 4.5 4.7 4.9 V VSUP_UVHH VSUP undervoltage rising threshold, high configuration VSUP_UVTH_OTP = 1 5.5 5.7 5.9 V VSUP_UVLL VSUP undervoltage falling threshold (VSUP_4P7_I flag) 4.5 4.7 4.9 V VSUP_UVLH VSUP undervoltage falling threshold (VSUP_5P7_I flag) 5.5 5.7 5.9 V TSUP_OV VSUP_OV filtering time 6 10 15 us TSUP_UV VSUP_UVL filtering time 6 10 15 us Internal digital supply VDIG Device digital supply voltage 1.55 1.6 1.65 V VDIG_OV VDIG overvoltage threshold 1.85 2 2.15 V TDIG_OV VDIG_OV filtering time 0.13 1 3.1 us VDIG_POR VDIG power-on reset threshold on falling edge 1.35 1.41 1.47 V TDIG_POR VDIG_POR filtering time 0.13 1 3.1 us Interface supply pins VDDIO VDDIO supply voltage range 1.8 - 5.5 V Table 10. Supply voltage happened but has no direct action to the safety pins (RSTB, LIMP0). FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

13.2 Operating range

5.5 V V1UV_LP VBOS_UV 18 V 28 V 40 V LPOFF mode Extended voltage range, potential thermal Iimitation Extended voltage range, potential thermal Iimitation Extended voltage range, potential thermal Iimitation High Voltage extended Operation High Voltage extended Operation High Voltage extended Operation Risk of damage Risk of damage Risk of damage Full Operation Full Operation Full Operation No Operation No Operation No Operation Figure 17. Input voltage range in LPOFF, LPON, and NORMAL mode

VSUP > 28 V: potential thermal limitation (risk of TSD detection)
VSUP > 18 V: extended high-voltage transient operation (Load dump)
VSUP < 5.5 V: linear regulator needs a minimum of 5.5 V input when configured to deliver 5 V output. AMUX, CAN and IO specified for VSUP > 5.5 V
VSUP < VBOS_UV in LPOFF mode: wake-up capability of the device is not guaranteed anymore, risk of POR
VSUP < V1UV_LP in LPON mode: undervoltage detected on V1 in LPON mode leads the device to Fail-safe mode, with all regulators OFF
VSUP < VBOS_UV in NORMAL mode: the device goes to Fail-safe mode, with all regulators OFF FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

13.3 Current consumption

TA = –40 °C to 115 °C, unless otherwise specified. VSUP from VSUP_UVH to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Quiescent current INORMAL Current in Normal mode

V1 in Force PWM mode
V3 enabled
CAN in Wake-up mode
V1 output current = 0 mA
V3 output current = 0 mA
Wake pins ignored - 5 10 mA Current in Low-power on (LPON) mode Typical value at Tj=25 °C. Maximum value at Tj = 85 °C
VSUP = 12 V
V1 output voltage set ≥ 3.3 V[1]
V1 in Pulse Frequency Modulation (PFM) mode
HVIO1 wake-up only - 40 50 µA IQ_LPON Current in Low-power on (LPON) mode Typical value at Tj = 25 °C. Maximum value at Tj = 85 °C
VSUP = 12 V
V1 output voltage set < 3.3 V
V1 in Pulse Frequency Modulation (PFM) mode
HVIO1 wake-up only - 65 80 µA IQ_LPOFF_CWK Current in Low-power off (LPOFF) mode Typical value at Tj = 25 °C. Maximum value at Tj = 85 °C
VSUP = 12 V
V1 off
V3 off
HVIO1 wake-up only - 35 55 µA

Table 11. Current consumption configured by OTP). This way, the current consumption beneficiates from the ratio between VBAT and V1 output. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14 Power management

Table 12. FS24 regulators list The FS24 includes two regulators, all supplied in parallel from the battery line. sequencing from the OTP programming for the remaining regulator V3 (HVLDO).

14.1 V1 HVBUCK: High-voltage buck regulator

14.1.1 Functional description

other local loads inside the ECU. reflecting the output DC current. rampup/down between the normal and the LPON voltages is done in PWM mode. current in case of output short to the battery. detection (V1UV_I flag generated). with RDCR_LBUCK = 200 mΩ and VBUCK = 3.3 V). When a thermal shutdown is detected, the regulator is disabled and V1TSD_I flag is generated. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14.1.2 HVBUCK clock management

14.1.2.1 Description

default, the spread-spectrum feature is configured following the OTP configuration. of the HVBUCK switching frequency.

14.1.2.2 Spread spectrum

frequency of 19 kHz with a ±10 % deviation range of the nominal oscillator frequency.

20 MHz + 10 %

20 MHz - 10 %

Figure 18. Triangular modulation random commutations on the carrier slope are added in each half period to increase the spectrum content. Figure 19. Pseudo-random modulation FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14.1.2.3 Pseudo-random modulation

random commutations on the carrier slope are added in each half period to increase the spectrum content. Figure 20. Pseudo-random modulation

14.1.3 Application schematic

Figure 21. HVBUCK schematic with connection to V1_IN

14.1.4 Electrical characteristics

TA = –40 °C to 115 °C, unless otherwise specified. VBUCK + VHDR < V1_IN pin voltage < 36 V, unless otherwise specified. All voltages referenced to ground.

Normal mode using VV1_BUCK_OTP and VV1_BUCK_RANGE_ OTP OTP registers)
Low-power on mode using VV1_LP_BUCK_OTP and VV1_ BUCK_RANGE_OTP OTP registers) 1.9 - 5 V

TA = –40 °C to 115 °C, unless otherwise specified. VBUCK + VHDR < V1_IN pin voltage < 36 V, unless otherwise specified. All voltages referenced to ground. Table 13. Electrical characteristics...continued FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 115 °C, unless otherwise specified. VBUCK + VHDR < V1_IN pin voltage < 36 V, unless otherwise specified. All voltages referenced to ground. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 115 °C, unless otherwise specified. VBUCK + VHDR < V1_IN pin voltage < 36 V, unless otherwise specified. All voltages referenced to ground.

12 V, FSW_BUCK = 450 kHz

[2] For all regulators, the effective capacitor value is the capacitor value after Tolerance, DC bias and Aging removal. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14.1.5 HVBUCK efficiency

OTP configurations listed in Table 14. Table 14. Hardware and configurations TFM252012ALMA4R7MTAA reference inductor and the VLS3015CX-4R7M-H reference inductor, respectively. Figure 22. HVBUCK efficiency using 2.25 MHz using TFM252012ALMA4R7MTAA FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 23. HVBUCK efficiency at 2.25 MHz using VLS3015CX-4R7M-H inductor and the VLS3015CX-4R7M-H reference inductor.

3.3 V VLS3015CX-4R7M-H

3.3 V TFM252012ALMA4R7MTAA

Figure 24. HVBUCK PFM efficiency

14.2 V3 HVLDO: High-voltage linear regulator

14.2.1 Functional description

configurable by OTP at 3.3 V or 5 V. A minimum voltage drop of 500 mV is required. HVLDO3 is low-power capable and can stay enabled in LPON mode by setting V3ON_LPON bit by SPI. However, if disabled in LPON mode, it cannot be enabled again by SPI in this mode. can also supply an additional external transceiver on the module. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

V3EN bit. When a thermal shutdown is detected, the regulator is disabled and V3TSD_I flag is generated.

14.2.2 Application schematic

Figure 25. HVLDO3 application schematic

14.2.3 Electrical characteristics

unless otherwise specified. ILDO3 = 0 mA to 150 mA unless otherwise specified. All voltages referenced to ground. Table 15. Electrical characteristics FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

unless otherwise specified. ILDO3 = 0 mA to 150 mA unless otherwise specified. All voltages referenced to ground. Table 15. Electrical characteristics...continued FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15 AMUX: Analog multiplexer

15.1 Functional description

capacitor CAMUX_OUT is required for the buffer stability.

15.2 AMUX schematic diagram

Figure 26. AMUX block diagram

15.3 Channel selection

Table 16. AMUX output selection...continued using the AMUX_EN and AMUX_PD_DIS bits, respectively, from M_AMUX_CTRL register.

15.4 Electrical characteristics

otherwise specified. IAMUX = -1 mA to 1 mA, unless otherwise specified. All voltages referenced to ground.

AMUX_DIV = 0
AMUX_DIV = 1 4.5 40 V VAMUX_OUT AMUX output voltage range 0.3 - VDDIO – 0.2 V RPD_AMUX Output pulldown resistance 200 400 800 kΩ VAMUX_OFF Offset voltage -8 - 8 mV VAMUX_RATIO Ratio accuracy
Ratio 1
Other ratio -0.5 -1.5 0.5 1.5 VTEMP25 Temperature sensor voltage at 25 °C 1.36 1.38 1.4 V VTEMP_COEFF Temperature sensor coefficient -3.95 -3.88 -3.8 mV/°C TAMUX_SET Settling time - - 10 us CAMUX_OUT Output capacitor - - 1 nF

16 I/O interface pins

16.1 WAKE2/HID0, WAKE3/HID1

WAKEx/HIDx pin has two different roles. It can be used either as a wake-up pin or as hardware ID detection pin. Figure 27. WAKEx/HIDx diagram

16.1.1 WAKE feature

WAKEx/HIDx pins are high-voltage inputs used as wake-up sources for the device. transceiver. When a WAKE pin is used as a global pin, an R - C protection is required. be enabled, disabled, or configured as cell repeater, as per WKxPUPD_OTP[1:0] bits. resistor is selected. If the buffer output is high, the pullup resistor is selected.

16.1.2 Hardware ID feature

location in the car based on WAKEx/HIDx pins hardware connection.

Connected to VBAT
Connected to GND
Open Using the two WAKEx/HIDx pins allows up to nine different hardware ID combinations. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

16.1.3 Electrical characteristics

TA = −40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

WKx_DGLT = 0
WKx_DGLT = 1 80 μs

16.2 HVIO1

an external device monitoring pin) or as open-drain output. Figure 30. HVIO1 pin

16.2.1 HVIO1 used as input

wake-up event can be generated on level (high or low) depending on HVIO1_WUCFG[1:0] bits. When used as a wake-up source, wake-up filtering time is configurable by SPI using HVIO1_DGLY bit. resistor is selected. If the buffer output is high, the pullup resistor is selected. When an HVIO pin is used as a global input pin, an R - C protection is required. See Section 11.

16.2.2 HVIO1 used as output

Figure 31. Example of HVIO1 pin configuration in the slots, at power up

16.2.3 Electrical characteristics

TA = −40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

HVIO1_DGLT = 0
HVIO1_DGLT = 1 80 μs THVIO1_FALL Fall time using open drain (external pullup at VUP = 14 V, COUT_HVIO1 = 10 nF) - - 30 μs THVIO1_WU Time between HVIO1 rising and V1 switching from PFM to PWM mode when HVIO1 configured as “mode selection”
LOAD_OTP_BYP = 0
LOAD_OTP_BYP = 1 150 μs

Table 19. HVIO1 electrical characteristics

16.3 INTB

interrupt occurs to inform the MCU. Each interrupt can be masked by setting the corresponding inhibit interrupt. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

16.3.1 Interrupts and wake-up events management

"Classic" interrupts used to diagnose the device state and to report events
Wake-up interrupts used to manage the wake-up from the Low-power modes See Table 21 for a list of all interrupts. The classic interrupts are maskable. If these interrupts are not masked, they will generate a pulse on INTB pin. Out of Normal mode, most of these interrupt flags will not be generated because the monitoring functions associated will be disabled. In addition, the WKx_I, HVIO1_I flags are not generated out of Normal mode. WAKEx/HIDx pins, HVIO1 pin, CAN and LDT can be configured as wake-up sources using xxxx_WUEN[1:0] SPI configuration bits. Each wake-up source can be configured to generate an interrupt, a transition to Normal mode or both. In this last case, a wake-up event on these functions will generate a non-maskable wake-up flag (xxxx_WU_I) and an interrupt pulse on INTB. In LPON mode, if a wake-up event occurs and the wake-up source is enabled, an interrupt is generated and/ or the device transitions to Normal mode. If only the interrupt generation is enabled, it is the MCU decision to request a transition to Normal mode or not, via GO2NORMAL SPI bit. In LPOFF mode, if a wake-up event occurs and the wake-up source is enabled, the device transitions to Normal mode.

16.3.2 Electrical characteristics

TA = −40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

INTB_DUR = 0 (short)
INTB_DUR = 1 (long) 17.5 100 32.5 130 μs TINTB_TO INTB timeout for wake-up event 8 10 12 ms TINTB_DLY Delay between INTB_REQ command reception and INTB pulse start 36 40 44 μs

Table 20. INTB electrical characteristics Table 21. List of interrupts from main logic FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

17 Long duration timer (LDT)

configurable counting periods, as well as a calibration mechanism for oscillator compensation. The timer is based on a 24-bits counter, with a 1 MHz oscillator, allowing a 1 second time base.

1 MHz

Figure 32. Long duration timer block diagram the prescaler 2 is bypassed and the timer can count up to 36 minutes, with 128 µs resolution. Table 22. Long duration timer characteristics

When LDT_MODE = 0, the LDT is set in Long-count mode.
When LDT_MODE = 1, the LDT is set in Short-count mode. The LDT_AFTER_RUN[15:0] bits can set and read the after run value in Normal mode. When the run value corresponds to the timer value, that triggers either a transition to LP mode or an interrupt. The LDT_WUP_H[7:0] and the LDT_WUP_L[15:0] bits allows the MCU to set and read the wake-up value. The wake-up value corresponds to the timer value that triggers a wake-up event:
The LDT_WUP_H[7:0] contains the eight most significant bits of the wake-up value.
The LDT_WUP_L[15:0] contains the 16 least significant bits of the wake-up value. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

When LDT_SEL = 0, the MCU reads or writes the wake-up value in the LDT_WUP_H[7:0] and the LDT_WUP_L[15:0] bits.
When LDT_SEL = 1, the MCU reads the counter current value. The LDT_EN bit shall be provided to start the LDT timer operation:
When LDT_EN = 0, the LDT is disabled.
When LDT_EN = 1, the LDT starts counting as defined in the M_LDT_CTRL and L_LDT_CFGx registers. The LDT2LP bit selects which Low-power mode (LPON or LPOFF) it needs to go once the after-run timer is expired, when timer function 2 or 3 is selected.
When LDT2LP = 0, the device goes into LPON mode when the after-run timer expires.
When LDT2LP = 1, the device goes into LPOFF mode when the after-run timer expires.
When timer function 4 or 5 is selected and the LDT_EN = 1, the LDT does not start any count until the device enters the corresponding Low-power mode.

17.1 Calibration procedure

calculate a time offset. It is recommended to perform the calibration between -20 °C and +85 °C.

Set the Timer mode to short count and select the timer function 1. Set the after-run value at max value 0xFFFF (~8.39 s).
Start the counter.
Read the counter when the MCU RTC reaches 6 s.
If the oscillator period is at the exact typical value (absolutely no deviation error), expected reading is 46875.
The exact reading calculates the error correction factor ECF = exact_reading / expected_reading
ECF < 1 if the oscillator is faster than the exact typical value.
ECF > 1 if the oscillator is slower than the exact typical value.
After calibration, the new after-run or wake-up values to set the counter are “after run x ECF” and “wake-up x ECF”.

17.2 Timer functions

000 Function 1: In Normal mode, count and generate a flag or an interrupt when the counter

reaches the after-run value.

001 Function 2: In Normal mode, count until the counter reaches the after-run value and enters

010 Function 3: In Normal mode, count until the counter reaches the after-run value and enters

011 Function 4: In Low-power mode, count until the counter reaches the wake-up value and

100 Function 5: In Low-power mode, count and do not wake up unless the counter overflow

occurs or if the device wakes up by wake-up input source. Table 23. LDT functions FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

17.3 Electrical characteristics

TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 18 V, unless otherwise specified. All voltages referenced to ground. Symbol Description Min Typ Max Unit FIN_CLK_LDT Long duration timer source clock (1 MHz / 64) - 15.625 - kHz TBASE_LDT 128 s µs IQ_LDT_85 Long duration timer quiescent current consumption (Tj = 85 °C) - 2 5 µA IQ_LDT_125 Long duration timer quiescent current consumption (Ta = 125 °C) - 5 10 µA LDTACC1 Long duration timer accuracy without calibration -10 - 10 % LDTACC2 Long duration timer accuracy with calibration In LPOFF or LPON states Including month aging drift (max) Including temperature drift 0 °C < Tj < 85 °C -5 - 5 % LDTDRIFT Long duration timer maximum drift per hour after calibration In LPOFF or LPON states Within 20 °C temperature variation. -1 - 1 % Table 24. Long duration timer electrical characteristics FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18 Physical layer

18.1 CAN FD transceiver

controller of an MCU and the physical CAN bus. Figure 34. CAN FD transceiver internal diagram, with external components

18.1.1 CAN operating modes

Off
Wake-capable
Listen-only
Active The Listen-only and Active modes are only available when the device is in Normal mode. In Low-power modes, the transceiver can be kept in Wake-capable mode in order to be used as a wake-up source for the device and the module. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Figure 35. CAN transceiver state machine

18.1.1.1 CAN off mode

and the MCU has set the CAN_FS_DIS bit to 0. CANH and CANL pins are set high ohmic, and the CANRXD pin is driven high.

18.1.1.2 CAN Wake-capable mode

the wake-up capability of the CAN is enabled, regardless of the device state once powered up. biased to ground via the common-mode input resistor RCAN_IN_CM and the CANRXD pin is driven high. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.1.1.3 CAN wake-up

Figure 36. CAN Wake-up timing diagram CANRXD pin will be asserted low for 1.5 ms. flag must be cleared after each wake-up event in order for the CAN communication to work properly.

18.1.1.4 CAN Listen-only mode

device must be in Normal mode and no undervoltage on V3 must be detected. pullup resistor RCANTXD_PU connected to VDDIO.

18.1.1.5 CAN Active mode

Listen-only mode and the transmitter is disabled. device can transmit information from CANTXD to the CAN bus and report the bus level to the CANRXD pin. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 37. CAN timing definition according to ISO 11898-2:2016

18.1.2 Electrical characteristics

19 Safety

19.1 Functional description

application needs. FS24 also provides an on-demand ABIST to cover latent faults. Figure 38. Fail-safe features block diagram

19.2 Watchdog

and the second half is said open. the microcontroller must refresh the watchdog in the open window of the watchdog window period. closed. The watchdog configuration requires the MCU to write in FS_WDW_CFG registers. during INIT phase). When enabled in LPON, the watchdog operates in Timeout mode. stored in the WD_TOKEN register, and is changed alternatively after each good WD refresh. wrong or not given at the right moment, or not given at all at the end of the watchdog period. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

period is set to 256 ms, and the watchdog type is set to timeout watchdog.

0000 DISABLE (infinite open window)

Table 26. Watchdog window period configuration

19.2.1 Watchdog selection

changed during operation by SPI using WDW_EN bit.

0 Timeout watchdog (default)

1 Window watchdog

Table 27. Watchdog type configuration

19.2.1.1 Timeout watchdog

and WD_NOK_I flag is set to 1.

19.2.1.2 Window watchdog

Figure 39. Window watchdog time diagram Table 28. Watchdog answer and refresh validation

19.2.2 Watchdog error counter

WD_ERR_LIMIT[1:0] bits during the INIT phase. Table 29. Watchdog error counter limit configuration The watchdog error counter value can be read by the MCU for diagnostic with the WD_ERR_CNT[3:0] bits. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 40. Watchdog error counter configurations

19.2.3 Watchdog refresh counter

Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog, the

watchdog refresh counter is reset to 0. the WD_RFR_LIMIT[1:0] bits during the INIT_FS phase. Table 30. Watchdog refresh counter limit configuration The watchdog refresh counter value can be read by the MCU for diagnostic with the WD_RFR_CNT[2:0] bits. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 41. Watchdog refresh counter configurations

19.2.4 Watchdog error impact

happens in LPON mode, the device also wakes up.

0 No effect on the pin

Table 31. Watchdog error impact configuration

19.2.5 Watchdog electrical characteristics

TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 32. Watchdog electrical characteristics

19.3 Voltage supervisor

reported accordingly. VMON0 monitoring on VMON_EXT pin is enabled by OTP (V0MON_EN_OTP). FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.3.1 V0MON (VMON_EXT) monitoring

with the internal thresholds accuracy (±1.5 %). The MCU can monitor VMON_EXT pin voltage using the AMUX by selecting channel 18, see Section 15.3.

19.3.2 VxMON monitoring (x = 1, 3)

The VxMON UV/OV threshold have ±1 % accuracy (trimmed at 5 V setting, 5 % VMON threshold).

19.3.3 VxMON UV/OV threshold

additional UV thresholds are available at 62 %, 63.5 %, 64 %, 64.5 %, and 65 %. Table 33. VMON UV/OV threshold configuration FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.3.4 VxMON deglitch time

Table 34. VMON deglitch time configuration

19.3.5 VxMON safety reaction (impact)

configurable with VxMON_OV/UV_RSTB/LIMP0_IMPACT bits during the INIT phase, for each monitoring input. The reactions of RSTB pin can be preconfigured by OTP.

19.3.6 V1UVLP monitoring

threshold, the device goes into fail-safe state (not configurable), and V1_UVLP_WU bit is set to 1.

19.3.7 Electrical characteristics

TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 35. VxMON electrical characteristics FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 35. VxMON electrical characteristics...continued

19.4 External IC monitoring

HVIO1 pin is used to monitor an external IC.

Polarity of the fault signal, configurable with ERRMON_FLT_POLARITY bit during the initialization phase
Desired reaction on RSTB and LIMP0
Time allowed to the microcontroller for receiving error acknowledgment When an error is detected, the microcontroller should acknowledge the FS24 device. If the acknowledgment is not received by the FS24 within the predefined time, the FS24 asserts LIMP0 and/or RSTB pin as defined during the initialization phase. The following tables, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, depict the different SPI bits used by this external IC monitoring function: FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

1 Low to high level

Table 36. Signal polarity to detect an error on HVIO1 pin

0 Error on HVIO1 pin asserts LIMP0 only

Table 37. Reaction when an error is detected HVIO1 pin Table 38. Allowed time before receiving microcontroller acknowledge when an external IC error is

0 No error detected by FS24

1 Error detected. FS24 is waiting for an acknowledgment within the allowed time. Table 39. Error flag for external IC monitoring

0 No error reported by MCU

1 Error detected and reported to FS24 by MCU

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver aaa-046859 Error signal (ERRMON input) FS24 ERRMON_ACK bit LIMP0 Reset counter ERRMON_ACK_TIME ERRMON_ACK_TIME Error acknowledged by MCU. Internal monitoring signal released. No error reported. Error NOT acknowledged by MCU. Error reported at the end of the counter. LIMP0 is asserted Figure 42. External IC monitoring timing diagram TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. VIH_ERRMON High-level input voltage threshold 0.7 x VDDIO - - V VIL_ERRMON Low-level input voltage threshold - - 0.3 x VDDIO V VIN_HYS_ERRMON Threshold hysteresis 100 - - mV tERRMON_ERR Filtering time 4 6 8 µs tERRMON_ACK_ACC Acknowledgment counter accuracy -10 - 10 % RPD_ERRMON ERRMON pulldown resistor value 200 400 800 kΩ Table 41. External IC monitoring electrical characteristics

19.5 Fault management

19.5.1 Fault error counter

Table 43. Fault error counter fail-safe impact Figure 43. Fault error counter diagram with maximum value = 2 or 6 FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 44. Fault error counter diagram with maximum value = 8 or 12

19.5.2 Fault source and reaction

counter is incremented by 1, each time the RSTB and/or LIMP0 pin is asserted. In Orange, the reaction is not configurable. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

In Green, the reaction is configurable by OTP and SPI for RSTB and by SPI for LIMP0 in INIT mode. Table 44. Application related fail-safe fault list and reaction transitioning to Fail-safe state. [2] By default (when no fault), RSTB is asserted in LPOFF mode. In the Fail-safe state, RSTB and LIMP0 are asserted.

19.5.3 Fail-safe mode

The fault error counter reaches its maximum value (not configurable)
VBOS UV is detected
RSTB is asserted low for 8 s (if enabled by OTP)
VxOV is detected (if configured by OTP)
VxTSD is detected (if configured by OTP)
V1UVLP is detected in LPON mode or during transition from LPON mode to Normal mode
When the first fault is detected (if configured by OTP) In Fail-safe mode, all the regulators are turned OFF, the high-power analog circuitry is disabled, the 20 MHz oscillator is disabled, the OV/UV monitoring are masked and FS_EVT bit is set to 1. The fault error counter is reset to 1 and disabled. The device exits the fail-safe state after TFS_DUR time. If FS_LPOFF_OTP bit is set to 1, the device exits FS state and goes to LPOFF. Otherwise it goes back to power-up sequence. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

TA = -40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

FS_DUR_CFG_OTP = 0
FS_DUR_CFG_OTP = 1 3.6 100 110 4.4 ms s

Table 45. Fail-safe state electrical characteristics

19.6 RSTB, LIMP0

Two safety output pins, RSTB and LIMP0, are implemented in order to guarantee the safe state of the system. All of those safety outputs are active low. released at startup and is only asserted when a fault occurs. The two pins are managed independently in parallel of the main-state machine.

19.6.1 RSTB

an external pullup resistor to VDDIO. An internal pulldown RSTBRPD ensures RSTB low level in case of POR. asserted at MCU request by SPI, to check the correct HW connection. Figure 45. RSTB pin implementation to accommodate specific MCU requirement asking for voltage supply stabilization before RSTB is released. TA = -40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 46. RSTB electrical characteristics FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = -40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 46. RSTB electrical characteristics...continued

19.6.2 LIMP0 as a safety output

(LPON and LPOFF), LIMP0 works as it does in Normal mode. GUN and ISO 7637 transient pulses. A weak internal pulldown RPD ensures LIMP0 low level in case of pin lift. request by SPI, to check the correct HW connection. Figure 46. LIMP0 pin implementation FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = -40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 47. LIMP0 electrical characteristics

19.6.3 LIMP0 as a safety output release

No fault affecting LIMP0 reported
Fault error counter = 0
Device in Normal mode
Device not in INIT mode
FS_LIMP0_REL register filled with the correct value, depending on current WD_TOKEN[15:0], (WD_TOKEN[15:8] with LSB and MSB inverted, then complemented)

19.6.4 LIMP0 as a GPO

up) by setting the LIMP0_REL bit.

19.7 Analog built-in self-test (ABIST)

launching the next ABIST. The flags have no impact on the safety pins. ignored. While the ABIST is running, the other monitoring functions are kept available. TA = −40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 48. ABIST electrical characteristics

19.8 Cyclic CRC check

a misconfiguration from the MCU or a bit flip in the INIT registers.

FS_I_OVUV_CFG1[15:0]
FS_I_OVUV_CFG2[15:0]
FS_I_ERRMON_LIMP0_CFG[15:0]
FS_I_FSSM_CFG[15:4]
FS_I_WD_CFG[15:7] The calculation to apply on the result of the concatenation is the same as the SPI CRC, using x^8+x^4+x^3+x^2+1 polynomial. The MCU must write the obtained CRC in the FS_CRC register before closing the INIT phase, after the modification of the INIT registers. Once the INIT phase is closed and the device is in Normal mode, the cyclic CRC check is launched automatically each 5 ms (TCRC) (<FTTI). Each 5 ms, the device logic recalculates the CRC and compares it to the value stored in FS_CRC register. If a mismatch is reported, the INIT_CRC_NOK_I bit is set and LIMP0 is asserted depending on its impact configuration (INIT_CRC_LIMP0_IMPACT). TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Cyclic CRC check TCRC CRC check timing interval 4.75 5 5.25 ms

Table 49. Cyclic CRC check characteristics

19.9 Clock monitoring

20 MCU communication

The FS24 provides SPI interface for device configuration, control and diagnostic, in Normal and LPON modes.

20.1 SPI communication

Bits 31 to 25: register address
Bit 24: read/write (For reading Bit 24 = ‘0’; For writing Bit 24 = ‘1’)
Bits 23 to 8: control bits
Bits 7 to 0: cyclic redundant check (CRC) Primary input secondary out bits (MISO):
Bits 31 to 24: general device status
Bits 23 to 8: device internal control register content
Bits 7 to 0: cyclic redundant check (CRC) The digital SPI pins (CSB, SCLK, MOSI, MISO) are referenced to VDDIO. The MCU is the master driving MOSI. FS24 is the slave driving MISO. The MISO data is latched at the SCLK rising edge and MOSI data is latched at the SCLK falling edge. MSB is sent first. In write command, MISO [31:24] bits are the general status flags, [23:8] bits are all 0 and MISO [7:0] is the CRC of the message sent by the FS24. In read command, MOSI [23:8] bits are all 0 and MOSI [7:0] is the CRC of the message sent by the MCU. Table 50 and Table 51 describe SPI communication protocol for writing data into the FS24 or reading data from the FS24. B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 MOSI Register address [6:0] R/W Write data [15:8] MISO 0 WD_G PHYG WUG IOG COMG VSUPG VXG Read data [15:8] B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MOSI Write data [7:0] CRC [7:0] MISO Read data [7:0] CRC [7:0] - response

Table 50. SPI write command message construction Table 51. SPI read command message construction FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 No error

1 Watchdog refresh error reported

30 WD_G

1 CAN error reported

29 PHYG

0 No event reported in M_IOWU_FLG or M_WU1_FLG registers

1 An interrupt or flag is present in M_IOWU_FLG or M_WU1_FLG registers

28 WUG

0 No event reported in M_IO_TIMER_G register

1 An interrupt or flag is present in M_IO_TIMER_G register

27 IOG

0 No event reported into M_VSUP_COM_FLG register

1 An interrupt or flag is present in the M_VSUP_COM_FLG register

26 COMG

25 VSUPG

0 No event reported into M_REG_FLG register

1 An interrupt or flag is present in the M_REG_FLG register

24 VxG

20.1.1 Cyclic redundant check

x^8+x^4+x^3+x^2+1 (identified by 0x1D) with a seed value of hexadecimal '0xFF'. Figure 47. CRC encoder example significant bits of the shift register. Table 53. Data preparation for CRC encoding Table 54. Data preparation for CRC encoding

Using a serial CRC calculation method, the transmitter rotates the seed and data into the least significant
During the serial CRC calculation, the seed and the data bits are XOR compared with the polynomial data
Once the CRC is calculated, it replaces the CRC byte initially set to all zeros and is transmitted.
The seed value is loaded into the most significant bits of the receive register.
Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least

significant bits of the shift register in the order received (MSB first).

When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the

If the shift register contains all zeros, the CRC is correct.
If the shift register contains a value other than zero, the CRC is incorrect. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

20.1.2 Electrical characteristics

otherwise specified. All voltages referenced to ground. Table 55. SPI electrical characteristics FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

21 Register mapping

22 Main register mapping

22.1 M_DEV_CFG

Table 58. M_DEV_CFG register bit allocation

0 VMON_EXT is disabled

1 VMON_EXT is enabled

2 V0MON_EN

0 LIMP0 is disabled3 LIMP0_EN

1 LIMP0 is enabled

0 ABIST on demand is disabled

1 ABIST on demand is enabled

6 ABIST_EN

0 LDT is disabled

1 LDT is enabled

11 LDTIM_EN

0 The CAN is disabled

1 The CAN is enabled

13 CAN_EN

Table 59. M_DEV_CFG register bit description

22.2 M_DEV_PROG_ID

Table 60. M_DEV_PROG_ID register bit allocation...continued

0001 Pass A silicon

0010 Pass B silicon

Table 61. M_DEV_PROG_ID register bit description

22.3 M_GEN_FLAG

Table 62. M_GEN_FLAG register bit allocation

1 Vx event occurred

0 VxG

1 VSUP error reported

1 VSUPG

1 Communication error reported

3 IOG

4 WUG

5 PHYG

6 WD_G

Table 63. M_GEN_FLAG register bit description...continued

22.4 M_STATUS

Table 64. M_STATUS register bit allocation

0 V3 is disabled

1 V3 is enabled

0 V3_S

0 V1 is disabled

1 V1 is enabled

2 V1_S

3 V1_MODE

0 BUCK is in PWM mode

1 BUCK is in PFM mode

0 HVIO1 is low

1 HVIO1 is high

7 HVIO1_S

0 WAKE2 is low

1 WAKE2 is high

10 WK2_S

0 WAKE3 is low

1 WAKE3 is high

11 WK3_S

0 Device is not in INIT mode

1 Device is in INIT mode

12 INIT_S

0 Device is not in Normal mode

1 Device is in Normal mode

13 NORMAL_S

0 Device is not in LPON mode

1 Device is in LPON mode

14 LPON_S

0 V1 temperature is < TWARNV1

1 V1 temperature is > TWARNV1

15 V1TWARN_S

22.5 M_SYS_CFG

Table 66. M_SYS_CFG register bit allocation

0 Spread spectrum is disabled (regardless of OTP configuration)

1 Spread spectrum is enabled (regardless of OTP configuration)

0 MOD_EN

0 Triangular modulation is selected

1 Pseudo random modulation is selected

1 MOD_CONF

0 INTB pulse = 25 us

1 INTB pulse = 100 us

3 INTB_DUR

0 No effect

1 INTB pulse is requested

4 INTB_REQ

0 Interrupt timeout will not generate a wake-up event

1 Interrupt time out will generate a wake-up event

5 INT_TO_WUEN

0 No action

1 Go to LPOFF mode

6 GO2LPOFF

1 Go to LPON mode

7 GO2LPON

1 Go to Normal mode

8 GO2NORMAL

1 Go to INIT phase

9 GO2INIT

0 No POR event

1 Digital POR event occurred

12 POR

0 No battery failure event

1 Battery failure event occurred

14 BAT_FAIL

Table 67. M_SYS_CFG register bit description...continued

22.6 M_SYS1_CFG

Table 68. M_SYS1_CFG register bit allocation

0 Device is not in OTP mode

1 Device is in OTP mode

0 OTP_MODE

0 No action1 OTP_EXIT

1 Leave OTP mode

0 Device is not in Debug mode

1 Device is in Debug mode

3 DBG_MODE

1 Leave Debug mode

4 DBG_EXIT

1 Software POR is requested

6 SOFTPOR_REQ

0 TSLOT = 2 ms

1 TSLOT = 0 ms

8 TSLOT_DOWN_CFG

0 Slots are not bypassed

1 Bypass unnecessary slots during power down or wake-up from LPON

9 SLOT_BYP

0 OTP loading is not bypassed

1 OTP loading is bypassed

10 LOAD_OTP_BYP

01010 M10

01011 M11

01100 M12

01101 M13

01110 M14

01111 M15

10000 M16

10001 M17

10010 M18

11110 M30

22.7 M_REG_CTRL

Table 70. M_REG_CTRL register bit allocation

0 No effect (Regulator remain in its current state)

1 Request to disable V3

0 V3DIS

1 Request to enable V3

1 V3EN

0 Follow the power down slot configuration

1 Keep V3 ON in LPON if V3 was already ON in NORMAL mode

2 V3ON_LPON

1 Request to disable V1

6 V1DIS

1 Request to enable V1

7 V1EN

000 HS rising slew rate is 20 ns (for 450 kHz only)

001 HS rising slew rate is 20 ns (for 450 kHz only)

010 HS rising slew rate is 15 ns (for 450 kHz only)

011 HS rising slew rate is 10 ns

101 HS rising slew rate is 5 ns

110 HS rising slew rate is 3 ns

111 HS rising slew rate is 2 ns

00 HS falling slew rate is 20 ns (for 450 kHz only)

01 HS falling slew rate is 15 ns (for 450 kHz only)

10 HS falling slew rate is 10 ns

11 HS falling slew rate is 5 ns

Table 71. M_REG_CTRL register bit description...continued

22.8 M_REG2_CTRL

Table 72. M_REG_CTRL register bit allocation...continued

1 V1 is set to DVS Value

8 GO2DVS

1 V1 is set to default Value

9 GOTODFLT[2]

0 Buck is set to default value

1 Buck is set to DVS value

7 VV1_BUCK_S

Table 73. M_REG_CTRL register bit description determined by the voltage settings and the VV1_BUCK_DVS_SR[1:0] setting.

22.9 M_REG_FLG

Table 74. M_REG_FLG register bit allocation...continued

0 No event detected

1 V3 OC occurred

0 V3OC_I

1 V1 OC occurred

2 V1OC_I

1 V3 OV occurred

3 V3OV_I

1 V1 OV occurred

5 V1OV_I

1 V3 UV occurred

6 V3UV_I

1 V1 UV occurred

8 V1UV_I

1 V1 undervoltage event occurred in LPON

9 V1UVLP_I

1 V3 TSD occurred

10 V3TSD_I

0 No event detected12 V1TSD_I

1 V1 TSD occurred

13 V1TWARN_I

1 V1 undervoltage pre-warning event occurred

14 V1UVW_I

1 V1 LS OC occurred

15 V1LSOC_I

Table 75. M_REG_FLG register bit description...continued

22.10 M_REG_MSK

Table 76. M_REG_MSK register bit allocation

0 Interrupt is not inhibited

1 Interrupt is inhibited

0 V3OC_M

2 V1OC_M

3 V3OV_M

0 Interrupt is not inhibited5 V1OV_M

6 V3UV_M

8 V1UV_M

9 V1UVLP_M

10 V3TSD_M

12 V1TSD_M

13 V1TWARN_M

14 V1UVW_M

15 V1LSOC_M

Table 77. M_REG_MSK register bit description...continued

22.11 M_REG1_FLG

1 VMON_EXT UV occurred

14 V0OV_I

1 VMON_EXT OV occurred

15 V0UV_I

Table 79. M_REG_FLG register bit description

22.12 M_REG1_MSK

Table 80. M_REG_MSK register bit allocation

14 V0OV_M

15 V0UV_M

Table 81. M_REG_MSK register bit description

22.13 M_IO_CTRL

0 No effect (IO remain in its current state)

1 Request to assert HVIO1 low

8 HVIO1LO

1 Request to release HVIO1 high

9 HVIO1HI

00 HVIO1 internal pulldown and pullup are disabled

01 HVIO1 internal pulldown is enabled and pullup is disabled

10 HVIO1 internal pulldown is disabled and pullup is enabled

11 HVIO1 internal pulldown and pullup are configured as cell repeater

00 WAKE3 internal pulldown and pullup are disabled

01 WAKE3 internal pulldown is enabled and pullup is disabled

10 WAKE3 internal pulldown is disabled and pullup is enabled

11 WAKE3 internal pulldown and pullup are configured as cell repeater

00 WAKE2 internal pulldown and pullup are disabled

01 WAKE2 internal pulldown is enabled and pullup is disabled

10 WAKE2 internal pulldown is disabled and pullup is enabled

11 WAKE2 internal pulldown and pullup are configured as cell repeater

Table 83. M_IO_CTRL register bit description

22.14 M_IO_TIMER_FLG

0 No event on WAKE2

1 Event on WAKE2 occurred

1 WK2_I

0 No event on WAKE3

1 Event on WAKE3 occurred

2 WK3_I

0 No event on HVIO1

1 Event on HVIO1 occurred

3 HVIO1_I

7 WK3_I

0 No event on LDT

1 Event on LDT occurred

8 LDT_I

Table 85. M_IO_TIMER_FLG register bit description

22.15 M_IO_TIMER_MSK

Table 86. M_IO_TIMER_MSK register bit allocation

0 Interrupt is not inhibited in Normal mode

1 Interrupt is always Inhibited

1 WK2_M

2 WK3_M

3 HVIO1_M

8 LDT_M

Table 87. M_IO_TIMER_MSK register bit description...continued

22.16 M_VSUP_COM_FLG

Table 88. M_VSUP_COM_FLG register bit allocation

0 VSUPUV_4P7_I

0 No VSUP OV event

1 VSUP OV event occurred

1 VSUPOV_I

2 VSUPUV_5P7_I

1 SPI request error reported

5 SPI_REQ_I

1 SPI clock error reported

6 SPI_CLK_I

1 SPI CRC error reported

7 SPI_CRC_I

1 VBOS UV occurred

11 VBOS_UV_I

0 The switch is opened

1 The switch is closed

12 VBOS2V1SW_S

Table 89. M_VSUP_COM_FLG register bit description...continued

22.17 M_VSUP_COM_MSK

Table 90. M_VSUP_COM_MSK register bit allocation

0 VSUPUV_4P7_M

1 VSUPOV_M

2 VSUPUV_5P7_M

5 SPI_REQ_M

6 SPI_CLK_M

7 SPI_CRC_M

Table 91. M_VSUP_COM_MSK register bit description...continued

22.18 M_IOWU_CFG

Table 92. M_IOWU_CFG register bit allocation

00 Input comparator disabled in LP modes only (no consumption)

01 High-level wake-up is configured

10 Low-level wake-up is configured

11 Reserved

11 Wake-up via mode selection is configured

0 WAKE2 deglitcher = 15 us

1 WAKE2 deglitcher = 65 us

9 WK2_DGLT

0 WAKE3 deglitcher = 15 us

1 WAKE3 deglitcher = 65 us

10 WK3_DGLT

0 HVIO1 deglitcher = 15 us

1 HVIO1 deglitcher = 65 us

11 HVIO1_DGLT

Table 93. M_IOWU_CFG register bit description...continued

22.19 M_IOWU_EN

Table 94. M_IOWU_EN register bit allocation

00 No wake-up and no interrupt

01 Wake-up only

10 Interrupt only

11 Wake-up and interrupt

01 Wake=up only

Table 95. M_IOWU_EN register bit description...continued

22.20 M_IOWU_FLG

Table 96. M_IOWU_FLG register bit allocation

0 No wake-up by WAKE2 (level)

1 Wake-up by WAKE2 occurred (level)

1 WK2_WU_I

0 No wake-up by WAKE3 (level)

1 Wake-up by WAKE3 occurred (level)

2 WK3_WU_I

0 No wake-up by HVIO1 (level)

1 Wake-up by HVIO1 occurred (level)

5 HVIO1_WU_I

Table 97. M_IOWU_FLG register bit description

22.21 M_WU1_EN

Table 99. M_WU1_EN register bit description

22.22 M_WU1_FLG

Table 100. M_WU1_FLG register bit allocation

0 No wake-up by CAN

1 Wake-up by CAN occurred

0 CAN_WU_I

0 No wake-up by LDT

1 Wake-up by LDT occurred

2 LDT_WU_I

0 No wake-up by MCU GO2NORMAL request

1 Wake-up by MCU GO2NORMAL request occurred

4 GO2NORMAL_WU

0 No wake-up generated by Interrupt time out

1 Wake-up by Interrupt Time Out occurred

5 INT_TO_WU

0 No wake-up by V1 LPON undervoltage

1 Wake-up by V1 LPON undervoltage occurred

6 V1_UVLP_WU

0 No wake-up by max error failure

1 Wake-up by watchdog max error failure occurred

7 WD_OFL_WU

0 No wake-up by to RSTB assertion

1 Wake-up by to RSTB assertion occurred

8 EXT_RSTB_WU

0 No fail-safe event

1 Fail-safe event occurred (FSM went to Fail-safe state)

9 FS_EVT

Table 101. M_WU1_FLG register bit description...continued

22.23 M_AMUX_CTRL

Table 102. M_AMUX_CTRL register bit allocation

00000 AGND is selected

00001 V1p6 internal voltage (VDIG) is selected

00010 V1 voltage is selected

00011 Reserved

00100 V3 voltage is selected

00101 VBOS internal voltage is selected

00110 VSUP voltage is selected (divider ratio configurable by SPI)

01110 Reserved

01111 V3 temperature sensor is selected

10000 VDDIO not divided is selected

10010 VMON_EXT pin voltage is selected

1 High divider ratio is selected (div by 14)

8 AMUX_DIV

0 AMUX is disabled (HIZ, int pulldown)

1 AMUX is enabled in Normal mode only

9 AMUX_EN

0 AMUX pin pulldown is enabled

1 AMUX pin pulldown is disabled

11 AMUX_PD_DIS

Table 103. M_AMUX_CTRL register bit description...continued

22.24 M_LDT_CFG1

Table 104. M_LDT_CFG1 register bit allocation Table 105. M_LDT_CFG1 register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

22.25 M_LDT_CFG2

Table 106. M_LDT_CFG2 register bit allocation Table 107. M_LDT_CFG2 register bit description

22.26 M_LDT_CFG3

Table 108. M_LDT_CFG3 register bit allocation Table 109. M_LDT_CFG3 register bit description

22.27 M_LDT_CTRL

Table 110. M_LDT_CTRL register bit allocation...continued

0 LDT is idle

1 LDT is busy

0 LDT_RUN

1 LDT starts counting

1 LDT_EN

0 LDT is set to long count (1 s)

1 LDT is set to short count (128 us)

2 LDT_MODE

0 Target value of wake-up LDT timer can be read or write

1 Real-time value of 24-bits timer is reported (once LDT stopped)

3 LDT_SEL

000 Function1 is selected

001 Function2 is selected

010 Function3 is selected

011 Function4 is selected

100 Function5 is selected

101 Not used

110 Not used

111 Not used

0 Go to LPOFF

1 Go to LPON

7 LDT2LP

Table 111. M_LDT_CTRL register bit description

22.28 M_CAN

Table 112. M_CAN register bit allocation...continued

1 CAN thermal shutdown occurred

0 CAN_TSD_I

1 Dominant timeout occurred

1 CAN_TXD_TO_I

0 Tj < thermal shutdown limit

1 Tj > thermal shutdown limit

2 CAN_TSD_S

0 Normal operation

1 TXD dominant timeout condition is present

3 CAN_TXD_TO_S

0 CAN transceiver is set offline

1 CAN transceiver keeps the current state

5 CAN_FS_DIS

0 CAN is neither in listen-only mode nor in Normal mode

1 CAN is either in listen-only mode or in Normal mode

7 CAN_ACTIVE_

00 Transceiver offline (TX and RX disabled)

01 Transceiver receive-only mode (TX disabled and RX enabled)

10 Transceiver active mode (TX and RX enabled) reacting on V3UV

11 Transceiver active mode (TX and RX enabled) reacting on V3UV

0 Trxd_wu_timeout not bypassed

1 Trxd_wu_timeout bypassed

10 CAN_WU_TMR_BYP

22.29 M_CAN_MSK

Table 114. M_CAN register bit allocation

0 CAN_TSD_M

1 CAN_TXD_TO_M

000 CAN OFF

001 CAN_WAKE_CAPABLE

010 Invalid state

011 CAN_OFF

100 Invalid state

101 CAN_LISTEN_ONLY

110 Invalid state

111 CAN_ACTIVE

Table 115. M_CAN_MSK register bit description

22.30 M_MEMORY0

Table 117. M_MEMORY0 register bit description

22.31 M_MEMORY1

Table 118. M_MEMORY1 register bit allocation Table 119. M_MEMORY1 register bit description

22.32 M_HW_ID

Table 120. M_HW_ID register bit allocation

0 No effect (pulldown remains in its current state)

1 Request to disable pulldown

0 HIDW3PD_DIS

1 Request to enable pulldown

1 HIDW3PD_EN

0 No effect (pullup remains in its current state)

1 Request to disable pullup

2 HIDW3PU_DIS

1 Request to enable pullup

3 HIDW3PU_EN

4 HIDW2PD_DIS

5 HIDW2PD_EN

0 No effect (pullup remain in its current state)

6 HIDW2PU_DIS

7 HIDW2PU_EN

0 WAKE3 not used as HID

1 WAKE3 used as HID (set by user when configuring PU/PD)

8 HIDW3_ENABLE

0 WAKE2 not used as HID

1 WAKE2 used as HID (set by user when configuring PU/PD)

9 HIDW2_ENABLE

0 Lower-current setting for PU/PD

1 Higher-current setting for PU/PD (10 mA)

10 HIDW3_10MA_EN

11 HIDW2_10MA_EN

0 Lower threshold

1 Higher threshold

12 HIDW3_TH_SEL

13 HIDW2_TH_SEL

14 LIMP0_TH_SEL

23 Fail-safe register mapping

23.1 FS_I_OVUV_CFG1

Table 122. FS_I_OVUV_CFG1 register bit allocation

1 LIMP0 assertion

7 V1MON_UV_LIMP0_IMPACT

1 RSTB assertion

9 V1MON_UV_RSTB_IMPACT

10 V1MON_OV_LIMP0_IMPACT

12 V1MON_OV_RSTB_IMPACT

Table 123. FS_I_OVUV_CFG1 register bit description

23.2 FS_I_OVUV_CFG2

0 V0MON_OV_

Table 124. FS_I_OVUV_CFG2 register bit allocation...continued

0 V0MON_UV_LIMP0_IMPACT

2 V0MON_UV_RSTB_IMPACT

3 V0MON_OV_LIMP0_IMPACT

5 V0MON_OV_RSTB_IMPACT

7 V3MON_UV_LIMP0_IMPACT

9 V3MON_UV_RSTB_IMPACT

10 V3MON_OV_LIMP0_IMPACT

12 V3MON_OV_RSTB_IMPACT

23.3 FS_I_ERRMON_LIMP0_CFG

Table 126. FS_I_ERRMON_LIMP0_CFG register bit allocation

0 LIMP0 only is asserted low in case of fault detection on ERRMON

1 RSTb and LIMP0 only is asserted low in case of fault detected on ERRMON

0 ERRMON_FS_REACTION

0 Low-level is a fault after a negative-edge transition

1 High-level is a fault after a positive-edge transition

3 ERRMON_FLT_POLARITY

0 Interruption not masked

1 Interruption masked

4 ERRMON_M

0 LIMP0 is a safety pin

1 LIMP0 is a GPO

15 LIMP0_GPO

Table 127. FS_I_ERRMON_LIMP0_CFG register bit description

23.4 FS_I_FSSM_CFG

Table 128. FS_I_FSSM_CFG register bit allocation...continued

4 FLT_MID_LIMP0_IMPACT

6 FLT_MID_RSTB_IMPACT

00 Max Value = 2

01 Max Value = 6

10 Max Value = 8

11 Max Value = 12

12 RSTB_DUR

0 RSTB low 8 s timer is enabled

1 RSTB low 8 s time is disabled

13 RSTB8S_DIS

0 External RSTB monitoring is enabled

1 External RSTB monitoring is disabled

14 EXT_RSTB_DIS

0 RSTB_REQ disabled

1 RSTB_REQ enabled

15 RSTB_REQ_EN

Table 129. FS_I_FSSM_CFG register bit description...continued

23.5 FS_I_WD_CFG

0 WD stays enabled in LPON

1 WD is disabled in LPON

11 WD_DIS_LPON

12 WD_LIMP0_IMPACT

14 WD_RSTB_IMPACT

Table 131. FS_I_WD_CFG register bit description...continued

23.6 FS_WDW_CFG

Table 132. FS_WDW_CFG register bit allocation

0000 INFINITE Time Out, Window fully opened

0 Watchdog window is disabled (watchdog time out)

1 Watchdog window is enabled (watchdog window 50 %)

10 WDW_EN

Table 133. FS_WDW_CFG register bit description...continued

23.7 FS_WD_TOKEN

Table 134. FS_WD_TOKEN register bit allocation Table 135. FS_WD_TOKEN register bit description

23.8 FS_WD_ANSWER

Table 136. FS_WD_ANSWER register bit allocation Table 137. FS_WD_ANSWER register bit description FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

23.9 FS_LIMP0_REL

Table 138. FS_ LIMP0_REL register bit allocation

1 LIMP0 release

0 LIMP0_REL

Table 139. FS_LIMP0_REL register bit description

23.10 FS_ABIST

Table 140. FS_ABIST register bit allocation

0 No ABIST

1 ABIST on V3MON requested

0 ABIST_V3MON

1 ABIST on V1MON requested

2 ABIST_V1MON

1 ABIST on V1UVLP requested

3 ABIST_V1UVLP

1 ABIST on VMON_EXT requested

4 ABIST_V0MON

0 ABIST not executed on V3MON or fail on V3MON

1 V3MON ABIST PASS

6 ABIST_V3MON_DIAG

0 ABIST not executed on V1MON or fail on V1MON

1 V1MON ABIST PASS

8 ABIST_V1MON_DIAG

0 ABIST not executed on V1UVLP or fail on V1UVLP

1 V1UVLP ABIST PASS

9 ABIST_V1UVLP_DIAG

0 ABIST not executed on V0MON or fail on V0MON

1 V0MON ABIST PASS

10 ABIST_V0MON_DIAG

0 ABIST not executed

1 ABIST executed

12 ABIST_DONE

1 Clear ABIST flags (ABIST_DONE, ABIST_VxMON_DIAG, ABIST_V1UVLP_DIAG)

13 CLEAR_ABIST

1 Launch ABIST

14 LAUNCH_ABIST

Table 141. FS_ABIST register bit description...continued

23.11 FS_SAFETY_OUTPUTS

Table 142. FS_SAFETY_OUTPUTS register bit allocation...continued

0 LIMP0_REQ

0 No failure

1 Short to high detected

1 LIMP0_DIAG

0 LIMP0 pad is sensed low

1 LIMP0 pad is sensed high

2 LIMP0_SNS

0 LIMP0 Driver command sensed low

1 LIMP0 Driver command sensed high

3 LIMP0_DRV

1 RSTB assertion (pulse)

9 RSTB_REQ

10 RSTB_DIAG

0 RSTB pad is sensed low

1 RSTB pad is sensed high

11 RSTB_SNS

0 RSTB Driver command sensed low

1 RSTB Driver command sensed high

12 RSTB_DRV

0 No RSTB event

1 RSTB event occurred

13 RSTB_EVT

0 No RSTB pin assertion

1 RSTB pin assertion Occurred

14 RSTB_EXT

1 WD timer reset requested

15 WD_RST_REQ

Table 143. FS_SAFETY_OUTPUTS register bit description...continued

23.12 FS_SAFETY_FLG

Table 144. FS_SAFETY_FLG register bit allocation

0 WD refresh OK

1 WD refresh not OK

8 WD_NOK_I

9 WD_NOK_M

0 Low level

1 High Level

10 ERRMON_RT

1 Error detected

11 ERRMON_I

1 Acknowledge ERRMON timeout

12 ERRMON_ACK

0 No error/error acknowledged by user on time

1 ERRMON timer expired with no acknowledgement by user

13 ERRMON_TMR_EXP_I

Table 145. FS_SAFETY_FLG register bit description...continued

23.13 FS_CRC

Table 146. FS_CRC register bit allocation

9 INIT_CRC_LIMP0_IMPACT

0 No error detected

1 INIT registers CRC error detected

12 INIT_CRC_NOK_I

13 INIT_CRC_NOK_M

24 OTP bits description

24.1 Main OTP overview

Table 148. Main OTP overview

24.2 Main OTP bits description

[1] These codes are suggested as best fit for the described use cases. In case other values are needed, contact local support. [2] The slope compensation values are given for a typical V1_IN at 13.5 V.

24.3 Fail-safe OTP overview

Table 150. Fail-safe OTP overview...continued

24.4 Fail-safe OTP bits description

FS24 package is a QFN, thermally enhanced, wettable flanks, 5 x 5 x 0.85 mm, 0.5 mm pitch, 32 pins. Figure 49. Top and bottom view FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Updated legal information FS2400 v.3 12 January 2024 • Global editing for style and grammar.
Section 2: Under System support, updated text to "Four wake-up inputs (40 V capable): WAKEx pins, HVIO1 pin, CAN FD or SPI command" from "Four wake-up inputs (40 V capable): WAKEx pins, HVIO1 pin, CAN FD or SPI activity"
Updated Section 7.5: Added first paragraph
Updated Table 1 and Table 2
Updated Table 13 – For "RHS_BUCK" and "RLS_BUCK", added "Typical value at Tj = 25 °C. Maximum value at Tj = 150 °C" to Description, deleted "Min" value, changed "Max" value to "350" from "330". – For IOC_PK_PFM, removed "BUCK_PK_OC_PFM_OTP[2:0] = 010", "BUCK_PK_ OC_PFM_OTP[2:0] = 011", and "BUCK_PK_OC_PWM_OTP[2:0] = 100"
Updated Table 21: For Interrupt "EXT_RSTB_WU", changed Mask/Enable to "EXT_ RSTB_DIS" from "None"
Updated Table 73: For Bit "0 to 5", updated Description, added "Range 1 …" and "Range 2 ..." and footnote.
Updated Table 129: For Bit "14", updated Description
Updated Table 149 – For Address "0x24", Bit Group Name "VV1_BUCK_OTP" updated Settings for "0x08", "0x1C", "0x28", and "0x28", removed all others. – For Address "0x25", Bit Group Name "VV1_LP_BUCK_OTP" updated Settings for "0x08", "0x1C", "0x28", and "0x28", removed all others. – For Address "0x29", Bit Group Name "CRC_INV_OTP" updated Description.
Updated Figure 3, Figure 10 FS2400 v.2 20231207 Product data sheet FS2400 v.1 20230614 Preliminary data sheet FS2400 v.0.3 20230207 Preliminary data sheet FS2400 v.0.2 20220811 Initial version

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. 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Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HTML publications — An HTML version, if available, of this document is provided as a courtesy. Definitive information is contained in the applicable document in PDF format. If there is a discrepancy between the HTML document and the PDF document, the PDF document has priority. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Tables Tab. 24. Long duration timer electrical Tab. 30. Watchdog refresh counter limit Tab. 36. Signal polarity to detect an error on HVIO1 Tab. 37. Reaction when an error is detected HVIO1 Tab. 38. Allowed time before receiving microcontroller acknowledge when an Tab. 41. External IC monitoring electrical Tab. 44. Application related fail-safe fault list and Tab. 52. MISO general device status bits Tab. 89. M_VSUP_COM_FLG register bit Tab. 90. M_VSUP_COM_MSK register bit allocation ..101 Tab. 91. M_VSUP_COM_MSK register bit FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Tab. 126. FS_I_ERRMON_LIMP0_CFG register bit Tab. 127. FS_I_ERRMON_LIMP0_CFG register bit Tab. 142. FS_SAFETY_OUTPUTS register bit Tab. 143. FS_SAFETY_OUTPUTS register bit FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Figures Fig. 4. FS24 for UWB Simplified application Fig. 5. FS24 for UWB and BLE Simplified Fig. 16. Application schematic, 2.2 MHz HVBUCK, Fig. 17. Input voltage range in LPOFF, LPON, and Fig. 21. HVBUCK schematic with connection to V1_ Fig. 22. HVBUCK efficiency using 2.25 MHz using Fig. 23. HVBUCK efficiency at 2.25 MHz using Fig. 28. Example of application for hardware ID Fig. 31. Example of HVIO1 pin configuration in the Fig. 34. CAN FD transceiver internal diagram, with Fig. 37. CAN timing definition according to ISO Fig. 43. Fault error counter diagram with maximum Fig. 44. Fault error counter diagram with maximum FS2400 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 23 October 2024 Document feedback

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 23 October 2024 Document identifier: FS2400

Product Information

MFS2401AVBA0ES specifications and overview.

Summary

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Rev. 4 - 23 October 2024

Description

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver Rev. 4 - 23 October 2024

Source title MFS2401AVBA0ES Datasheet(PDF) - NXP Semiconductors

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