Power Management

MFS2300BMBA0EP

NXP Semiconductors

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Rev. 7.0 - 16 October 2024

Manufacturer: NXP Semiconductors

Document: 230 Pages / 2Mb

Request Quote Download Datasheet Read online HTML view

More from NXP Semiconductors Browse M parts

Online Datasheet

Read MFS2300BMBA0EP online.

FS23 NXP | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 230

Technical content

Datasheet sections

1 General description
2 Features and benefits
3 Simplified application diagram
4 Ordering information
4.1 Part numbers definition
4.2 Part numbers list
5 Applications
6 Internal block diagram
7 Pinout information
7.1 Pinout
7.2 Pin description
7.3 Connection of unused pins
8 Limiting values
9 Electrostatic discharge
10 Thermal characteristics
11 Operating range and current
11.1 Supply voltage
11.2 Current consumption
12 Functional description
12.1 Simplified state machine
12.2 Operation and power modes
12.3 Main state machine description
12.4 Detailed functional state diagram
12.5 INIT state machine
12.6 Power sequencing
12.7 Debug and OTP modes
12.7.1 Electrical characteristics
12.8 MCU programming
12.9 Best of supply
12.9.1 Functional description
12.9.2 BOS electrical characteristics
13 Power management
13.1 HVBUCK: High-voltage buck regulator
13.1.1 Functional description
13.1.2 HVBUCK clock management
13.1.2.1 Description
13.1.2.2 Spread spectrum
13.1.3 Application schematic
13.1.4 Electrical characteristics
13.1.5 HVBUCK efficiency
13.2 HVLDO1: High-voltage linear regulator
13.2.1 Functional description
13.2.2 Application schematic
13.2.3 Electrical characteristics
13.3 HVLDO2: High-voltage linear regulator
13.3.1 Functional description
13.3.2 Application schematic
13.3.3 Electrical characteristics
13.4 HVLDO3: High-voltage linear regulator
13.4.1 Functional description
13.4.2 Application schematic
13.4.3 Electrical characteristics
14 AMUX: Analog multiplexer
14.1 Functional description
14.2 Block diagram
14.3 Channel selection
14.4 Electrical characteristics
15 I/O interface pins
15.1 WAKE1, WAKE2
15.1.1 WAKE1 as input for Key OFF – Key ON
15.1.2 Electrical characteristics
15.2 HVIO1, HVIO2
15.2.1 HVIO1, HVIO2 used as input
15.2.2 HVIO1, HVIO2 used as output
15.2.3 Electrical characteristics
15.3 LVIO3, LVIO4, LVI5, LVO6
15.3.1 LVIO3, LVIO4, LVI5 used as input
15.3.2 LVIO3, LVIO4, LVO6 used as output
15.3.3 Electrical characteristics
15.4 I/Os configuration summary
15.5 INTB
15.5.1 Interrupts and wake-up events
15.5.2 Electrical characteristics
16 High-side drivers
16.1 Functional description
16.2 LED driving
16.3 Cyclic sense
16.4 Electrical characteristics
17 Long duration timer
17.1 Calibration procedure
17.2 Timer functions
17.3 Electrical characteristics
18 Physical layers
18.1 CAN FD transceiver
18.1.1 CAN operating modes
18.1.1.1 CAN Off mode
18.1.1.2 CAN Wake-capable mode
18.1.1.3 CAN Wake-up
18.1.1.4 CAN Listen-only mode
18.1.1.5 CAN Active mode
18.1.2 Electrical characteristics
18.2 LIN transceiver
18.2.1 LIN operating modes
18.2.1.1 LIN Off mode
18.2.1.2 LIN Wake-capable mode
18.2.1.3 LIN Wake-up
18.2.1.4 LIN Listen-only mode
18.2.1.5 LIN Active mode
18.2.2 Electrical characteristics
19 Safety
19.1 Functional description
19.2 Watchdog
19.2.1 Watchdog selection
19.2.1.1 Timeout watchdog
19.2.1.2 Window watchdog
19.2.2 Watchdog error counter
19.2.3 Watchdog refresh counter
19.2.4 Watchdog error impact
19.2.5 MCU fault recovery strategy

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Rev. 7.0 — 16 October 2024 Product data sheet Document information Information Content Keywords FS23, system basis chip (SBC), pin-to-pin, software compatible, low dropout (LDO), DC-DC, quality management (QM), automotive safety integrity level (ASIL) B Abstract The FS23 SBC offers an expandable family of devices that is pin-to-pin and software compatible. It is scalable from the LDO version to the DC-DC version, as well as from QM to ASIL B.

1 General description

system and safety features for the latest generation of automotive electronic control units (ECU). processors because of its high level of flexibility. sequencing, and inputs/outputs configuration to address multiple applications. Figure 1. Functional block diagram FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

2 Features and benefits

Normal mode with all power management and functional safety features available
Stop mode: Low-power OFF mode with multiple wake-up sources (LPOFF)
Standby mode: Low-power ON mode with HVBUCK or HVLDO1 active and multiple wake-up sources (LPON) Power management
HVBUCK: Synchronous buck converter with integrated FETs. Configurable Normal mode output voltage and LPON mode output voltage (3.3 V or 5.5 V). Output DC current capability of 600 mA in Normal mode, and 100 mA current capability in Low-power ON mode
HVLDO1: High-voltage LDO instead of the HVBUCK for MCU supply with selectable output voltage (3.3 V or 5.5 V) and up to 100 mA DC current capability with internal PMOS and 250 mA with external PNP
HVLDO2: High-voltage LDO regulator for system loads, with optional external protection for off-board sensors, selectable output voltage (3.3 V or 5.0 V) and up to 100 mA DC current capability
HVLDO3: High-voltage LDO regulator for CAN FD block supply or other with selectable output voltage (3.3 V or 5.0 V) and up to 150 mA current capability System features
One CAN FD supporting up to 5 Mbps communication following ISO 11898-2:2016 and SAE J2284 standards
One LIN following LIN 2.2, ISO 17987-4 and SAE-J2602-2 standards
Two wake-up inputs (40 V capable)
Two high-voltage I/Os with wake-up capability (40 V capable)
Up to four low-voltage I/Os with wake-up capability
Four configurable high-side drivers with 150 mA drive capability, to supply LEDs or enable external devices (INH), and cyclic-sense capability
Multiple wake-up sources: WAKE pins, HVIO pins, LVIO pins, CAN FD, LIN or dedicated SPI / I2C command
Device control via 32 bits SPI interface or via I2C interface, with CRC
Integrated long duration timer (LDT) for system shutdown and wake-up control, programmable up to 194 days
16-channel analog multiplexer (AMUX) for system monitoring (temperature, battery voltage, internal voltages) Functional safety
Developed following ISO 26262:2018 standard to fit for ASIL B applications
Internal monitoring circuitry with its own reference
Additional input for external voltage monitoring
Window or timeout watchdog function to monitor the MCU failures by software
FCCU inputs to monitor MCU failures by hardware
Analog built-in self-test (ABIST) on demand
Safety outputs (RSTB, FS0B, LIMP0 and LIMP1/2 with 1.25 Hz or 100 Hz PWM capability) EMC compliance
The FS23 EMC tests are performed according to ZVEI Generic IC EMC Test Specification version 2.1 (2017) and FMC1278 Electromagnetic Compatibility Specification for Electrical/Electronic Components and subsystems version 3.0 (2018).
CAN EMC performances certified against IEC62228-3:2019 and SAE J2962-2:2019
LIN EMC performances certified against IEC62228-2:2016 and SAE J2962-1:2019 Configuration and enablement
QFN48EP: QFN 48 pins with exposed pad for optimized thermal management, wettable flanks, 7 x 7 x 0.85 mm, 0.5 mm pitch, 48 pins
One-time programmable (OTP) memory for scalability, expandability and device customization
OTP emulation mode for system development and evaluation FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

3 Simplified application diagram

4 Ordering information

describes how the part number reference is built.

4.1 Part numbers definition

Two FS23 part numbering types can be found: a full part number reference and a simplified part number. Figure 3 and Figure 4 describe how the FS23 part numbers are built. Figure 3. Full FS23 part numbers breakdown

1 HVBUCK, 2 HVLDOs

Figure 4. Simplified FS23 part numbers breakdown Figure 5 maps FS23 part numbers versus the selectable product features. Figure 5. Part numbers mapping versus base feature sets FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

4.2 Part numbers list

Table 1. Device segmentation Note: Additional part numbers will exist with different features and parametric settings. The device segmentation is also available on nxp.com. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 2 is an example of orderable part number list. Table 2. Orderable part numbers FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

5 Applications

Body control module
HVAC
Lighting
Steering column lock
Seat module
Roof module
Door control module
Car access
Gearshift
Seat belt pre-tension
Tail gate
Alarm FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

6 Internal block diagram

7 Pinout information

7.1 Pinout

Figure 8. FS2320 Pin configuration (HVBUCK) Figure 9. FS2300 Pin configuration (HVLDO1) FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

7.2 Pin description

1 HVIO1 Digital input/output High-voltage I/O 1, with wake-up capability

2 HS2 Analog output High-side driver 2

3 HS1 Analog output High-side driver 1

4 V3_IN Analog input V3 regulator input voltage

5 FS0B Digital output Fail-safe output 0 - Active low (low by default)

6 V3 Analog output V3 regulator output voltage

7 CANH Analog input/output CAN bus - CAN high

8 CANL Analog input/output CAN bus - CAN low

9 GNDCAN Ground CAN bus - ground

10 LIN Analog input/output LIN single-wire bus transmitter and receiver

11 GNDLIN Ground LIN bus - ground

12 LIMP0 Digital output LIMP Home mode output 0 - Active low (high by default)

13 FCCU1 Digital Input MCU error monitoring input 1

14 AMUX Analog output Multiplexed output to be connected to an MCU ADC with selection of the analog

15 DEBUG Analog input Debug mode entry and OTP input supply (development only)

16 VDIG Analog output Internal supply decoupling capacitor

17 GND_IO Ground I/Os ground connection

18 LVIO4 Digital input/output Low-voltage IO 4, with wake-up capability

19 LVIO3 Digital input/output Low-voltage IO 3, with wake-up capability

20 LINTXD Digital input Transmitter input from the MCU, which controls the state of the LIN bus

21 LINRXD Digital output Receiver output, which reports the state of the LIN bus to the MCU

22 VDDIO Analog input Input voltage for SPI, I2C, LVIOs and AMUX

23 CANRXD Digital output Receiver output, which reports the state of the CAN bus to the MCU

24 CANTXD Digital input Transmitter input from the MCU, which controls the state of the CAN bus

25 MISO/LVO6 Digital output SPI bus - Master input slave output(MISO)/Low-voltage output 6

26 MOSI/LVI5 Digital input SPI bus - Master output slave input(MOSI)/Low-voltage input 5

27 SCK/SCL Digital input/output SPI bus - Clock input / I2C bus - clock input

28 CSB/SDA Digital input/output SPI bus - Chip select (active low) / I2C bus - bidirectional data line

voltage is monitored in order to detect external reset and fault condition.

30 INTB Digital output Interrupt output

NC NC (FS2300) Not connected. This pin must be left open. V1_B Analog output (FS2300) V1 external PNP base signal. This pin must be left open if no PNP.

33 V1_IN Analog input V1 regulator input voltage

V1_E Analog output (FS2300) V1 external PNP emitter signal. This pin must be left open if no PNP. Table 3. Pin description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

35 WAKE2 Analog input Wake up input 2

36 WAKE1 Analog input Wake up input 1

37 VMON_EXT Analog input External-voltage monitoring input

38 VBOS Analog output Best of supply output voltage

39 V1 Analog output V1 regulator output voltage

40 NC NC Not connected. This pin must be left open.

41 VSUP Analog input Power supply of the device

42 V2_IN Analog input V2 regulator input voltage

43 V2 Analog output V2 regulator output voltage

44 V2_FB Analog input V2 regulator voltage feedback

45 HS4 Analog output High-side driver 4

46 HS3 Analog output High-side driver 3

47 VSHS Analog input High-side drivers and LIN supply

48 HVIO2 Digital input/output High-voltage I/O 2, with wake-up capability

Table 3. Pin description...continued

7.3 Connection of unused pins

1 HVIO1 Digital input/output Open (HVIO1PUPD_OTP = 01)

2 HS2 Analog output Open

3 HS1 Analog output Open

4 V3_IN Analog input VSUP

5 FS0B Digital output Open

6 V3 Analog output Open

7 CANH Analog input/output Open

8 CANL Analog input/output Open

9 GNDCAN Ground Connection mandatory

10 LIN Analog input/output Open

11 GNDLIN Ground Connection mandatory

12 LIMP0 Digital output Open

13 FCCU1 Digital Input GND

14 AMUX Analog output Open

15 DEBUG Analog input Connection mandatory to GND in production (5 V or 8 V authorized for development

16 VDIG Analog output Connection mandatory

17 GND_IO Ground Connection mandatory

18 LVIO4 Digital input/output Open (LVIO4PUPD_OTP = 01)

19 LVIO3 Digital input/output Open (LVIO3PUPD_OTP = 01)

20 LINTXD Digital input Open (200 kΩ internal pull up to VDDIO)

21 LINRXD Digital output Open (push-pull structure)

22 VDDIO Analog input Connection mandatory

23 CANRXD Digital output Open (push-pull structure)

24 CANTXD Digital input Open (200 kΩ internal pull up to VDDIO)

25 MISO/LVO6 Digital output Open

26 MOSI/LVI5 Digital input Open (200 kΩ internal pull up to VDDIO)

27 SCK/SCL Digital input/output Connection mandatory

28 CSB/SDA Digital input/output Connection mandatory

29 RSTB Digital input/output Connection mandatory

30 INTB Digital output Open

33 V1_IN Analog input Connection mandatory

35 WAKE2 Analog input Open (WK2PUPD_OTP = 01)

36 WAKE1 Analog input Open (WK1PUPD_OTP = 01)

37 VMON_EXT Analog input GND

38 VBOS Analog output Connection mandatory

39 V1 Analog output Connection mandatory

40 NC NC Open

41 VSUP Analog input Connection mandatory

42 V2_IN Analog input Open

43 V2 Analog output Open

44 V2_FB Analog input Open (internal pull down)

45 HS4 Analog output Open

46 HS3 Analog output Open

47 VSHS Analog input Connection mandatory

48 HVIO2 Digital input/output Open (HVIO2PUPD_OTP = 01)

8 Limiting values

may cause a malfunction or permanent damage to the device. Debug pin to enter in Debug mode. Table 5. Limiting values [1] Min value is the worst case value at cold temperature (TA = –40 °C). FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9 Electrostatic discharge

or permanent damage to the device. Human body model: AEC-Q100 Rev H. Table 6. ESD ratings FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

10 Thermal characteristics

Table 7. Thermal characteristics application-specific environment. at the package bottom side dead center. package top side dead center. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11 Operating range and current consumption

11.1 Supply voltage

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 8. Supply voltage the safety pins (FS0B, RSTB, LIMP0). action to the safety pins (FS0B, RSTB, LIMP0). It is also used at power up to start the device. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11.2 Current consumption

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 9. Current consumption OTP). This way, the current consumption beneficiates from the ratio between VBAT and V1 output. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12 Functional description

power management, the monitoring of the MCU, and the monitoring of an external IC. the configuration of the device per SPI/I2C.

12.1 Simplified state machine

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

12.2 Operation and power modes

The FS23 provides three main operating modes:

Normal mode is intended to be the fully functional mode. All power supplies are enabled as required by the system, and all system functionalities provided by the FS23 are available. In Normal mode, the monitoring is available and all safety features operate in the device.
LPON mode is the Low-power ON mode, providing support to the minimum system requirements with low current consumption from the battery. During the LPON mode, only V1 regulator (HVBUCK or HVLDO1) remains enabled, by default, to supply the microcontroller rail. For V1 HVBUCK configuration, an LPON- specific output voltage can be configured by OTP, and the regulator operates in PFM mode. For V1 HVLDO1 configuration, only the internal PMOS can be used in LPON mode, and the external PNP is turned OFF. HVLDO2 and HVLDO3 can remain in the same state as in Normal mode, depending on the SPI / I2C configuration. HVIOx and LVIOx only stay active in LPON mode when used as wake-up sources. LPON mode is assumed to be a safe state with no critical activity. Therefore, only monitoring of undervoltage on V1 power rail and MCU watchdog are active to achieve minimum current consumption by the system and FS0B is asserted low.
LPOFF mode is the Low-power OFF mode, with no active system supplies. Logic circuitry is internally supplied to allow proper wake up from any of the available wake-up mechanisms, with the minimum current consumption possible. The system can wake up from any of the Low-power modes via any of the following wake-up mechanisms available in the device:
WAKE1 and WAKE2 pins
HVIOx pins
LVIOx pins (from LPON only)
Long duration timer (LDT) expiration
CAN via wake-up pattern
LIN via wake-up pattern
GO2NORMAL SPI or I2C command via M_SYS_CFG register (from LPON only) The FS23 will also wake up from LPON ...
… in case of repeated watchdog error (WD_ERR_CNT = max)
… in case of pending interrupt for more than TINTB_TO
… in case of external reset event.
Fail-safe mode is intended to be the safe state of the device. It is used to bring the application in a safe state and to protect the FS23, the MCU and the full system in case of failure of the FS23 or the MCU itself. In this mode, all regulators, safety features and systems features are disabled and the safety pins are asserted. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Table 10. Operating modes summary kept active (timeout) in LPON, if previously configured by SPI / I2C. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

12.3 Main state machine description

Power-on reset and power-up sequence The FS23 starts when VBOS > VBOS_POR and VDIG > VDIG_POR. VBOS is the first supply to start. The internal 1.6 V supply of the digital circuitry, VDIG, is generated from VBOS. When VBOS > VBOS_UV, the high-power (HP) analog circuitry is enabled and the OTP registers content is loaded into mirror registers. When VSUP > VSUP_UV , the power-up sequence starts in Slot 0, with at least V1 regulator. The remaining regulators start according to the power-up sequencing configured by OTP. Transition to fail-safe during the power up During the power-up sequence, if VBOS < VBOS_UV, the device goes to Fail-safe mode and all regulators are disabled. If an overvoltage or an overtemperature is detected, the device goes to fail-safe, depending on the OTP configuration. Normal mode When the power up is finished, the main state machine is in Normal mode, which is the application running mode. If VSUP < VSUP_UV, an interrupt is generated but it has no effect on the state machine. If VBOS < VBOS_UV, the device goes to Fail-safe mode. Transitions to low-power modes The device can go to Low-power modes via an SPI/I2C command from the MCU. A GO2LPOFF command will start the power-down sequence to go in LPOFF mode, and a GO2LPON command will start the power-down sequence to go in LPON mode. The device goes into Low-power mode after the power-down sequence to stop all the regulators in the reverse order of the power-up sequence. In case the device goes in LPON, V1 regulator is not shut down and is kept ON. Transition to Fail-safe from Normal mode In case of loss of VBOS (VBOS < VBOS_UV), the device goes directly to Fail-safe mode without power-down sequence. In case of overvoltage detection, or TSD detection on a regulator, depending on OTP configuration, or when the fault error counter reaches its maximum value, the device stops and goes directly to Fail-safe mode without power-down sequence. Fail-safe state exit Three behaviors are configurable by OTP to exit the Fail-safe state:

Automatic restart after TFS_DUR (autoretry feature, configurable by OTP at 100 ms or 4 s)
Semi-automatic restart after TFS_DUR, the device exits Fail-safe state and enters LPOFF states, then waits for a wake-up source to transition to M2 and restart (FS_LPOFF = 1 and KEY_OFFON_EN_OTP = 0).
Restart on Key OFF – Key ON event: Key OFF – Key ON feature is meant to be used when the ignition signal is connected to WAKE1. When enabled, the car driver must turn OFF then ON the ignition signal to restart the device from fail-safe. In this case, the device will only exit fail-safe when WAKE1 = 0 and KEY_OFFON_EN_OTP = 1, and will transition to LPOFF. There, the device will wait for a wake-up event (that is, WAKE1 = 1) to transition to M2 and restart.
This feature requires WAKE1 to be configured as a direct wake-up source. Waking up from Low-power modes When waking up from Low-power modes, it is possible to reduce the startup time by bypassing the M3 state (OTP content loaded in the mirror register) using LOAD_OTP_BYP SPI/I²C bit. This is also valid when exiting fail-safe. When waking up from LPON only, it is possible to bypass slots 1 and 2 if all of the regulators are configured to start in Slot 0. This can be configured by OTP (SLOT_BYP_OTP) or later by SPI/I²C (SLOT_BYP). FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

12.4 Detailed functional state diagram

1 MHz oscillator enabled

20 MHz oscillator enabled

20 MHz oscillator disabled

12.5 INIT state machine

Figure 12. Simplified INIT state diagram programming example, see Section 12.8. To exit the INIT state, LOCK_INIT is cleared by writing 1, and then a good watchdog refresh must be sent. against write access. The cyclic CRC check on the INIT registers is activated, and occurs every 5 ms. watchdog period. If not, the watchdog error counter will be incremented, see Section 19.2.2. if the watchdog is enabled, it must be refreshed every watchdog period. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.6 Power sequencing

sequence of V2 and V3 regulators, as well as I/Os release or assertion. order, starting at SLOT_2 toward SLOT_0. M_REG_CTRL register if they were enabled by OTP. (FS230x), it lasts 500 µs (fixed duration). Slot 1 and Slot 2 always last 500 µs. can also be preconfigured by OTP using SLOT_BYP_OTP bit. Figure 13. Power sequencing FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 14. Power-up sequence example

12.7 Debug and OTP modes

applications or vehicles. OTP mode is intended for OTP emulation and OTP programming. device for production purposes. Debug mode, write 1 in the DBG_EXIT bit in the M_SYS1_CFG register. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.7.1 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 11. Electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

12.8 MCU programming

MCU programming can be done at any time. When the watchdog functionality is enabled by OTP (WD_INF_OTP = 0), NXP recommends extending the watchdog period (up to 1024 ms) or to set it as infinite (window is fully opened) during INIT phase. This will prevent any watchdog error detection and RSTB pin assertion while programming. If the watchdog is not “disabled” (window set as infinite), the user will have to refresh it during the MCU programming. The advised procedure to change the watchdog period to infinite is the following: 1. Make sure the FS23 is in Normal mode by reading M_STATUS register. 2. Send a GO2INIT request by writing in M_SYS_CFG register. 3. Make sure the FS23 is in INIT mode by reading M_STATUS register. 4. Set the infinite watchdog period by writing 4b’0000 in the WDW_PERIOD and WDW_RECOVERY fields in FS_WDW register. 5. Exit INIT mode by clearing the LOCK_INIT bit, then sending a good WD refresh.

12.9 Best of supply

12.9.1 Functional description

The VBOS regulator manages the best of supply from VSUP or V1 (in case V1 is an HVBUCK) to efficiently generate the internal biasing of the device, in every Device mode. VBOS is also the supply of V1 high-side and low-side gate drivers in HVBUCK use case. VBOS undervoltage may not guarantee the full functionality of the device. Consequently, VBOS_UV detection powers down the device by going into Fail-safe state. VBOS is composed of two regulators implemented in parallel: VBOS_HP used to supply the HP analog internal biasing, and VBOS_LP used to supply the internal biasing in Low-Power modes. At power up, VBOS_LP is automatically enabled, and VBOS_HP is enabled later when the HP analog circuitry is enabled. At power up, both VBOS_LP and VBOS_HP are generated from VSUP. In HVBUCK use case only:

In Normal mode, VBOS can be connected to V1 if V1 = 5 V (configurable by OTP + SPI/I2C, using VBOS2V1_SW_ALWAYS_EN bit). In this case, VBOS will stay connected to V1 in LPON mode.
In LPON mode, VBOS can be connected to V1 using VBOS2V1_SW_LP_EN _OTP bit. This feature allows the user to optimize the efficiency, as the current consumption benefits from the VBAT to V1 ratio.
When waking-up from LPON mode, VBOS will stay connected to V1 if VBOS2V1_SW_ALWAYS_EN = 1. In HVLDO1 use case, VBOS is always supplied from VSUP. In LPOFF mode, only VBOS_LP is enabled. The behavior of VBOS regulator is summarized in Figure 18. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

12.9.2 BOS electrical characteristics

TA = –40 °C to 125 °C, unless otherwise specified. VSUP = 4 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 12. Best of supply electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13 Power management

Table 13. FS23 regulators list the V1 regulator can be a BUCK regulator or a linear regulator. configured by OTP for the remaining regulators (LDO2, LDO3).

13.1 HVBUCK: High-voltage buck regulator

13.1.1 Functional description

other local loads inside the ECU. configurable by OTP. Compensation is ensured by internal circuitry. value reflecting the output DC current. voltages is done in PWM mode. undervoltage detection (V1UV_I flag generated). FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers An overcurrent detection is also implemented on the low-side MOSFET, to detect high negative current in case of output short to the battery. In this case, both V1OC_I flag and V1_OCLS_I flag are set and the device transitions to fail-safe depending on OTP configuration using V1_OCLS_EN_OTP. Input voltage range HVBUCK output voltage regulation is guaranteed for a minimum V1_IN, which depends on IBUCK current load. To ensure HVBUCK output voltage regulation, V1_IN should be above (VBUCK + ((Max(RLS_BUCK) + Max(RDCR_LBUCK)) x IBUCK)) / DCMAX_DROP the maximum duty cycle in Dropout mode. For example, with RDCR_LBUCK = 200 mΩ at IBUCK = 400 mA with VBUCK = 3.3 V, the minimal V1_IN is VBUCK + 527 mV. Thermal shutdown When a thermal shutdown is detected, the regulator is disabled and V1TSD_I flag is generated. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

13.1.2 HVBUCK clock management

13.1.2.1 Description

The HVBUCK 450 kHz or 2.2 MHz clock is generated from a 20 MHz internal oscillator. I2C to reduce the emission of the oscillator fundamental frequency.

13.1.2.2 Spread spectrum

MOD_CONF bit. By default, the spread spectrum is disabled, unless configured differently by OTP. internal oscillator and HVBUCK frequency on VBAT frequency spectrum. It is recommended to select the triangular spread spectrum for the best performance.

0 X Disabled

Table 14. Spread spectrum configuration of 19 kHz with -10 %/0 % deviation range of the nominal oscillator frequency. Figure 19. Triangular spread spectrum two random commutations on the carrier slope are added in each half period to increase the spectrum content. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 20. Pseudo-random triangular spread spectrum

13.1.3 Application schematic

Figure 21. HVBUCK schematic with connection to V1_IN

13.1.4 Electrical characteristics

TA = –40 °C to 125 °C, unless otherwise specified. V1_IN = VBUCK_IN (min) to 36 V, unless otherwise specified. All voltages referenced to ground. Table 15. Electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 125 °C, unless otherwise specified. V1_IN = VBUCK_IN (min) to 36 V, unless otherwise specified. All voltages referenced to ground. Table 15. Electrical characteristics...continued FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 125 °C, unless otherwise specified. V1_IN = VBUCK_IN (min) to 36 V, unless otherwise specified. All voltages referenced to ground. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 125 °C, unless otherwise specified. V1_IN = VBUCK_IN (min) to 36 V, unless otherwise specified. All voltages referenced to ground. [1] Average and peak current limits is set dependently, taking into account the inductor value. [2] For all regulators, the effective capacitor value is the capacitor value after Tolerance, DC bias and Aging removal.

13.1.5 HVBUCK efficiency

hardware and OTP configurations listed in Table 16. Table 16. Hardware and OTP configurations FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 16. Hardware and OTP configurations...continued Figure 22. HVBUCK efficiency in force PWM mode

1 Efficiency in force PWM mode, Ta = 25 °C, Vin = 14 V

2 Efficiency in PFM mode, Ta = 25 °C, Vin 14 V

Figure 23. HVBUCK efficiency in PFM mode

13.2 HVLDO1: High-voltage linear regulator 1

13.2.1 Functional description

options is available by part number). The HVLDO1 is low-power capable and stays enabled in LPON mode. The output voltage is configurable by OTP at 3.3 V or 5.0 V. In LPON mode, only the internal PMOS can be used, and external PNP is turned OFF. An overcurrent detection and a thermal shutdown are implemented on LDO1 to protect the internal pass device. The overcurrent detection limits the current in the internal PMOS and by extension in the external PNP, if used. implemented on the PNP base control pin, V1_B, to protect it. state and the regulator only restarts when the device restarts. device can transition to Fail-safe state if configured by OTP. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.2.2 Application schematic

Figure 24. HVLDO1 application schematic, with optional external PNP

13.2.3 Electrical characteristics

unless otherwise specified. All voltages referenced to ground. Table 17. LDO1 electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

unless otherwise specified. All voltages referenced to ground. and from 50 mA to 1 mA in 10 us. Table 17. LDO1 electrical characteristics...continued FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.3 HVLDO2: High-voltage linear regulator 2

13.3.1 Functional description

The HVLDO2 is a high-voltage linear-voltage regulator. The HVLDO2 is commonly supplied from the battery. The output voltage is configurable by OTP at 3.3 V or 5.0 V. it cannot be enabled again by SPI/I2C in this mode. short to the battery. If V2 is used as a local supply, V2_FB is shorted to V2 pin. the regulator by SPI/I2C using the V2DIS bit, and to decide when to enable the regulator using the V2EN bit. When a thermal shutdown is detected, the regulator is disabled and V2TSD_I flag is generated.

13.3.2 Application schematic

13.3.3 Electrical characteristics

unless otherwise specified. ILDO2 = 0 to 100 mA unless otherwise specified. All voltages referenced to ground. Table 18. HVLDO2 electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.4 HVLDO3: High-voltage linear regulator 3

13.4.1 Functional description

The HVLDO3 is a high-voltage linear-voltage regulator. The HVLDO3 is commonly supplied from the battery. The output voltage is configurable by OTP at 3.3 V or 5.0 V. it cannot be enabled again by SPI/I2C in this mode. HVLDO3 can also supply an additional external transceiver on the module. shutdown is detected, the regulator is disabled and V3TSD_I flag is generated.

13.4.2 Application schematic

Figure 26. HVLDO3 application schematic.

13.4.3 Electrical characteristics

unless otherwise specified. ILDO3 = 0 to 100 mA unless otherwise specified. All voltages referenced to ground. Table 19. HVLDO3 electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

unless otherwise specified. ILDO3 = 0 to 100 mA unless otherwise specified. All voltages referenced to ground. Table 19. HVLDO3 electrical characteristics...continued FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14 AMUX: Analog multiplexer

14.1 Functional description

V). An external output capacitor, CAMUX_OUT, is required for the buffer stability.

14.2 Block diagram

Figure 27. AMUX block diagram.

14.3 Channel selection

following formula: T(°C) = (VAMUX – VTEMP25) / VTEMP_COEFF + 25.

14.4 Electrical characteristics

otherwise specified. IAMUX = -1 mA to 1 mA, unless otherwise specified. All voltages referenced to ground.

AMUX_DIV = 0
AMUX_DIV = 1 2.5 4.2 40 V VAMUX_OUT AMUX output-voltage range 0.3 - VDDIO – 0.2 V RPD_AMUX Output pulldown resistance 100 1000 3000 kΩ VAMUX_OFF Offset voltage -7 - +7 mV RAMUX_ACC AMUX ratio accuracy
Ratio 1
Ratio 3
Ratio 10.5 (AMUX_DIV = 0)
Ratio 20 (AMUX_DIV = 1) -0.5 -1.7 -1.9 -1.5 0.5 1.7 1.9 1.5 VTEMP25 Temperature sensor voltage at 25 °C 1.31 1.38 1.45 V VTEMP_COEFF Temperature sensor coefficient -4.074 -3.880 -3.686 mV/°C TAMUX_SET Settling time (from 10 % to 90 % of VDDIO, Rs = 220 Ω, Cout = 10 nF) - - 10 us CAMUX_OUT Output capacitor - - 2 nF RAMUX_OUT Output resistor - 220 - Ohm

15 I/O interface pins

15.1 WAKE1, WAKE2

in combination with an high-side driver (HSx) for cyclic sensing. event, depending on WKx_WUCFG[1:0] bits. can be enabled, disabled, or configured as cell repeater as per WKxPUPD_OTP[1:0] bits. resistor is selected. If the buffer output is high, the pullup resistor is selected.

15.1.1 WAKE1 as input for Key OFF – Key ON feature

WAKE1 pin can be connected to the ignition signal of the vehicle to implement the Key OFF – Key ON feature. = 0. In LPOFF, the device will wait for any wake-up event to restart. Figure 28. Key OFF – Key ON feature description. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15.1.2 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground.

WKx_DGLT = 0
WKx_DGLT = 1 80 μs

Table 22. WAKE12 electrical characteristics [1] There is no digital filtering when WAKEx input pin is used as a source to control an high-side driver.

15.2 HVIO1, HVIO2

as output, the pins provide an open-drain output structure.

15.2.1 HVIO1, HVIO2 used as input

resistor is selected. If the buffer output is high, the pullup resistor is selected. combination or independently of FCCU1 pin. This mechanism is detailed in Section 19.3.

15.2.2 HVIO1, HVIO2 used as output

case, the output state can be controlled by SPI/I2C using HVIOxHI and HVIOxLO control bits. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

and assigned to power sequence slot 1, and HVIO2 default state high assigned to power sequence slot 2. Figure 29. Example of HVIO pins configuration in the slots, at power up functions come in addition to LIMP0 safety output pin, and are described in detail in Section 19.6.6.

15.2.3 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 23. HVIO12 electrical characteristics [1] There is no digital filtering when HVIOx input pin is used as a source to control an high-side driver.

15.3 LVIO3, LVIO4, LVI5, LVO6

sources for the device, or as digital outputs. The MOSI/LVI5 pin can only be used as digital input, and MISO/LVO6 can only be used as digital output. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15.3.1 LVIO3, LVIO4, LVI5 used as input

error detection in combination or independently of FCCU1 pin. This mechanism is detailed in Section 19.3. When the SPI communication interface is used, the MOSI/LVI5 pin, is used a MOSI function. See Section 20.2.

15.3.2 LVIO3, LVIO4, LVO6 used as output

be controlled by SPI/I2C using LVIOxHI and LVIOxLO control bits. LVIO3 default state low and assigned to SLOT_1, and LVIO4 default state high assigned to SLOT_2. Figure 30. Example of LVIO pins configuration in the slots, at power-up. used. In this case, it can be controlled by I2C using LVO6HI and LVO6LO bits. When SPI communication interface is used, MOSI/LVO6 pin is used as MISO function. See Section 20.2. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15.3.3 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 24. LVIOx electrical characteristics [1] There is no digital filtering when LVIOx input pin is used as a source to control an high-side driver.

15.4 I/Os configuration summary

The following table summarizes the available I/Os configurations. Table 25. I/Os configurations

15.5 INTB

interrupt occurs to inform the MCU. Each interrupt can be masked by setting the corresponding inhibit interrupt.

15.5.1 Interrupts and wake-up events management

The “classic” interrupts used to diagnose the device state and to report events FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

The wake-up interrupts used to manage the wake-up from the Low-Power modes The list of all the interrupts is given in Table 26. The “classic” interrupts are maskable. If the interrupts are not masked, a pulse will be generated on the INTB pin. Out of Normal mode, most of these interrupt flags will not be generated, because the monitoring functions associated will be disabled. In addition, the WKx_I, HVIOx_I, LVIOx_I, and LVI5_I flags are not generated out of Normal mode. The I/Os are considered as wake-up sources, with the CAN, LIN, and LDT. A wake-up event on these functions will generate a non-maskable wake-up flag (xxxx_WU_I). An interrupt pulse will be generated on INTB if the wake-up source is enabled following SPI/I2C configuration (xxxx_WUEN[1:0] bits). Each wake-up source can be configured to generate an interrupt, a transition to Normal mode, or both. In LPON mode, if a wake-up event occurs and the wake-up source is enabled, an interrupt is generated, and/ or the device transitions to Normal mode. If only the interrupt generation is enabled, it is the MCU's decision to request a transition to Normal mode or not, via GO2NORMAL SPI/I2C bit. In LPOFF mode, if a wake-up event occurs and the wake-up source is enabled, the device transitions to Normal mode.

15.5.2 Electrical characteristics

voltages referenced to ground. Table 26. INTB electrical characteristics Table 27. List of interrupts from main logic FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

16 High-side drivers

16.1 Functional description

The FS23 provides four high-side drivers, supplied by VSHS supply voltage. Each high-side driver (HSx) can be used to drive loads, such as LEDs, or to perform cyclic sense in combination with a high-voltage input (WAKEx, HVIOx). Each HSx can be controlled by different sources, configurable by SPI/I2C (HSx_SRC_SEL):

HSx_EN and HSx_DIS SPI/I2C control bits
Any input (WAKEx, HVIOx, LVIOx, LVI5)
One of the TIMERx (x = 1, 2, 3) for cyclic sense
One of the PWMx (x = 1, 2, 3) for LED driving Undervoltage and overvoltage is implemented on the HSx supply VSHS. In case of under/overvoltage detection, all the HSx are kept enabled or disabled depending on SPI/I2C configuration via HS_VSHSUV_DIS and HS_VSHSOV_DIS bits. When the HSx are disabled because of a UV/OV on VSHS, an automatic recovery of the HSx functions is possible if enabled via HS_VSHSUVOV_REC bit. If not, the MCU will enable the HSx again. The HSx are monitored by pair for overtemperature. If the temperature of HS1 or HS2 rises above the overtemperature threshold, HS12_TSD_I flag is generated. If the temperature of HS3 or HS4 rises above the overtemperature threshold, HS34_TSD_I flag is generated. All four HSx are also monitored individually for overcurrent (short-circuit detection) and open load. When an overcurrent is detected, a flag is generated (HSx_OC_I) and the concerned high-side driver is disabled. When an open load is detected, a flag is generated (HSx_OL_I).

16.2 LED driving

The high-side drivers can be used to drive LEDs, with one of the three PWMs configured as source. The frequency of each PWM is configurable between 200 Hz and 400 Hz (PWMx_F), and the duty cycle is configurable on 10 bits from 0 % to 100 % (PWMx_DC[9:0]). A configurable delay (PWMx_DLY) can be applied to both the rising and falling edges of each PWMx in order to limit the inrush current on VSHS supply if multiple HSx are used with a PWM at the same time. LED driving is controlled by SPI/I2C using PWMx_EN bits.

16.3 Cyclic sense

The high-side drivers can be used for cyclic sense, with one of the three TIMERs configured as source and one of the high-voltage inputs among WAKE1, WAKE2, HVIO1, and HVIO2 configured as a sensing input. Cyclic sense is enabled by SPI/I2C using TIMx_EN bits. Both the period and the ON time of each TIMER are configurable by SPI/I2C using TIMERx_PER[2:0] and TIMERx_ON[3:0] bits. The period is configurable from 10.24 ms to 2048 ms and the ON time is configurable from 0.128 ms to 204.8 ms. A configurable delay (TIMERx_DLY) can be added to both the rising and falling edges of each TIMERx in order to limit the inrush current on the VSHS supply if multiple HSx are used with a TIMER at the same time. When used for cyclic sense, an HSx is turned ON following the ON time of the associated TIMERx. At the end of each ON time, at each falling edge, the state of the high-voltage input pin is sampled and stored for one period. If two successive samples show different states, a flag is generated. See Figure 31. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

16.4 Electrical characteristics

Table 28. High-Side drivers electrical characteristics...continued [1] On resistive short-circuit. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

17 Long duration timer

calibration mechanism for oscillator compensation. The timer is based on a 24-bit counter, with a 1 MHz/64-input clock, allowing a 1.0 second time base.

1 MHz

Figure 33. Long duration timer block diagram the prescaler 2 is bypassed and the timer can count up to 36 minutes, with 128 µs resolution. Table 29. Long duration timer characteristics The LDT has two modes of operation based on the prescaler used during the count.

When LDT_MODE = 0, the LDT is set in long count mode.
When LDT_MODE = 1, the LDT is set in short count mode. The LDT_AFTER_RUN[15:0] bits are used to set or to read the after-run target value in Normal mode. The LDT_WUP_H[7:0] and the LDT_WUP_L[15:0] bits is used to set or to read the wakeup target value, in combination with the LDT_SEL bit:
LDT_WUP_H[7:0] contains the eight most significant bits of the wake-up target value.
LDT_WUP_L[15:0] contains the 16 least significant bits of the wake-up target value. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers The LDT_SEL bit allows the MCU to either set/read the wake-up target value or to read the current value of the 24 bit LDT counter in the LDT_WUP_H[7:0] and the LDT_WUP_L[15:0] bits.

When LDT_SEL = 0, the MCU can read or write the wake-up target value in the LDT_WUP_H[7:0] and the LDT_WUP_L[15:0] bits.
When LDT_SEL = 1, the MCU can read the counter current value (running or not). The LDT_EN bit is provided to start the LDT timer operation:
When LDT_EN = 0, the LDT is disabled.
When LDT_EN = 1, the LDT starts counting as defined in the M_LDT_CTRL and M_LDT_CFGx registers. The LDT2LP bit selects which Low-power mode (LPON or LPOFF) it needs to go once the after-run timer is expired, when timer function 2 or 3 is selected.
When LDT2LP = 0, the device goes into LPOFF mode when the after-run timer expires.
When LDT2LP = 1, the device goes into LPON mode when the after-run timer expires.
When timer function 4 or 5 is selected and the LDT_EN = 1, the LDT does not start any count until the device enters the corresponding Low-Power mode.

17.1 Calibration procedure

The calibration principle consists of activating the counter for a specific duration and comparing the timing given by the LDT with the MCU's accurate clock and timing. Once the timer expires, the MCU reads back the final timer value and compares it that value with its own accurate time of activation to calculate a time offset. It is recommended to perform the calibration between -20 °C and 85 °C. Calibration example: 2. Start the counter. 3. Read the counter when the MCU RTC reaches 7 s (must be less than 7.5 s with ±10.0 % oscillator accuracy). 4. If the oscillator period is at the exact typical value (absolutely no deviation error), the expected reading is 54688. 5. The exact reading is used to compute the error correction factor ECF = exact_reading/expected_reading.

ECF < 1 if the oscillator is faster than the exact typical value.
ECF > 1 if the oscillator is slower than the exact typical value. After calibration, the new after-run or wake-up values to set the counter are “after run x ECF” and “wake-up x ECF”. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

17.2 Timer functions

000 Function 1: In Normal mode, count and generate a flag or an interrupt when the counter

reaches the after-run value.

001 Function 2: In Normal mode, count until the counter reaches the after-run value and enters

010 Function 3: In Normal mode, count until the counter reaches the after-run value and enters

011 Function 4: In Low-Power mode, count until the counter reaches the wake-up value and

100 Function 5: In Low-Power mode, count and do not wake up unless the counter overflow

occurs or if the device wakes up by wake-up input source. Table 30. LDT functions Figure 34. Long duration timer functions FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

17.3 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 18.0 V, unless otherwise specified. All voltages referenced to ground. Symbol Description Min Typ Max Unit

Electrical characteristics

FIN_CLK_LDT Long duration timer source clock (1 MHz/64) - 15.625 - kHz TBASE_LDT Long duration timer time base LDT_MODE = 0 (long) LDT_MODE = 1 (short) 0.909 116.4 128 1.11 142.1 s µs IQ_LDT_85 Long duration timer quiescent current consumption (Tj = 85 °C) - 2 5 µA IQ_LDT_125 Long duration timer quiescent current consumption (Ta = 125 °C) - 5 10 µA LDTACC1 Long duration timer accuracy without calibration -10 - 10 % LDTACC2 Long duration timer accuracy with calibration In LPOFF or LPON states Including one month aging drift (max) Including temperature drift 0 °C < ∆Tj < 85 °C -5 - 5 % LDTDRIFT Long duration timer maximum drift per hour after calibration In LPOFF or LPON states Within 20 °C temperature variation. -1 - 1 % Table 31. Long duration timer characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18 Physical layers

18.1 CAN FD transceiver

MCU and the physical CAN bus. The CAN FD transceiver bus driver is supplied internally by the V3 regulator. Figure 35. CAN FD transceiver internal diagram, with external components

18.1.1 CAN operating modes

in Wake-capable mode in order to be used as a wake-up source for the device and the module. FS0B, or LIMP0 is asserted in Normal mode. This can be configured by SPI/I2C using CAN_FS_DIS bit. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 36. CAN transceiver state machine

18.1.1.1 CAN Off mode

CANH and CANL pins are set high ohmic, and the CANRXD pin is driven high.

18.1.1.2 CAN Wake-capable mode

the wake-up capability of the CAN is enabled, regardless of the device state once powered up. biased to ground via the Common mode input resistor RCAN_IN_CM and the CANRXD pin is driven high. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.1.1.3 CAN Wake-up

Figure 37. CAN Wake-up timing diagram

18.1.1.4 CAN Listen-only mode

device must be in Normal mode and no undervoltage on V3 must be detected. pullup resistor RCANTXD_ PU connected to VDDIO.

18.1.1.5 CAN Active mode

Listen-only mode and the transmitter is disabled. device can transmit information from CANTXD to the CAN bus and report the bus level to the CANRXD pin. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 38. CAN timing definition according to ISO 11898-2:2016

18.1.2 Electrical characteristics

unless otherwise specified. VDDIO = 3 V to 5.5V, unless otherwise specified. All voltages referenced to ground. Table 32. CAN FD transceiver characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

unless otherwise specified. VDDIO = 3 V to 5.5V, unless otherwise specified. All voltages referenced to ground. Table 32. CAN FD transceiver characteristics...continued FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

unless otherwise specified. VDDIO = 3 V to 5.5V, unless otherwise specified. All voltages referenced to ground. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

unless otherwise specified. VDDIO = 3 V to 5.5V, unless otherwise specified. All voltages referenced to ground.

18.2 LIN transceiver

provides the physical interface between the LIN controller of an MCU and the physical LIN bus. Figure 39. LIN transceiver internal diagram

18.2.1 LIN operating modes

kept in Wake-capable mode in order to be used as a wake-up source for the device and the module. LIMP0 is asserted. This can be configured by SPI/I2C using LIN_FS_DIS bit. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 40. LIN transceiver state machine

18.2.1.1 LIN Off mode

the LINRXD pin is driven high.

18.2.1.2 LIN Wake-capable mode

wake-up capability of the LIN is enabled, regardless of the device state once powered up. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.2.1.3 LIN Wake-up

Figure 41. LIN wake-up timing diagram

18.2.1.4 LIN Listen-only mode

18.2.1.5 LIN Active mode

2b’10 or 2b’11 and LINTXD is high. The device must be in Normal mode. In Active mode, the normal receiver and the transmitter are enabled, and the low-power receiver is disabled. The device can transmit information from LINTXD to the LIN bus and report the bus level to the LINRXD pin. by a rising edge on LINTXD pin. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 42. Timing diagram of LIN duty cycle

18.2.2 Electrical characteristics

5.5V, unless otherwise specified. All voltages referenced to ground. Table 33. LIN transceiver characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

5.5V, unless otherwise specified. All voltages referenced to ground.

7.6 V to 18 V, TLIN_BIT = 50 µs, D2 = TBus_rec(max)/(2 x TLIN_BIT)

5.5V, unless otherwise specified. All voltages referenced to ground.

7.6 V to 18 V, TLIN_BIT = 96 µs, D4 = TBus_rec(max)/(2 x TLIN_BIT)

19 Safety

19.1 Functional description

the application needs. The FS23 also provides an on-demand ABIST to cover latent faults. Figure 43. Fail-safe features block diagram

19.2 Watchdog

always considered as infinite. There is no need to refresh the watchdog, except to release the safety pins. during INIT phase). When enabled in LPON, the watchdog operates in Timeout mode. stored in the WD_TOKEN register, and is changed alternatively after each good WD refresh. is wrong or not given at the right moment, or not given at all at the end of the watchdog period. MCU must refresh the watchdog every period. watchdog disable is effective when the INIT phase is closed. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0000 Disable (infinite open window)

Table 34. Watchdog window period configuration

19.2.1 Watchdog selection

changed during operation by SPI/I2C using WDW_EN bit.

0 Timeout watchdog (default)

1 Window watchdog

Table 35. Watchdog type configuration

19.2.1.1 Timeout watchdog

incremented and WD_NOK_I flag is set to 1.

19.2.1.2 Window watchdog

Figure 44. Window watchdog time diagram Table 36. Watchdog answer and refresh validation

19.2.2 Watchdog error counter

converges to a failure detection. WD_ERR_LIMIT[1:0] bits during the INIT phase. Table 37. Watchdog error counter limit configuration The watchdog error counter value can be read by the MCU for diagnostic with the WD_ERR_CNT[3:0] bits. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 45. Watchdog error counter configurations

19.2.3 Watchdog refresh counter

watchdog refresh counter is reset to ’0’. the WD_RFR_LIMIT[1:0] bits during the INIT_FS phase. Table 38. Watchdog refresh counter limit configuration The watchdog refresh counter value can be read by the MCU for diagnostic with the WD_RFR_CNT[2:0] bits. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 46. Watchdog refresh counter configurations

19.2.4 Watchdog error impact

INIT phase. If it happens in LPON mode, the device also wakes up.

0 No effect on the pin

Table 39. Watchdog error impact configuration

19.2.5 MCU fault recovery strategy

0000 DISABLE (Infinite window, fully open)

Table 40. Watchdog window in fault recovery configuration then a reset pulse is generated and the device goes to Fail-safe state. Figure 47. Fault recovery strategy principle FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.2.6 Watchdog electrical characteristics

Table 41. Watchdog electrical characteristics

19.3 FCCU monitoring

charge of monitoring the error signals of the MCU fault collection and control unit. can be configured as FCCU2 pin, via FCCU2_ASSIGN[2:0] bits, in INIT phase.

000 No monitoring

010 FCCU1 or FCCU2 single input level monitoring activated

011 FCCU1 input level monitoring only, FCCU2 input not used

100 FCCU2 input level monitoring only, FCCU1 input not used

101 FCCU1 or FCCU2 single input PWM monitoring activated

110 FCCU1 input PWM monitoring only, FCCU2 input level monitoring

111 FCCU2 input PWM monitoring only, FCCU1 input level monitoring

Table 42. FCCU monitoring configuration

19.3.1 FCCU12 monitoring by pair

The polarity of the FCCU fault signals is configurable with FCCU12_FLT_POL bit during the INIT_FS phase.

1 FCCU1 = 1 or FCCU2 = 0 level is a fault

Table 43. FCCU12 polarity configuration configurable with the FCCU1_RSTB/FS0B/LIMP0_IMPACT bits during the INIT phase. Table 44. FCCU12 error impact configuration

19.3.2 FCCU1, FCCU2 independent monitoring

independent error signals. These error signals can be either steady-state level signals or PWM signals. with FCCUx_FLT_POL bits during the INIT phase.

1 FCCU1 high level is a fault

1 FCCU2 high level is a fault

Table 45. FCCUx polarity configuration FCCUx_RSTB/FS0B/LIMP0_IMPACT bits during the INIT phase. Table 46. FCCUx error impact configuration FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 46. FCCUx error impact configuration...continued

19.3.3 FCCU12 electrical characteristics

Table 47. FCCU12 electrical characteristics

19.4 Voltage supervisor

then reported accordingly. V0MON monitoring on VMON_EXT pin is enabled by OTP (V0MON_EN_OTP).

19.4.1 V0MON (VMON_EXT) monitoring

resistor bridge must be used to divide the regulator voltage if higher than 1 V, and set the middle point to 1 V. thresholds accuracy (±1.5 %). FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.4.2 VxMON monitoring (x from 1 to 3)

V1 and V3 regulators are monitored via the corresponding V1 and V3 pins, which also serve as feedback pins. configured by OTP (VxMON_OTP), separately from the output voltage and must be configured the same. The VxMON threshold have ±1.5 % UV/OV accuracy (trimmed at 5 V setting, 5.0 % VxMON threshold).

19.4.3 VxMON UV/OV threshold

additional UV thresholds are available at 61 %, 62 %, 62.5 %, 63 %, and 64 %. Table 48. VxMON UV/OV threshold configuration FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.4.4 VxMON deglitch time

Table 49. VxMON deglitch time

19.4.5 VxMON safety reaction (impact)

input. The reactions of RSTB pin can be pre-selected by OTP.

19.4.6 V1UVLP monitoring

configurable), and V1_UVLP_WU bit is set to 1.

19.4.7 Electrical characteristics

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 50. VxMON electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 50. VxMON electrical characteristics...continued

19.5 Fault management

19.5.1 Fault error counter

LIMP0_IMPACT bits configuration (INIT phase). Table 52. Fault error counter fail-safe impact Figure 49. Fault Error Counter diagram with maximum value = 2 or 6 FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 50. Fault Error Counter diagram with maximum value = 8 or 12

19.5.2 Fault source and reaction

LIMP0 will not increment the fault error counter. In that case, only the flags are available for MCU diagnostic. The fault error counter is incremented by 1, each time the RSTB and/or FS0B and/or LIMP0 pin is asserted. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

SPI / I²C for FS0B/LIMP0 in INIT mode. Table 53. Application related fail-safe fault list and reaction FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.5.3 Fail-Safe mode

The fault error counter reaches its maximum value (not configurable)
VBOS UV is detected
RSTB is asserted low for 8 s (if enabled by OTP)
VxOV is detected (if configured by OTP)
VxTSD is detected (if configured by OTP)
Negative overcurrent (V1_OC_LS) is detected in HVBUCK version (if enabled by OTP)
OC timeout is detected in HVLDO1 version used with external PNP
V1UVLP is detected in LPON mode or during transition from LPON mode to Normal mode
When the first fault is detected (if configured by OTP) In Fail-Safe mode, all the regulators are turned off, the high-power analog circuitry in enabled, the 20 MHz oscillator is enabled, the OV/UV monitoring is turned on, and the FS_EVT bit is set to 1. The fault error counter is reset to 1. The device exits the Fail-Safe state after TFS_DUR time. If FS_LPOFF_OTP bit is set to 1 or if KEY_OFFON_EN_OTP bit is set to 1, the device exits FS state and goes to LPOFF. Otherwise, the device goes back automatically to the power-up sequence. TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Fail-Safe TFS_DUR Fail-Safe state duration
FS_DUR_CFG_OTP = 0
FS_DUR_CFG_OTP = 1 3.6 100 4.0 110 4.4 ms s

Table 54. Fail-Safe state electrical characteristics

19.6 RSTB, FS0B, LIMP0/1/2

system. All those safety outputs are active low. RSTB and FS0B are activated during power up and can only be released when the device is in Normal mode. LIMP0, on the contrary, will be released at startup and will only be asserted when a fault occurs. The three pins are managed independently in parallel of the main state machine.

19.6.1 RSTB

Figure 51. RSTB pin implementation TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Table 55. RSTB electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.6.2 FS0B

asserted at MCU request by SPI/I2C, to check the correct hardware connection. Figure 52. FS0B pin implementation Table 56. FS0B electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19.6.3 FS0B release

No fault affecting FS0B reported
Fault error counter = 0
Device in Normal mode
Device not in Debug mode and not in INIT mode
FS_FS0B_LIMP0_REL register filled with the correct value, depending on current WD_TOKEN[15:0] value as Table 57: FS_FS0B_ LIMP0_REL[15:0] B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Release FS0B 0 1 1 NOT(WD_TOKEN[0:12]) Release LIMP0 1 1 0 NOT(WD_TOKEN[3:15]) Release both FS0B and LIMP0 1 0 1 NOT(WD_TOKEN[0:6]) NOT(WD_TOKEN[10:15])

Table 57. FS0B and/or LIMP0 release commands

19.6.4 LIMP0

(LPON and LPOFF), LIMP0 works like in Normal mode. GUN and ISO 7637 transient pulses. A weak internal pulldown RPD ensures LIMP0 low level in case of pin lift. An internal pulldown RPD_STUP ensures LIMP0 is released at startup. request by SPI/I2C, to check the correct HW connection. Figure 53. LIMP0 pin implementation Table 58. LIMP0 electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 58. LIMP0 electrical characteristics...continued

19.6.5 LIMP0 release

No fault affecting LIMP0 reported
Fault error counter = 0
Device in Normal mode
Device not in INIT mode
FS_FS0B_LIMP0_REL register filled with the correct value, depending on current WD_TOKEN[15:0] value as per Table 57.

19.6.6 LIMP1, LIMP2

HS3 can be configured as LIMP2 function. and LIMP2 paths can also be checked by the MCU by requesting their assertion by SPI/I2C. asserted, depending on LIMPx_CFG[1:0] bit. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

duty cycle is configurable between 2.5 %/5 %/10 %/20 % using LIMP2_DC_CFG[1:0] bit. Table 59. LIMP1, LIMP2 electrical characteristics

19.7 Analog built-in self-test (ABIST)

The diagnostic flags must be cleared before launching the next ABIST, using the CLEAR_ABIST bit. ignored. While the ABIST is running, the other monitoring functions are kept available. Table 60. ABIST electrical characteristics

19.8 Periodic CRC check

detection of a misconfiguration from the MCU or a bit flip in the INIT registers.

FS_I_OVUV_CFG1[12:7], FS_I_OVUV_CFG1[5:0]
FS_I_OVUV_CFG2[12:7], FS_I_OVUV_CFG2[5:0]
FS_I_FCCU_CFG[14:0]
FS_I_FSSM_CFG[14:4] FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

FS_I_WD_CFG[14:7] The calculation to apply on the result of the concatenation is the same as the SPI/I2C CRC, using x^8+x^4+x^3+x^2+1 polynomial. The MCU must write the obtained CRC in the FS_CRC register before closing the INIT phase, after the modification of the INIT registers. Once the INIT phase closes and the device is in Normal mode, the periodic CRC check is launched automatically each 5 ms (TCRC) (<FTTI). Each 5 ms, the device logic recalculates the CRC and compares it to the value stored in FS_CRC register. If a mismatch is reported, the INIT_CRC_NOK_I bit is set and the safety outputs FS0B or LIMP0 are asserted depending on their impact configuration (INIT_CRC_FS0B_IMPACT and INIT_CRC_LIMP0_IMPACT). TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit Cyclic CRC check TCRC CRC check timing interval - - 5.5 ms TCRC_RUN CRC maximum computation time - - 80 µs

Table 61. Cyclic CRC check characteristics

19.9 Clock monitoring

20 MCU communication

diagnostic, in Normal and LPON modes. The choice of the interface is done by OTP. respectively as SCL and SDA signals, and pins 25 and 26 are available as LVO6 and LVI5 digital I/Os. MISO, MOSI, SCK, and CSB pins.

20.1 I2C communication interface

20.1.1 I2C interface overview

The I2C interface uses the VDDIO pin as power input and it is compatible with 3.3 V and 5.0 V input supply. Timing, diagrams, and further details can be found in the NXP I2C specification. Refer to UM10204 Rev. 7.

0 ADR[6:0] DATA[15:8]

0 Register address Data MSB

Table 62. I2C message construction Bit B32 must be set to 0 to execute a write command, and to 1 to execute a read command.

The first access is the request with the device address and the register address.
The second access is the answer with the data contained in the register and the CRC. First access Second access Device address + R/W 0b0 + Register address Device address + R/W Data 8-bit CRC 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0x40 0x06 0x41 0x0009 0x5F

SAE-J1850 (identified by 0x1D) with a SEED value of hexadecimal '0xFF'.

20.1.2 Device address

Bit 39: 0
Bit 38: 1
Bit 37 to 34: OTP value
Bit 33: 0 B39 B38 B37 B36 B35 B34 B33 0 1 I2CDEVADDR_OTP[3:0] 0

Table 64. Device address

20.1.3 I2C CRC calculation and results

20.1.4 Electrical characteristics

V, unless otherwise specified. All voltages referenced to ground. Table 66. Electrical characteristics

20.2 SPI communication

The FS23 provides a 32-bit SPI interface, as alternative to the I2C interface (SPI_EN_OTP = 1).

20.2.1 SPI interface overview

Bits 31 to 25: register address
Bit 24: Read/Write (for reading Bit 24 = 0; For writing Bit 24 = 1)
Bits 23 to 8: control bits
Bits 7 to 0: CRC MISO bits
Bits 31 to 24: general device status
Bits 23 to 8: device internal control register content
Bits 7 to 0: CRC The digital SPI pins (CSB, SCLK, MOSI, MISO) are referenced to VDDIO. The MCU is the master driving MOSI and FS23 is the slave driving MISO. The MISO data is latched at the SCLK rising edge and MOSI data is latched at the SCLK falling edge. MSB first.
In write command, MISO [31:24] bits are the general status flags, [23:8] bits are register’s content before Write access and MISO [7:0] is the CRC of the message sent by the FS23.
In read command, MOSI [23:8] bits are all 0 and MOSI [7:0] is the CRC of the message sent by the MCU. Table 67 and Table 68 describe SPI communication protocol for writing data into the FS23 or reading data from the FS23. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Table 67. SPI write command message construction Table 68. SPI read command message construction

20.2.2 SPI status bits

0 No event reported in M_HSx_FLG or M_CS_FLG_MSK registers

1 An interrupt or flag is present in M_HSx_FLG or M_CS_FLG_MSK registers

0 No event reported in FS_SAFETY_FLG register

1 Safety-related interrupt or flag present in FS_SAFETY_FLG register

30 SAFETYG

0 No event present reported in M_CAN or M_LIN registers

1 An interrupt or flag is present in M_CAN or M_LIN registers

29 PHYG

0 No event reported in M_IOWU_FLG or M_WU1_FLG registers

1 An interrupt or flag is present in M_IOWU_FLG or M_WU1_FLG registers

0 No event reported in M_IO_TIMER_G register

1 An interrupt or flag is present in M_IO_TIMER_G register

27 IOTIMG

0 No event reported into M_VSUP_COM_FLG register

1 An interrupt or flag is present in the M_VSUP_COM_FLG register

26 COMG

25 VSUPG

0 No event reported into M_REG_FLG and M_REG1_FLG registers

1 An interrupt or flag is present in M_REG_FLG or M_REG1_FLG register

24 VxG

20.2.3 Cyclic redundant check

by 0x1D) with a SEED value of hexadecimal '0xFF'. Figure 54. CRC encoder example

20.2.3.1 CRC encoding procedure

significant bits of the shift register. Table 70. Data preparation for CRC encoding

Using a serial CRC calculation method, the transmitter rotates the seed and data into the least significant
During the serial CRC calculation, the seed and the data bits are XOR compared with the polynomial data

CRC byte all equal to zero (00000000).

Once the CRC is calculated, it replaces the CRC byte initially set to all zeros and is transmitted.

20.2.3.2 CRC decoding procedure

The seed value is loaded into the most significant bits of the receive register.
Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least

significant bits of the shift register in the order received (MSB first).

When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the

If the shift register contains all zeros, the CRC is correct.
If the shift register contains a value other than zero, the CRC is incorrect. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

20.2.4 Electrical characteristics

V, unless otherwise specified. All voltages referenced to ground. Table 71. SPI electrical characteristics FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

21 SPI/I2C register mapping

Table 72. Main register mapping...continued Table 73. Safety-related register mapping FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

21.1 Register map overview

0 BAT_FAIL 0 POR 0 LOCK_INIT GO2INIT GO2

0 LOAD_

0 SOFTPOR_

0 DBG_EXIT DBG_

0 OTP_EXIT OTP_

0 VSHS_

0 HVIO2_

0 LDT_WU_I LIN_WU_I CAN_WU_I 0x0000

0 HVIO2_HS_SEL HVIO1_HS_SEL WK2_HS_SEL WK1_HS_SEL 0x0000

0 HS_

0 HS2_OL_I HS2_OC_I 0 HS1_OL_I HS1_OC_I HS12_

0 HS2_OL_M HS2_OC_M 0 HS1_OL_M HS1_OC_M HS12_

0 CAN_

0 CAN_FSM_STATE_S CAN_TXD_

0 V2MON_

0 V0MON_

0 FCCU_CFG FCCU2_ASSIGN FCCU12_

0 EXT_

0 WD_

0 LIMP1_CFG LIMP1_

0 ABIST_

0 RSTB_EXT RSTB_EVT RSTB_DRV RSTB_SNS RSTB_

0 CRC_VALUE 0x0000

22 SPI/I2C register description

22.1 M_DEV_CFG

Table 75. M_DEV_CFG register bit allocation

0 VMON_EXT is disabled

1 VMON_EXT is enabled

2 V0MON_EN

0 LIMP0 is disabled

1 LIMP0 is enabled

3 LIMP0_EN

0 FS0B is disabled

1 FS0B is enabled

4 FS0B_EN

0 FCCU is disabled

1 FCCU is enabled

5 FCCU_EN

0 ABIST on demand is disabled

1 ABIST on demand is enabled

6 ABIST_EN

0 V1 PNP mode is disabled

1 V1 PNP mode is enabled

7 V1_PNP_EN

0 V2 regulator is disabled by OTP

1 V2 regulator is enabled by OTP

8 V2_EN

0 HS2 and HS4 are disabled

1 HS2 and HS4 are enabled

9 HSD24_EN

0 HS1 and HS3 are disabled

1 HS1 and HS3 are enabled

10 HSD13_EN

0 LDT is disabled

1 LDT is enabled

11 LDTIM_EN

0 The LIN is disabled

1 The LIN is enabled

12 LIN_EN

0 The CAN is disabled

1 The CAN is enabled

13 CAN_EN

Table 76. M_DEV_CFG register bit description...continued

22.2 M_DEV_PROG_ID

Table 77. M_DEV_PROG_ID register bit allocation Table 78. M_DEV_PROG_ID register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0000 Rev A0 (Default full layer revision)

0001 Rev X1

0010 Rev X2

0011 Rev X3

0100 Rev X4

0101 Rev X5

0110 Rev X6

0111 Rev X7

1000 Rev X8

1001 Rev X9

1010 Rev X10

1011 Rev X11

1100 Rev X12

1101 Rev X13

1110 Rev X14

1111 Rev X15

0000 Unused

0001 Pass A silicon

0010 Pass B silicon

0011 Pass C silicon

0100 Pass D silicon

0101 Pass E silicon

0110 Pass F silicon

0111 Pass G silicon

1000 Pass H silicon

1001 Pass I silicon

1010 Pass J silicon

1011 Pass K silicon

1100 Pass L silicon

1101 Pass M silicon

1110 Pass N silicon

1111 Pass O silicon

22.3 M_GEN_FLAG

Table 79. M_GEN_FLAG register bit allocation

0 No event

1 Vx event occurred

0 VxG

0 No error

1 VSUP error reported

1 VSUPG

1 Communication error reported

2 COMG

3 IOTIMG

1 Wake up event occurred

4 WUG

1 CAN or LIN error reported

5 PHYG

0 No error6 SAFETYG

1 Watchdog Refresh error reported

7 HSxG

Table 80. M_GEN_FLAG register bit description...continued

22.4 M_STATUS

Table 81. M_STATUS register bit allocation

0 V3 is disabled

1 V3 is enabled

0 V3_S

0 V2 is disabled

1 V2 is enabled

1 V2_S

0 V1 is disabled

1 V1 is enabled

2 V1_S

0 HVBUCK is in PWM mode or HVLDO1 PNP is enabled

1 HVBUCK is in PFM mode or HVLDO1 PNP is disabled

3 V1_MODE

0 LVIO3 is low

1 LVIO3 is high

4 LVIO3_S

0 LVIO4 is low

1 LVIO4 is high

5 LVIO4_S

0 LVI5 is low

1 LVI5 is high

6 LVI5_S

0 HVIO1 is low

1 HVIO1 is high

7 HVIO1_S

0 HVIO2 is low

1 HVIO2 is high

8 HVIO2_S

0 WAKE1 is low

1 WAKE1 is high

9 WK1_S

0 WAKE2 is low

1 WAKE2 is high

10 WK2_S

0 Device is not in INIT mode

1 Device is in INIT mode

12 INIT_S

0 Device is not in Normal mode

1 Device is in Normal mode

13 NORMAL_S

0 Device is not in LPON mode

1 Device is in LPON mode

14 LPON_S

0 V1 temperature is < TWARNV1

1 V1 temperature is > TWARNV1

15 V1TWARN_S

22.5 M_SYS_CFG

Table 83. M_SYS_CFG register bit allocation

0 Spread spectrum is disabled

1 Spread spectrum is enabled

0 MOD_EN

0 Triangular modulation is selected

1 Pseudo random modulation is selected

1 MOD_CONF

0 INTB pulse = 25 us

1 INTB pulse = 100 us

3 INTB_DUR

0 No effect

1 INTB pulse is requested

4 INTB_REQ

0 Interrupt time-out wake-up capability is disabled

1 Interrupt time-out wake-up capability is enabled

5 INT_TO_WUEN

0 No action

1 Go to LPOFF mode

6 GO2LPOFF

1 Go to LPON mode

7 GO2LPON

1 Go to Normal mode

8 GO2NORMAL

1 Go to INIT phase

9 GO2INIT

0 Exit INIT phase is possible

1 Device locked in INIT phase

10 LOCK_INIT

0 No POR event

1 Digital POR event occurred

12 POR

0 No battery failure event

1 Battery failure event occurred

14 BAT_FAIL

Table 84. M_SYS_CFG register bit description...continued

22.6 M_SYS1_CFG

Table 85. M_SYS1_CFG register bit allocation

0 Device is not in OTP mode

1 Device is in OTP mode

0 OTP_MODE

1 Exit OTP mode

1 OTP_EXIT

0 Device is not in Debug mode

1 Device is in Debug mode

3 DBG_MODE

1 Exit Debug mode

4 DBG_EXIT

1 Software POR is requested

6 SOFTPOR_REQ

0 TSLOT = 2 ms

1 TSLOT = 0 ms

8 TSLOT_DOWN_CFG

0 Slot 1 and Slot 2 are not bypassed

1 Slot 1 and Slot 2 are bypassed during power up

9 SLOT_BYP

0 OTP loading is not bypassed

1 OTP loading is bypassed

10 LOAD_OTP_BYP

0 VBOS to V1 switch is open in Normal mode

1 VBOS to V1 switch is closed in Normal and LPON mode (possible only when V1 = 5 V in Normal

12 VBOS2V1_SW_ALWAYS_EN

Table 86. M_SYS1_CFG register bit description...continued

22.7 M_REG_CTRL

Table 87. M_REG_CTRL register bit allocation

0 No effect (Regulator remains in its current state)

1 Request to disable V3

0 V3DIS

1 Request to enable V3

1 V3EN

0 Follow the power-down slot configuration

1 Keep V3 ON in LPON if V3 was already ON in Normal mode

2 V3ON_LPON

1 Request to disable V2

3 V2DIS

1 Request to enable V2

4 V2EN

0 Follow the power down slot configuration

1 Keep V2 ON in LPON if V2 was already ON in Normal mode

5 V2ON_LPON

000 HS rising slew rate is 20 ns (for 450 KHz only)

001 HS rising slew rate is 20 ns (for 450 KHz only)

010 HS rising slew rate is 15 ns (for 450 KHz only)

011 HS rising slew rate is 10 ns

101 HS rising slew rate is 5 ns

110 HS rising slew rate is 3 ns

111 HS rising slew rate is 2 ns

00 HS falling slew rate is 20 ns (for 450 KHz only)

01 HS falling slew rate is 15 ns (for 450 KHz only)

10 HS falling slew rate is 10 ns

11 HS falling slew rate is 5 ns

Table 88. M_REG_CTRL register bit description...continued

22.8 M_REG_FLG

0 No event detected

1 V3 OC occurred

0 V3OC_I

1 V2 OC occurred

1 V2OC_I

1 V1 OC occurred

2 V1OC_I

1 V3 OV occurred

3 V3OV_I

1 V2 OV occurred

4 V2OV_I

1 V1 OV occurred

5 V1OV_I

1 V3 UV occurred

6 V3UV_I

1 V2 UV occurred

7 V2UV_I

1 V1 UV occurred

8 V1UV_I

1 V2 OL occurred

9 V2OL_I

1 V3 TSD occurred

10 V3TSD_I

1 V2 TSD occurred

11 V2TSD_I

1 V1 TSD occurred

12 V1TSD_I

13 V1TWARN_I

1 VMON_EXT OV occurred

14 V0OV_I

1 VMON_EXT UV occurred

15 V0UV_I

Table 90. M_REG_FLG register bit description...continued

22.9 M_REG_MSK

Table 91. M_REG_MSK register bit allocation

0 Interrupt is not inhibited

1 Interrupt is inhibited

0 V3OC_M

1 V2OC_M

2 V1OC_M

3 V3OV_M

4 V2OV_M

5 V1OV_M

6 V3UV_M

7 V2UV_M

8 V1UV_M

9 V2OL_M

10 V3TSD_M

11 V2TSD_M

12 V1TSD_M

13 V1TWARN_M

14 V0OV_M

15 V0UV_M

22.10 M_REG1_FLG

Table 93. M_REG1_FLG register bit allocation [1] Write 1 in a flag to clear it.

1 V1 low-side OC occurred

0 V1_OCLS_I

Table 94. M_REG1_FLG register bit description

22.11 M_REG1_MSK

0 V1_OCLS_M

Table 96. M_REG1_MSK register bit description

22.12 M_IO_CTRL

Table 97. M_IO_CTRL register bit allocation

0 No effect (IO remain in its current state)

1 Request to assert LVO6 low

0 LVO6LO

1 Request to release LVO6 high

1 LVO6HI

1 Request to assert LVIO4 low

2 LVIO4LO

1 Request to release LVIO4 high

3 LVIO4HI

1 Request to assert LVIO3 low

4 LVIO3LO

1 Request to release LVIO3 high

5 LVIO3HI

1 Request to assert HVIO2 low

6 HVIO2LO

1 Request to release HVIO2 high

7 HVIO2HI

1 Request to assert HVIO1 low

8 HVIO1LO

1 Request to release HVIO1 high

9 HVIO1HI

Table 98. M_IO_CTRL register bit description...continued

22.13 M_IO_TIMER_FLG

Table 99. M_IO_TIMER_FLG register bit allocation [1] Write 1 in a flag to clear it.

0 No event on WAKE1

1 Event on WAKE1 occurred

0 WK1_I

0 No event on WAKE2

1 Event on WAKE2 occurred

1 WK2_I

0 No event on HVIO1

1 Event on HVIO1 occurred

3 HVIO1_I

0 No event on HVIO2

1 Event on HVIO2 occurred

4 HVIO2_I

0 No event on LVIO3

1 Event on LVIO3 occurred

5 LVIO3_I

0 No event on LVIO4

1 Event on LVIO4 occurred

6 LVIO4_I

0 No event on LVI5

1 Event on LVI5 occurred

7 LVI5_I

0 No event on LDT

1 Event on LDT occurred

8 LDT_I

Table 100. M_IO_TIMER_FLG register bit description...continued

22.14 M_IO_TIMER_MSK

Table 101. M_IO_TIMER_MSK register bit allocation

0 Interrupt is not inhibited in Normal mode

1 Interrupt is always inhibited

0 WK1_M

1 WK2_M

3 HVIO1_M

4 HVIO2_M

5 LVIO3_M

6 LVIO4_M

7 LVI5_M

8 LDT_M

Table 102. M_IO_TIMER_MSK register bit description...continued

22.15 M_VSUP_COM_FLG

Table 103. M_VSUP_COM_FLG register bit allocation [1] Write 1 in a flag to clear it.

0 No VSUP undervoltage event

1 VSUP undervoltage event occurred

0 VSUP_UV_I

0 No VSUP overvoltage event

1 VSUP overvoltage event occurred

1 VSUP_OV_I

0 No VSHS undervoltage event

1 VSHS undervoltage event occurred

2 VSHS_UV_I

0 No VSHS overvoltage event

3 VSHS_OV_I

1 SPI request error reported

5 SPI_REQ_I

1 SPI clock error reported

6 SPI_CLK_I

1 SPI CRC error reported

7 SPI_CRC_I

1 I2C request error reported

8 I2C_REQ_I

1 I2C CRC error reported

9 I2C_CRC_I

1 VBOS UV occurred

11 VBOS_UV

0 The switch is opened

1 The switch is closed

12 VBOS2V1SW_S

22.16 M_VSUP_COM_MSK

Table 105. M_VSUP_COM_MSK register bit allocation

0 VSUP_UV_M

1 VSUP_OV_M

2 VSHS_UV_M

3 VSHS_OV_M

5 SPI_REQ_M

6 SPI_CLK_M

7 SPI_CRC_M

8 I2C_REQ_M

9 I2C_CRC_M

Table 106. M_VSUP_COM_MSK register bit description...continued

22.17 M_IOWU_CFG

Table 107. M_IOWU_CFG register bit allocation

00 Input comparator disabled in LP modes only (no consumption)

01 High-level wake-up is configured

10 Low-level wake-up is configured

11 Cyclic sense wake-up is configured

0 WAKE1 deglitcher = 15 us

1 WAKE1 deglitcher = 65 us

8 WK1_DGLT

0 WAKE2 deglitcher = 15 us

1 WAKE2 deglitcher = 65 us

9 WK2_DGLT

0 HVIO1 deglitcher = 15 us

1 HVIO1 deglitcher = 65 us

10 HVIO1_DGLT

0 HVIO2 deglitcher = 15 us

1 HVIO2 deglitcher = 65 us

11 HVIO2_DGLT

0 High-level wake-up is configured

1 Low-level wake-up is configured

13 LVIO3_WUCFG

14 LVIO4_WUCFG

15 LVI5_WUCFG

Table 108. M_IOWU_CFG register bit description...continued

22.18 M_IOWU_EN

00 No wake-up and no interrupt

01 Wake-up only

10 Interrupt only

11 Wake-up and interrupt

22.19 M_IOWU_FLG

Table 111. M_IOWU_FLG register bit allocation [1] Write 1 in a flag to clear it.

1 Wake up by WAKE1 occurred (level) or WAKE1 pin state changed between two trigger event (cyclic sense)

0 WK1_WU_I

1 Wake up by WAKE2 occurred (level) or WAKE2 pin state changed between two trigger event (cyclic sense)

1 WK2_WU_I

0 State at trigger point captured at 0

1 State at trigger point captured at 1

2 WK1_CYC_S

3 WK2_CYC_S

0 Cyclic sense not ready

1 Cyclic sense ready

4 WK1_CYS_RDY

5 WK2_CYS_RDY

1 Wake up by HVIO1 occurred (level) or HVIO1 pin state changed between two trigger event (cyclic sense)

6 HVIO1_WU_I

1 Wake up by HVIO2 occurred (level) or HVIO2 pin state changed between two trigger event (cyclic sense)

7 HVIO2_WU_I

8 HVIO1_CYC_S

9 HVIO2_CYC_S

10 HVIO1_CYS_RDY

11 HVIO2_CYS_RDY

13 LVIO3_WU_I

14 LVIO4_WU_I

15 LVI5_WU_I

Table 112. M_IOWU_FLG register bit description...continued

22.20 M_WU1_EN

Table 114. M_WU1_EN register bit description

22.21 M_WU1_FLG

Table 115. M_WU1_FLG register bit allocation [1] Write 1 in a flag to clear it.

0 No wake-up by CAN

1 Wake-up by CAN occurred

0 CAN_WU_I

0 No wake-up by LIN

1 Wake-up by LIN occurred

1 LIN_WU_I

0 No wake-up by LDT

1 Wake-up by LDT occurred

2 LDT_WU_I

0 No wake-up by MCU GO2NORMAL request

1 Wake-up by MCU GO2NORMAL request occurred

4 GO2NORMAL_WU

0 No wake-up by interrupt time out

1 Wake-up by interrupt time out occurred

5 INT_TO_WU

0 No wake-up by V1 LPON undervoltage

1 Wake-up by V1 LPON undervoltage occurred

6 V1_UVLP_WU

0 No wake-up by max error failure

1 Wake-up by watchdog max error failure occurred

7 WD_OFL_WU

0 No wake-up by to RSTB assertion

1 Wake-up by to RSTB assertion occurred

8 EXT_RSTB_WU

0 No fail-safe event

1 Fail-safe event occurred (FSM went to Fail-safe state)

9 FS_EVT

Table 116. M_WU1_FLG register bit description...continued

22.22 M_TIMER1_CFG

101 TIMER1 period = 512 ms

110 TIMER1 period = 1024 ms

111 TIMER1 period = 2048 ms

0000 TIMER1 ON time = 0 ms

1111 TIMER1 ON time = Infinite

00 TIMER1 delay = 0 us

01 TIMER1 delay = 5 us

10 TIMER1 delay = 10 us

11 TIMER1 delay = 15 us

22.23 M_TIMER2_CFG

Table 119. M_TIMER2_CFG register bit allocation

101 TIMER2 period = 512 ms

110 TIMER2 period = 1024 ms

111 TIMER2 period = 2048 ms

0000 TIMER2 ON time = 0 ms

1111 TIMER2 ON time = Infinite

00 TIMER2 delay = 0 us

01 TIMER2 delay = 5 us

10 TIMER2 delay = 10 us

11 TIMER2 delay = 15 us

Table 120. M_TIMER2_CFG register bit description...continued

22.24 M_TIMER3_CFG

Table 121. M_TIMER3_CFG register bit allocation

101 TIMER3 period = 512 ms

110 TIMER3 period = 1024 ms

111 TIMER3 period = 2048 ms

0000 TIMER3 ON time = 0 ms

1111 TIMER3 ON time = Infinite

00 TIMER3 delay = 0 us

01 TIMER3 delay = 5 us

10 TIMER3 delay = 10 us

11 TIMER3 delay = 15 us

22.25 M_PWM1_CFG

Table 123. M_PWM1_CFG register bit allocation

0 PWM1 frequency = 200 Hz

1 PWM1 frequency = 400 Hz

10 PWM1_F

00 PWM1 delay = 0 us

01 PWM1 delay = 5 us

10 PWM1 delay = 10 us

11 PWM1 delay = 15 us

Table 124. M_PWM1_CFG register bit description

22.26 M_PWM2_CFG

Table 125. M_PWM2_CFG register bit allocation Table 126. M_PWM2_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 PWM2 frequency = 200 Hz

1 PWM2 frequency = 400 Hz

10 PWM2_F

00 PWM2 delay = 0 us

01 PWM2 delay = 5 us

10 PWM2 delay = 10 us

11 PWM2 delay = 15 us

Table 126. M_PWM2_CFG register bit description...continued

22.27 M_PWM3_CFG

Table 127. M_PWM3_CFG register bit allocation

0 PWM3 frequency = 200 Hz

1 PWM3 frequency = 400 Hz

10 PWM3_F

00 PWM3 delay = 0 us

01 PWM3 delay = 5 us

10 PWM3 delay = 10 us

11 PWM3 delay = 15 us

22.28 M_TIMER_PWM_CTRL

Table 129. M_TIMER_PWM_CTRL register bit allocation

0 PWM3 is disabled

1 PWM3 is enabled

0 PWM3_EN

0 PWM2 is disabled

1 PWM2 is enabled

1 PWM2_EN

0 PWM1 is disabled

1 PWM1 is enabled

2 PWM1_EN

0 TIMER3 is disabled

1 TIMER3 is enabled

4 TIM3_EN

0 TIMER2 is disabled

1 TIMER2 is enabled

5 TIM2_EN

0 TIMER1 is disabled

1 TIMER1 is enabled

6 TIM1_EN

22.29 M_CS_CFG

Table 131. M_CS_CFG register bit allocation

00 HS1 is connected to WAKE1

01 HS2 is connected to WAKE1

10 HS3 is connected to WAKE1

11 HS4 is connected to WAKE1

00 HS1 is connected to WAKE2

01 HS2 is connected to WAKE2

10 HS3 is connected to WAKE2

11 HS4 is connected to WAKE2

00 HS1 is connected to HVIO1

01 HS2 is connected to HVIO1

10 HS3 is connected to HVIO1

11 HS4 is connected to HVIO1

00 HS1 is connected to HVIO2

01 HS2 is connected to HVIO2

10 HS3 is connected to HVIO2

11 HS4 is connected to HVIO2

0 Disable the cyclic sense engine when the fault is present

1 Force the wake-up of the device when the fault is detected

9 HS_FLT_WU_FORCE

22.30 M_CS_FLG_MSK

Table 133. M_CS_FLG_MSK register bit allocation [1] Write 1 in a flag to clear it.

1 WAKE1 OL occurred

0 WAKE1_OL_I

1 WAKE2 OL occurred

1 WAKE2_OL_I

1 HVIO1 OL occurred

2 HVIO1_OL_I

1 HVIO2 OL occurred

3 HVIO2_OL_I

5 WAKE1_OL_M

6 WAKE2_OL_M

7 HVIO1_OL_M

0 Interrupt is not inhibited8 HVIO2_OL_M

Table 134. M_CS_FLG_MSK register bit description...continued

22.31 M_HSx_SRC_CFG

Table 135. M_HSx_SRC_CFG register bit allocation

0000 High side is driven by HS1_EN and HS1_DIS register bits

0001 HVIO1 is selected as direct drive pin

0010 HVIO2 is selected as direct drive pin

0011 WAKE1 is selected as direct drive pin

0100 WAKE2 is selected as direct drive pin

0101 LVIO3 is selected as direct drive pin

0110 LVIO4 is selected as direct drive pin

0111 LVI5 is selected as direct drive pin

1000 High side is driven by TIMER1

1001 High side is driven by TIMER2

1010 High side is driven by TIMER3

1011 High side is driven by PWM1

1100 High side is driven by PWM2

1101 High side is driven by PWM3

1110 Not used

1111 Not used

0000 High side is driven by HS2_EN and HS2_DIS register bits

0000 High side is driven by HS3_EN and HS3_DIS register bits

0000 High side is driven by HS4_EN and HS4_DIS register bits

22.32 M_HSx_CTRL

Table 137. M_HSx_CTRL register bit allocation

0 HS1 is disabled

1 HS1 is enabled

0 HS1_EN

0 HS2 is disabled

1 HS2 is enabled

2 HS2_EN

0 HS3 is disabled

1 HS3 is enabled

4 HS3_EN

0 HS4 is disabled

1 HS4 is enabled

6 HS4_EN

0 HSx remains enable in case of VSHS overvoltage

1 HSx are disabled in case of VSHS overvoltage

12 HS_VSHSOV_DIS

0 HSx remains enable in case of VSHS undervoltage

1 HSx are disabled in case of VSHS undervoltage

13 HS_VSHSUV_DIS

0 No recovery

1 Automatic recovery when VSHS UV or OV is removed

14 HS_VSHSUVOV_REC

Table 138. M_HSx_CTRL register bit description...continued

22.33 M_HSx_FLG

Table 139. M_HSx_FLG register bit allocation [1] Write 1 in a flag to clear it.

1 HS1 or HS2 TSD occurred

0 HS12_TSD_I

1 HS1 OC occurred

1 HS1_OC_I

1 HS1 OL occurred

2 HS1_OL_I

1 HS2 OC occurred

4 HS2_OC_I

1 HS2 OL occurred

5 HS2_OL_I

1 HS3 or HS4 TSD occurred

7 HS34_TSD_I

1 HS3 OC occurred

8 HS3_OC_I

1 HS3 OL occurred

9 HS3_OL_I

1 HS4 OC occurred

11 HS4_OC_I

1 HS4 OL occurred

12 HS4_OL_I

Table 140. M_HSx_FLG register bit description...continued

22.34 M_HSx_MSK

0 HS12_TSD_M

1 HS1_OC_M

2 HS1_OL_M

4 HS2_OC_M

5 HS2_OL_M

7 HS34_TSD_M

8 HS3_OC_M

9 HS3_OL_M

11 HS4_OC_M

12 HS4_OL_M

22.35 M_AMUX_CTRL

Table 143. M_AMUX_CTRL register bit allocation

00000 AGND is selected

00001 V1p6 internal voltage (VDIG) is selected

00010 V1 voltage is selected

00011 V2 voltage is selected

00100 V3 voltage is selected

00101 VBOS internal voltage is selected

00110 VSUP voltage is selected (divider ratio configurable by SPI/I²C)

00111 VSHS voltage is selected (divider ratio configurable by SPI/I²C)

01000 WAKE1 voltage is selected (divider ratio configurable by SPI/I²C)

01001 WAKE2 voltage is selected (divider ratio configurable by SPI/I²C)

01010 HVIO1 voltage is selected (divider ratio configurable by SPI/I²C)

01011 HVIO2 voltage is selected (divider ratio configurable by SPI/I²C)

01100 Die temperature sensor is selected : T(°C) = (VAMUX – VTEMP25) / VTEMP_COEFF + 25

01101 V1 temperature sensor is selected

01110 V2 temperature sensor is selected

01111 V3 temperature sensor is selected

10000 VDDIO not divided is selected

1 High-divider ratio is selected (div by 20)

8 AMUX_DIV

0 AMUX is disabled (HIZ, int pull down)

1 AMUX is enabled in Normal mode only

9 AMUX_EN

22.36 M_LDT_CFG1

Table 145. M_LDT_CFG1 register bit allocation Table 146. M_LDT_CFG1 register bit description

22.37 M_LDT_CFG2

Table 147. M_LDT_CFG2 register bit allocation Table 148. M_LDT_CFG2 register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

22.38 M_LDT_CFG3

Table 149. M_LDT_CFG3 register bit allocation Table 150. M_LDT_CFG3 register bit description

22.39 M_LDT_CTRL

Table 151. M_LDT_CTRL register bit allocation

0 LDT is idle

1 LDT is busy

0 LDT_RUN

1 LDT starts counting

1 LDT_EN

0 LDT is set to long count (1 s)

1 LDT is set to short count (128 us)

2 LDT_MODE

0 Target value of wake-up LDT can be read or write

1 Real-time value of 24-bit timer is reported (once LDT stopped)

3 LDT_SEL

000 Function1 is selected

001 Function2 is selected

010 Function3 is selected

011 Function4 is selected

100 Function5 is selected

101 Not used

110 Not used

111 Not used

0 Go to LPOFF

1 Go to LPON

7 LDT2LP

Table 152. M_LDT_CTRL register bit description...continued

22.40 M_CAN

Table 153. M_CAN register bit allocation [1] Write 1 in a flag to clear it.

1 CAN thermal shutdown occurred

0 CAN_TSD_I

1 Dominant timeout occurred

1 CAN_TXD_TO_I

0 CAN transceiver is offline

1 CAN transceiver keeps the current state

5 CAN_FS_DIS

0 CAN is neither in Listen-only mode nor in Normal mode

1 CAN is either in Listen-only mode or in Normal mode

7 CAN_ACTIVE_MODE_S

00 Transceiver offline (TX and RX disabled)

01 Transceiver receive only mode (TX disabled and RX enabled)

10 Transceiver active mode (TX and RX enabled) reacting on V3UV

11 Transceiver active mode (TX and RX enabled) reacting on V3UV

Table 154. M_CAN register bit description...continued

22.41 M_LIN

Table 155. M_LIN register bit allocation [1] Write 1 in a flag to clear it.

1 LIN thermal shutdown occurred

0 LIN_TSD_I

1 LIN_TXD_TO_I

1 Short-circuit timeout occurred

2 LIN_SC_I

0 TXD dominant timeout detection is disabled

1 TXD dominant timeout detection is enabled

7 LIN_TXD_TO

0 LIN short circuit protection is enabled

1 LIN short circuit protection is disabled

8 LIN_SC

0 The LIN transceiver is OFF in case of VSHS undervoltage

1 The LIN transceiver remains in Active mode in case of VSHS undervoltage

9 LIN_VSHSUV_DIS

0 LIN transceiver is offline

1 LIN transceiver keeps the current state

10 LIN_FS_DIS

00 LIN normal slope is enabled

01 Not used

10 LIN slow slope is enabled

11 Not used

00 Transceiver offline

01 Transceiver receive only mode

10 Transceiver active mode

11 Transceiver active mode

Table 156. M_LIN register bit description...continued

22.42 M_CAN_LIN_MSK

0 CAN_TSD_M

1 CAN_TXD_TO_M

000 OFF

001 OFFLINE

010 Invalid state

011 OFFLINEVCCNOK

100 GOACTIVE

101 LISTEN

110 Invalid state

111 NORMAL

6 LIN_TSD_M

7 LIN_TXD_TO_M

8 LIN_SC_M

00011 TRX_ON

00110 TRX_RXONLY

00111 TRX_PROTECT

01100 TRX_DISABLE

01111 TRX_POWERON

10011 TRX_MONITOR

10111 TX_POWERON

22.43 M_MEMORY0

Table 159. M_MEMORY0 register bit allocation Table 160. M_MEMORY0 register bit description

22.44 M_MEMORY1

Table 161. M_MEMORY1 register bit allocation Table 162. M_MEMORY1 register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

22.45 FS_I_OVUV_CFG1

Table 163. FS_I_OVUV_CFG1 register bit allocation

1 LIMP0 assertion

0 V2MON_UV_LIMP0_IMPACT

1 FS0B assertion

1 V2MON_UV_FS0B_IMPACT

1 RSTB assertion

2 V2MON_UV_RSTB_IMPACT

3 V2MON_OV_LIMP0_IMPACT

4 V2MON_OV_FS0B_IMPACT

5 V2MON_OV_RSTB_IMPACT

7 V1MON_UV_LIMP0_IMPACT

8 V1MON_UV_FS0B_IMPACT

9 V1MON_UV_RSTB_IMPACT

10 V1MON_OV_LIMP0_IMPACT

11 V1MON_OV_FS0B_IMPACT

12 V1MON_OV_RSTB_IMPACT

Table 164. FS_I_OVUV_CFG1 register bit description...continued

22.46 FS_I_OVUV_CFG2

0 V0MON_OV_

Table 165. FS_I_OVUV_CFG2 register bit allocation

0 V0MON_UV_LIMP0_IMPACT

1 V0MON_UV_FS0B_IMPACT

2 V0MON_UV_RSTB_IMPACT

3 V0MON_OV_LIMP0_IMPACT

4 V0MON_OV_FS0B_IMPACT

5 V0MON_OV_RSTB_IMPACT

7 V3MON_UV_LIMP0_IMPACT

8 V3MON_UV_FS0B_IMPACT

9 V3MON_UV_RSTB_IMPACT

10 V3MON_OV_LIMP0_IMPACT

11 V3MON_OV_FS0B_IMPACT

12 V3MON_OV_RSTB_IMPACT

22.47 FS_I_FCCU_CFG

Table 167. FS_I_FCCU_CFG register bit allocation

0 FCCU1_LIMP0_IMPACT

1 FCCU1_FS0B_IMPACT

2 FCCU1_RSTB_IMPACT

3 FCCU2_LIMP0_IMPACT

4 FCCU2_FS0B_IMPACT

5 FCCU2_RSTB_IMPACT

0 Low level is a fault

1 High level is a fault

6 FCCU1_FLT_POL

7 FCCU2_FLT_POL

0 FCCU1 = 0 or FCCU2 = 1 level is a fault

8 FCCU12_FLT_POL

000 FCCU2 is disabled

001 FCCU2 is assigned to HVIO1

010 FCCU2 is assigned to HVIO2

011 FCCU2 is assigned to LVIO3

100 FCCU2 is assigned to LVIO4

101 FCCU2 is assigned to LVI5

001 FCCU1 and FCCU2 inputs monitoring activated by pair (bi-stable protocol)

010 FCCU1 or FCCU2 single input monitoring activated

011 FCCU1 input monitoring only, FCCU2 input not used

100 FCCU2 input monitoring only, FCCU1 input not used

Table 168. FS_I_FCCU_CFG register bit description...continued

22.48 FS_I_FSSM_CFG

4 FLT_MID_LIMP0_IMPACT

5 FLT_MID_FS0B_IMPACT

6 FLT_MID_RSTB_IMPACT

00 Max value = 2

01 Max value = 6

10 Max value = 8

11 Max value = 12

9 FS0B_SC_RSTB_IMPACT

10 EXTRSTB_FS0B_IMPACT

11 LIMP0_SC_RSTB_IMPACT

12 RSTB_DUR

0 RSTB low 8 s timer is enabled

1 RSTB low 8 s time is disabled

13 RSTB8S_DIS

0 External RSTB monitoring is enabled

1 External RSTB monitoring is disabled

14 EXT_RSTB_DIS

Table 170. FS_I_FSSM_CFG register bit description...continued

22.49 FS_I_WD_CFG

Table 171. FS_I_WD_CFG register bit allocation Table 172. FS_I_WD_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 WD stays enabled in LPON

1 WD is disabled in LPON

11 WD_DIS_LPON

12 WD_LIMP0_IMPACT

13 WD_FS0B_IMPACT

14 WD_RSTB_IMPACT

22.50 FS_WDW_CFG

Table 173. FS_WDW_CFG register bit allocation

0000 INFINITE Time Out, Window fully opened[1]

0 Watchdog window is disabled (watchdog time out)

1 Watchdog window is enabled (watchdog window 50 %)

10 WDW_EN

0 Watchdog recovery is disabled

1 Watchdog recovery is enabled

11 WDW_REC_EN

Table 174. FS_WDW_CFG register bit description...continued [1] The value 4b’0000 can be written in INIT phase only.

22.51 FS_WD_TOKEN

Table 175. FS_WD_TOKEN register bit allocation Table 176. FS_WD_TOKEN register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 176. FS_WD_TOKEN register bit description...continued

22.52 FS_WD_ANSWER

Table 177. FS_WD_ANSWER register bit allocation Table 178. FS_WD_ANSWER register bit description

22.53 FS_LIMP12_CFG

Table 179. FS_LIMP12_CFG register bit allocation

1 LIMP1 assertion

0 LIMP1_REQ

01 Default high (Active low)

11 Default low (Active high)

1 LIMP2 assertion

4 LIMP2_REQ

00 PWM frequency = 100 Hz (Default high)

10 PWM frequency = 100 Hz (Default low)

00 PWM duty cycle = 20 %

01 PWM duty cycle = 10 %

10 PWM duty cycle = 5 %

Table 180. FS_LIMP12_CFG register bit description...continued

22.54 FS_FS0B_LIMP0_REL

Table 181. FS_FS0B_LIMP0_REL register bit allocation Table 182. FS_FS0B_LIMP0_REL register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

22.55 FS_ABIST

Table 183. FS_ABIST register bit allocation

0 No ABIST

1 ABIST on V3MON requested

0 ABIST_V3MON

1 ABIST on V2MON requested

1 ABIST_V2MON

1 ABIST on V1MON requested

2 ABIST_V1MON

1 ABIST on V1UVLP requested

3 ABIST_V1UVLP

1 ABIST on VMON_EXT requested

4 ABIST_V0MON

0 ABIST not executed on V3MON or fail on V3MON

1 V3MON ABIST PASS

6 ABIST_V3MON_DIAG

0 ABIST not executed on V2MON or fail on V2MON

1 V2MON ABIST PASS

7 ABIST_V2MON_DIAG

0 ABIST not executed on V1MON or fail on V1MON

1 V1MON ABIST PASS

8 ABIST_V1MON_DIAG

0 ABIST not executed on V1UVLP or fail on V1UVLP

1 V1UVLP ABIST PASS

9 ABIST_V1UVLP_DIAG

0 ABIST not executed on V0MON or fail on V0MON

1 V0MON ABIST PASS

10 ABIST_V0MON_DIAG

0 No ABIST on going

1 ABIST on going

11 ABIST_ONGOING

0 ABIST not executed

1 ABIST executed

12 ABIST_DONE

1 Clear ABIST flags (ABIST_DONE, ABIST_VxMON_DIAG, ABIST_V1UVLP_DIAG)

13 CLEAR_ABIST

1 Launch ABIST

14 LAUNCH_ABIST

0 ABIST not ready for launch

1 ABIST ready for launch

15 ABIST_READY

Table 184. FS_ABIST register bit description...continued

22.56 FS_SAFETY_OUTPUTS

0 LIMP0_REQ

0 No failure

1 Short to high detected

1 LIMP0_DIAG

0 LIMP0 pad is sensed low

1 LIMP0 pad is sensed High

2 LIMP0_SNS

0 LIMP0 driver command sensed Low

1 LIMP0 driver command sensed High

3 LIMP0_DRV

5 FS0B_REQ

1 FS0B short to High detected

6 FS0B_DIAG

0 FS0B pad sensed low

1 FS0B pad sensed High

7 FS0B_SNS

0 FS0B driver command sensed Low

1 FS0B driver command sensed High

8 FS0B_DRV

1 RSTB assertion (pulse)

9 RSTB_REQ

10 RSTB_DIAG

0 RSTB pad is sensed low

1 RSTB pad is sensed High

11 RSTB_SNS

0 RSTB driver command sensed low

1 RSTB driver command sensed high

12 RSTB_DRV

0 No RSTB event

1 RSTB event occurred

13 RSTB_EVT

0 No RSTB pin assertion

1 RSTB pin assertion occurred

14 RSTB_EXT

Table 186. FS_SAFETY_OUTPUTS register bit description...continued

22.57 FS_SAFETY_FLG

Table 187. FS_SAFETY_FLG register bit allocation [1] Write 1 in a flag to clear it.

0 FCCU2 is low

1 FCCU2 is high

0 FCCU2_S

0 FCCU1 is low

1 FCCU1 is high

1 FCCU1_S

1 FCCU2 error reported

2 FCCU2_I

0 No error3 FCCU1_I

1 FCCU1 error reported

1 FCCU12 error reported

4 FCCU12_I

5 FCCU2_M

6 FCCU1_M

7 FCCU12_M

0 WD refresh OK

1 WD refresh not OK

9 WD_NOK_I

10 WD_NOK_M

0 No error detected

1 INIT registers CRC error detected

11 INIT_CRC_NOK_I

12 INIT_CRC_NOK_M

1 Real-time error detected

13 FCCU2_ERR_S

14 FCCU1_ERR_S

15 FCCU12_ERR_S

22.58 FS_CRC

Table 189. FS_CRC register bit allocation

9 INIT_CRC_LIMP0_IMPACT

10 INIT_CRC_FS0B_IMPACT

1 Computation of the INIT CRC starts

14 INIT_CRC_REQ

23 OTP register mapping

24 OTP register description

24.1 OTP_DEVICE_VER

Table 193. OTP_DEVICE_VER register bit allocation

0 V1_PNP_EN_OTP

1 V2_EN_OTP

2 HSD24_EN_OTP

3 HSD13_EN_OTP

4 LDTIM_EN_OTP

0 LIN is disabled

1 LIN is enabled

5 LIN_EN_OTP

0 CAN is disabled by OTP

1 CAN is enabled by OTP

6 CAN_EN_OTP

0 Key OFF – Key ON feature is disabled by OTP

1 Key OFF – Key ON feature is enabled by OTP

7 KEY_OFF_ON_EN_OTP

24.2 OTP_DEVICE_VER1

Table 195. OTP_DEVICE_VER1 register bit allocation

0 VMON_EXT pin is disabled

1 VMON_EXT pin is enabled

2 V0MON_EN_OTP

3 LIMP0_EN_OTP

4 FS0B_EN_OTP

0 FCCU monitoring is disabled

1 FCCU monitoring is enabled

5 FCCU_EN_OTP

0 ABIST is disabled

1 ABIST is enabled

6 ABIST_EN_OTP

7 RSTB_DUR_OTP

24.3 OTP_PROG_ID

Table 197. OTP_PROG_ID register bit allocation Table 198. OTP_PROG_ID register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

24.4 OTP_V1_CFG1

Table 199. OTP_V1_CFG1 register bit allocation

00 Soft start is 269 µs

01 Soft start is 538 µs

10 Soft start is 1077 µs

11 Soft start is 2150 µs

24.5 OTP_V1_CFG2

Table 201. OTP_V1_CFG2 register bit allocation

0 Switching frequency is 450 kHz

5 BUCK_CLK_OTP

24.6 OTP_V1_CFG3

Table 203. OTP_V1_CFG3 register bit allocation

101001 SC = 361 mV/µs (recommended when Fsw = 450 kHz, LV1_buck = 22 µH and Vbuck = 5 V)

0 Low side overcurrent protection is disabled

1 Low side overcurrent protection is enabled

6 V1_OCLS_EN_OTP

Table 204. OTP_V1_CFG3 register bit description [1] The slope compensation values are normalized for a typical V1_IN at 12 V.

24.7 OTP_V1_CFG4

Table 205. OTP_V1_CFG4 register bit allocation

00 TON time in PFM is 1021 ns (V1 = 5 V, freq = 450 kHz, V1_IN = 12 V)

00 TOFF time in PFM is 605 ns (freq = 450 kHz)

01 TOFF time in PFM is 1170 ns (freq = 450 kHz)

10 TOFF time in PFM is 1725 ns (freq = 450 kHz)

11 TOFF time in PFM is 2285 ns (freq = 450 kHz)

000 Not used

001 Not used

010 Not used

011 Not used

100 Not used

101 Overcurrent (peak) threshold is 700 mA

110 Overcurrent (peak) threshold is 800 mA

111 Overcurrent (peak) threshold is 900 mA

Table 206. OTP_V1_CFG4 register bit description...continued [1] Values given for indication only. Refer to application note for detailed description of these parameters. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

24.8 OTP_V1_CFG5

Table 207. OTP_V1_CFG5 register bit allocation

000 Average overcurrent threshold is 200 mA

001 Average overcurrent threshold is 300 mA

010 Average overcurrent threshold is 400 mA

011 Average overcurrent threshold is 500 mA

100 Average overcurrent threshold is 600 mA

101 Average overcurrent threshold is 700 mA

110 Average overcurrent threshold is 800 mA

010 Overcurrent (peak) threshold is 425 mA

011 Overcurrent (peak) threshold is 525 mA

100 Overcurrent (peak) threshold is 625 mA

101 Overcurrent (peak) threshold is 725 mA

110 Overcurrent (peak) threshold is 825 mA

111 Overcurrent (peak) threshold is 925 mA

Table 208. OTP_V1_CFG5 register bit description

24.9 OTP_V1_CFG7

Table 210. OTP_V1_CFG7 register bit description

24.10 OTP_V1_CFG8

Table 211. OTP_V1_CFG8 register bit allocation Table 212. OTP_V1_CFG8 register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

24.11 OTP_V1_CFG9

Table 213. OTP_V1_CFG9 register bit allocation

0 VBOS to V1 switch is open in LPON mode

1 VBOS to V1 switch is closed in LPON mode

0 VBOS2V1_SW_LP_EN_OTP

0 V1 PNP OC time out = 10 ms

1 V1 PNP OC time out = 1 ms

1 CONF_OC_TO_V1_OTP

2 VV1_LDO_OTP

0 V1 LDO OC = 150 mA

1 V1 LDO OC = 75 mA

3 CONF_OC_V1_OTP

0 V1 regulator is disabled in case of TSD

1 V1 regulator is disabled and the device transitions to Fail-Safe state in case of TSD

4 CONF_TSD_V1_OTP

0 V1 regulator is disabled in case of OV

1 V1 regulator is disabled and the device transitions to Fail-Safe state in case of OV

5 CONF_OV_V1_OTP

6 V1MON_OTP

1 VBOS to V1 switch is closed in Normal and LPON mode (possible only when V1 = 5 V in Normal mode)

7 VBOS2V1_SW_

24.12 OTP_V2_CFG

Table 215. OTP_V2_CFG register bit allocation

00 V2 starts and stops in slot 0

01 V2 starts and stops in slot 1

10 V2 starts and stops in slot 2

11 V2 does not start in a slot (enabled by SPI / I²C)

2 VV2_OTP

0 V2 LDO OC = 150 mA

1 V2 LDO OC = 75 mA

3 CONF_OC_V2_OTP

0 V2 regulator is disabled in case of TSD

1 V2 regulator is disabled and the device transitions to Fail-safe state in case of TSD

4 CONF_TSD_V2_OTP

0 V2 regulator is disabled in case of OV

1 V2 regulator is disabled and the device transitions to Fail-safe state in case of OV

5 CONF_OV_V2_OTP

6 V2MON_OTP

24.13 OTP_V3_CFG

Table 217. OTP_V3_CFG register bit allocation

00 V3 starts and stops in slot 0

01 V3 starts and stops in slot 1

10 V3 starts and stops in slot 2

11 V3 does not start in a slot (enabled by SPI/I²C)

2 VV3_OTP

0 V3 LDO OC = 150 mA

1 V3 LDO OC = 75 mA

3 CONF_OC_V3_OTP

0 V3 regulator is disabled in case of TSD

1 V3 regulator is disabled and the device transitions to Fail-safe state in case of TSD

4 CONF_TSD_V3_OTP

0 V3 regulator is disabled in case of OV

1 V3 regulator is disabled and the device transitions to Fail-safe state in case of OV

5 CONF_OV_V3_OTP

6 V3MON_OTP

24.14 OTP_HVIO_CFG1

Table 219. OTP_HVIO_CFG1 register bit allocation

00 HVIO2 polarity is changed in slot 0

01 HVIO2 polarity is changed in slot 1

10 HVIO2 polarity is changed in slot 2

11 HVIO2 is not released in a slot (enabled by SPI / I²C)

00 HVIO1 polarity is changed in slot 0

01 HVIO1 polarity is changed in slot 1

10 HVIO1 polarity is changed in slot 2

11 HVIO1 is not released in a slot (enabled by SPI/I2C)

00 WAKE2 internal pull down and pull up are configured as cell repeater

01 WAKE2 internal pull down is enabled and pull up is disabled

10 WAKE2 internal pull down is disabled and pull up is enabled

11 WAKE2 internal pull down and pull up are disabled

00 WAKE1 internal pull down and pull up are configured as cell repeater

01 WAKE1 internal pull down is enabled and pull up is disabled

10 WAKE1 internal pull down is disabled and pull up is enabled

11 WAKE1 internal pull down and pull up are disabled

24.15 OTP_HVIO_CFG2

Table 221. OTP_HVIO_CFG2 register bit allocation

00 HVIO2 internal pull down and pull up are configured as cell repeater

01 HVIO2 internal pull down is enabled and pull up is disabled

10 HVIO2 internal pull down is disabled and pull up is enabled

11 HVIO2 internal pull down and pull up are disabled

0 HVIO2 default state is low (asserted)

1 HVIO2 default state is high (HIZ)

2 HVIO2_OUT_DFLT_OTP

0 HVIO2 is configured as an input

1 HVIO2 is configured as an output

3 HVIO2_OUT_EN_OTP

00 HVIO1 internal pull down and pull up are configured as cell repeater

01 HVIO1 internal pull down is enabled and pull up is disabled

10 HVIO1 internal pull down is disabled and pull up is enabled

11 HVIO1 internal pull down and pull up are disabled

0 HVIO1 default state is low (asserted)

1 HVIO1 default state is high (HIZ)

6 HVIO1_OUT_DFLT_OTP

0 HVIO1 is configured as an input

1 HVIO1 is configured as an output

7 HVIO1_OUT_EN_OTP

24.16 OTP_LVIO_CFG1

Table 223. OTP_LVIO_CFG1 register bit allocation

00 LVIO3 polarity is changed in slot 0

01 LVIO3 polarity is changed in slot 1

10 LVIO3 polarity is changed in slot 2

11 LVIO3 is not released in a slot (enabled by SPI/I²C)

0 LVIO3 HS is disabled

1 LVIO3 HS is enabled

2 LVIO3_HS_EN_OTP

0 LVIO3 LS is disabled

1 LVIO3 LS is enabled

3 LVIO3_LS_EN_OTP

00 LVIO3 internal pull down and pull up are configured as cell repeater

01 LVIO3 internal pull down is enabled and pull up is disabled

10 LVIO3 internal pull down is disabled and pull up is enabled

11 LVIO3 internal pull down and pull up are disabled

6 LVIO3_OUT_DFT_OTP

7 LVIO4_OUT_DFT_OTP

24.17 OTP_LVIO_CFG2

Table 225. OTP_LVIO_CFG2 register bit allocation

00 LVIO4 polarity is changed in slot 0

01 LVIO4 polarity is changed in slot 1

10 LVIO4 polarity is changed in slot 2

11 LVIO4 is not released in a slot (enabled by SPI/I²C)

0 LVIO4 HS is disabled

1 LVIO4 HS is enabled

2 LVIO4_HS_EN_OTP

0 LVIO4 LS is disabled

1 LVIO4 LS is enabled

3 LVIO4_LS_EN_OTP

00 LVIO4 internal pull down and pull up are configured as cell repeater

01 LVIO4 internal pull down is enabled and pull up is disabled

10 LVIO4 internal pull down is disabled and pull up is enabled

11 LVIO4 internal pull down and pull up are disabled

00 LVI5 internal pull down and pull up are configured as cell repeater

11 LVI5 internal pull down and pull up are disabled

24.18 OTP_IO_OUT_SEL_CFG

Table 227. OTP_IO_OUT_SEL_CFG register bit allocation

0 HVO1 is connected to alternate function (SLOT by OTP or control by SPI/I²C)

1 HVO1 is connected to LIMP1 function

0 HVO1_SEL_OTP

0 HVO2 is connected to alternate function (SLOT by OTP or control by SPI/I²C)

1 HVO2 is connected to LIMP2 function

1 HVO2_SEL_OTP

0 LVO3 is connected to alternate function (SLOT by OTP or control by SPI/I²C)

1 LVO3 is connected to LIMP1 function

2 LVO3_SEL_OTP

0 LVO4 is connected to alternate function (SLOT by OTP or control by SPI/I2C)

1 LVO4 is connected to LIMP2 function

3 LVO4_SEL_OTP

0 HS1 is connected to HS1 driver

1 HS1 is connected to LIMP1 function

4 HS1_SEL_OTP

0 HS3 is connected to HS3 driver

1 HS3 is connected to LIMP2 function

5 HS3_SEL_OTP

24.19 OTP_MAIN_SYS_I2C_CFG

Table 229. OTP_MAIN_SYS_I2C_CFG register bit allocation

0000 I2C address is 0x20

0001 I2C address is 0x22

0010 I2C address is 0x24

0011 I2C address is 0x26

0100 I2C address is 0x28

0101 I2C address is 0x2A

0110 I2C address is 0x2C

0111 I2C address is 0x2E

1000 I2C address is 0x30

1001 I2C address is 0x32

1010 I2C address is 0x34

1011 I2C address is 0x36

1100 I2C address is 0x38

1101 I2C address is 0x3A

1110 I2C address is 0x3C

1111 I2C address is 0x3E

0 I2C pins are enabled

1 SPI pins are enabled

4 SPI_EN_OTP

1 Slot 1 and Slot 2 are bypassed when waking up from LPON

5 SLOT_BYP_OTP

0 Modulation is disabled

1 Modulation is enabled

6 MOD_EN_OTP

1 Pseudo-random modulation is selected

7 MOD_CONF_OTP

24.20 OTP_FS_SYS_CFG

Table 231. OTP_FS_SYS_CFG register bit allocation

0 Do not go to FS at first fault

1 Go to FS at first fault

0 FIRST_FAULT_EN_OTP

0 RSTB 8 s timer is enabled

1 RSTB 8 s timer is disabled

1 RSTB8S_DIS_OTP

0 Watchdog period is configurable by SPI/I2C

1 Watchdog period is infinite

2 WD_INF_OTP

0 FS state duration is 100 ms

1 FS state duration is 4 s

3 FS_DUR_CFG_OTP

0 Automatic restart after FS state

1 Go to LPOFF after FS state

4 FS_LPOFF_OTP

0 CRC is enabled

1 CRC is disabled

5 INIT_CRC_DIS_OTP

24.21 OTP_OVUV_CFG1

Table 233. OTP_OVUV_CFG1 register bit allocation

0001 V1MON OV = 103 %

0011 V1MON OV = 104 %

0101 V1MON OV = 105 %

0111 V1MON OV = 106 %

1001 V1MON OV = 107 %

1011 V1MON OV = 108 %

1101 V1MON OV = 109 %

1111 V1MON OV = 110 %

0000 V1MON UV = 64 %

0001 V1MON UV = 63 %

0011 V1MON UV = 96 %

0101 V1MON UV = 95 %

0111 V1MON UV = 94 %

1001 V1MON UV = 93 %

1011 V1MON UV = 92 %

1110 V1MON UV = 62 %

1111 V1MON UV = 61 %

24.22 OTP_OVUV_CFG2

Table 235. OTP_OVUV_CFG2 register bit allocation

0001 V2MON OV = 103 %

0011 V2MON OV = 104 %

0101 V2MON OV = 105 %

0111 V2MON OV = 106 %

1001 V2MON OV = 107 %

1011 V2MON OV = 108 %

1101 V2MON OV = 109 %

1111 V2MON OV = 110 %

0000 V2MON UV = 64 %

0001 V2MON UV = 63 %

0011 V2MON UV = 96 %

0101 V2MON UV = 95 %

0111 V2MON UV = 94 %

1001 V2MON UV = 93 %

1011 V2MON UV = 92 %

1110 V2MON UV = 62 %

1111 V2MON UV = 61 %

24.23 OTP_OVUV_CFG3

Table 237. OTP_OVUV_CFG3 register bit allocation

0001 V3MON OV = 103 %

0011 V3MON OV = 104 %

0101 V3MON OV = 105 %

0111 V3MON OV = 106 %

1001 V3MON OV = 107 %

1011 V3MON OV = 108 %

1101 V3MON OV = 109 %

1111 V3MON OV = 110 %

0000 V3MON UV = 64 %

0001 V3MON UV = 63 %

0011 V3MON UV = 96 %

0101 V3MON UV = 95 %

0111 V3MON UV = 94 %

1001 V3MON UV = 93 %

1011 V3MON UV = 92 %

1110 V3MON UV = 62 %

1111 V3MON UV = 61 %

24.24 OTP_OVUV_CFG4

Table 239. OTP_OVUV_CFG4 register bit allocation

0001 V0MON OV = 103 %

0011 V0MON OV = 104 %

0101 V0MON OV = 105 %

0111 V0MON OV = 106 %

1001 V0MON OV = 107 %

1011 V0MON OV = 108 %

1101 V0MON OV = 109 %

1111 V0MON OV = 110 %

0000 V0MON UV = 64 %

0001 V0MON UV = 63 %

0011 V0MON UV = 96 %

0101 V0MON UV = 95 %

0111 V0MON UV = 94 %

1001 V0MON UV = 93 %

1011 V0MON UV = 92 %

1110 V0MON UV = 62 %

1111 V0MON UV = 61 %

24.25 OTP_UV_DGLT_CFG

Table 241. OTP_UV_DGLT_CFG register bit allocation

00 V3MON UV deglitcher = 5 µs

01 V3MON UV deglitcher = 15 µs

10 V3MON UV deglitcher = 25 µs

11 V3MON UV deglitcher = 40 µs

00 V2MON UV deglitcher = 5 µs

01 V2MON UV deglitcher = 15 µs

10 V2MON UV deglitcher = 25 µs

11 V2MON UV deglitcher = 40 µs

00 V1MON UV deglitcher = 5 µs

01 V1MON UV deglitcher = 15 µs

10 V1MON UV deglitcher = 25 µs

11 V1MON UV deglitcher = 40 µs

00 V0MON UV deglitcher = 5 µs

01 V0MON UV deglitcher = 15 µs

10 V0MON UV deglitcher = 25 µs

11 V0MON UV deglitcher = 40 µs

24.26 OTP_LIMP_OV_DGLT_CFG

Table 243. OTP_LIMP_OV_DGLT_CFG register bit allocation

0 V3MON OV deglitcher = 25 µs

1 V3MON OV deglitcher = 45 µs

0 V3MON_OVDGLT_OTP

0 V2MON OV deglitcher = 25 µs

1 V2MON OV deglitcher = 45 µs

1 V2MON_OVDGLT_OTP

0 V1MON OV deglitcher = 25 µs

1 V1MON OV deglitcher = 45 µs

2 V1MON_OVDGLT_OTP

0 V0MON OV deglitcher = 25 µs

1 V0MON OV deglitcher = 45 µs

3 V0MON_OVDGLT_OTP

24.27 OTP_RSTB_IMPACT_CFG

Table 245. OTP_RSTB_IMPACT_CFG register bit allocation

0 V3 OV does not assert RSTB

1 V3 OV asserts RSTB

0 V3OV_RSTB_IMPACT_OTP

0 V3 UV does not assert RSTB

1 V3 UV asserts RSTB

1 V3UV_RSTB_IMPACT_OTP

0 V2 OV does not assert RSTB

1 V2 OV asserts RSTB

2 V2OV_RSTB_IMPACT_OTP

0 V2 UV does not assert RSTB

1 V2 UV asserts RSTB

3 V2UV_RSTB_IMPACT_OTP

0 V1 OV does not assert RSTB

1 V1 OV asserts RSTB

4 V1OV_RSTB_IMPACT_OTP

0 V1 UV does not assert RSTB

1 V1 UV asserts RSTB

5 V1UV_RSTB_IMPACT_OTP

0 VMON_EXT OV does not assert RSTB

1 VMON_EXT OV asserts RSTB

6 V0OV_RSTB_IMPACT_OTP

0 VMON_EXT UV does not assert RSTB

1 VMON_EXT UV asserts RSTB

7 V0UV_RSTB_IMPACT_OTP

7.95 V for OTP programming

Figure 56. Example of application schematic with 450 kHz HVBUCK version, SPI interface FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

2.25 MHz

Figure 57. Example of application schematic with 2.25 MHz HVBUCK version, SPI interface FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 58. Example of application schematic, HVLDO1 version with internal PMOS only, I2C interface FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 59. Example of application schematic, HVLDO1 version with external PNP, SPI interface FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers FS23 package is a QFN, thermally enhanced, wettable flanks, 7 x 7 x 0.85 mm, 0.5 mm pitch, 48 pins. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

27 Appendix: ISO 11898-2016 parameter cross-reference list

Updated legal information FS23 v.6 14 May 2024 • CIN 202404026I
Global editing for NXP style and standards
Updated Figure 8, Figure 11, Figure 40
Added new condition to each parameter
Section 18.2: Changed "Depending on the OTP configuration via VSHS_UV_DIS_OTP bit, ..." to "Depending on the configuration of the SPI/I2C LIN_VSHSUV_DIS bit, ..."
Table 33: Changed "ILIN_NO_BAT" Max value from "100" to "30"
Table 84: Changed Bit "10" Description from "POR" to "POR, or clear on write (write '1')"
Table 89: Changed Write Bit "7" from "V3UV_I" to "V2UV_I"
Table 115: Deleted "or Fail-safe" from Description for Bit "6" and "9"

Global editing for NXP style and standards
Updated Figure 1, Figure 10, Figure 15, Figure 17
Section 2, Figure 35 – Under "Power management", in the first bullet, changed "400 mA" to "600 mA" – Under "System features", first bullet changed to "One CAN FD supporting up to 5 Mbps communication following ISO 11898-2:2016 and SAE J2284 standards" – Under "EMC compliance", added two bullet items
Table 1: Changed all entries under "LIMPx" from "Yes" to "Opt"
Table 2: Updated part descriptions
Table 7: Updated Max values for "RθJA", "RθJC_BOT", and "RθJC_TOP" Added row "ΨJT", and three footnotes
Section 12.7: Added second paragraph
Section 12.9.1: Updated text
Table 13: Changed "V1" "Max DC current" from "400 mA" to "600 mA"
Section 13.1.1: Updated text of first paragraph under "Current limitation"
Section 13.1.2: Relocated section – Section 13.1.2.1: Incorporated former sections "Spread spectrum", "Triangular spread spectrum", and "Pseudo-random triangular spread spectrum"
Section 13.1.4: Updated HVBUCK electrical parameters
Added Section 13.1.5
Section 18.1: Updated text
Table 32: Updated CAN electrical parameters descriptions
Table 33: Updated LIN electrical parameters descriptions
Section 19.2: Added paragraph before Table 34
Section 19.6.6: Updated text
Section 21: Removed for sections "Readable registers" and "Writable registers", added Section 21.1
Section 22: Updated SPI/I²C register descriptions
Section 23: Updated OTP register descriptions
Table 208: Updated threshold values (mA) in "Description" for "Symbol" "3 to 5"
Updated title of Section 27 to "Appendix: ISO 11898-2016 parameter cross-reference list" FS23 v.4.1 20231211 — FS23 v.4 20230915 — FS23 v.3 2023/03 — FS23 v.2 2023/03 — FS23 v.1.1 2022/05 — FS23 v.1 2022/01 Initial version

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers HTML publications — An HTML version, if available, of this document is provided as a courtesy. Definitive information is contained in the applicable document in PDF format. If there is a discrepancy between the HTML document and the PDF document, the PDF document has priority. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Suitability for use in automotive applications (functional safety) — This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Tables Tab. 38. Watchdog refresh counter limit Tab. 40. Watchdog window in fault recovery Tab. 53. Application related fail-safe fault list and Tab. 69. MISO general device status bits Tab. 104. M_VSUP_COM_FLG register bit Tab. 105. M_VSUP_COM_MSK register bit allocation ..132 Tab. 106. M_VSUP_COM_MSK register bit FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Tab. 129. M_TIMER_PWM_CTRL register bit Tab. 130. M_TIMER_PWM_CTRL register bit Tab. 181. FS_FS0B_LIMP0_REL register bit Tab. 182. FS_FS0B_LIMP0_REL register bit Tab. 185. FS_SAFETY_OUTPUTS register bit Tab. 186. FS_SAFETY_OUTPUTS register bit Tab. 194. OTP_DEVICE_VER register bit description .. 183 Tab. 196. OTP_DEVICE_VER1 register bit FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Tab. 227. OTP_IO_OUT_SEL_CFG register bit Tab. 228. OTP_IO_OUT_SEL_CFG register bit Tab. 229. OTP_MAIN_SYS_I2C_CFG register bit Tab. 230. OTP_MAIN_SYS_I2C_CFG register bit Tab. 232. OTP_FS_SYS_CFG register bit description ..201 Tab. 241. OTP_UV_DGLT_CFG register bit allocation . 206 Tab. 242. OTP_UV_DGLT_CFG register bit Tab. 243. OTP_LIMP_OV_DGLT_CFG register bit Tab. 244. OTP_LIMP_OV_DGLT_CFG register bit Tab. 245. OTP_RSTB_IMPACT_CFG register bit Tab. 246. OTP_RSTB_IMPACT_CFG register bit Tab. 247. ISO 11898-2:2016 to NXP data sheet FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Figures Fig. 5. Part numbers mapping versus base feature Fig. 21. HVBUCK schematic with connection to V1_ Fig. 24. HVLDO1 application schematic, with Fig. 29. Example of HVIO pins configuration in the Fig. 30. Example of LVIO pins configuration in the Fig. 32. Cyclic sense schematic example with HS1 Fig. 35. CAN FD transceiver internal diagram, with Fig. 38. CAN timing definition according to ISO Fig. 49. Fault Error Counter diagram with maximum Fig. 50. Fault Error Counter diagram with maximum Fig. 56. Example of application schematic with 450 Fig. 57. Example of application schematic with 2.25 Fig. 58. Example of application schematic, HVLDO1 version with internal PMOS only, Fig. 59. Example of application schematic, HVLDO1 version with external PNP, SPI FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

27 Appendix: ISO 11898-2016 parameter

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 16 October 2024 Document identifier: FS23

Product Information

MFS2300BMBA0EP specifications and overview.

Summary

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Rev. 7.0 - 16 October 2024

Description

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Rev. 7.0 - 16 October 2024

Source title MFS2300BMBA0EP Datasheet(PDF) - NXP Semiconductors

Related Parts

More parts from the same family.

Browse manufacturer