MF4SAM3

MF4SAM3 NXP | Alldatasheet

Document overview

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Technical content

MIFARE SAM AV3 secure access module Rev. 3.0 — 2 August 2019 Product short data sheet

561930 COMPANY PUBLIC

1 General description

The NXP MIFARE SAM AV3 secure hardware solution is the ideal add-on for reader devices offering additional security services. Supporting DES, TDEA, AES and RSA capabilities, it offers secure storage and secure communication in a variety of infrastructures. Unlike other products in the field, MIFARE SAM AV3 has proven interoperability with all of NXP's broad card and RFID product portfolio, (MIFARE, NTAG DNA, ICODE DNA, UCODE DNA and SmartMX product families), making it the most versatile and secure SAM solution on the market today. The MIFARE SAM AV3 is built on NXP’s SmartMX2 P60 secure smart card controller with CC EAL6+ certification. Its software implementation is evaluated and composite certified by the MIFARE Security Evaluation Scheme. Similar to the hardware CC evaluation, the MIFARE Scheme also evaluates against high attack potential. Hence, systems using MIFARE SAM AV3 are reassured with the state-of-the-art security measures adopted by the industry. Programmable Logic The MIFARE SAM AV3 is equipped with a new Programmable Logic functionality which allows customers to flexibly create their business logic on the SAM. This new functionality opens up many new possibilities with the creation of project-specific customization such as a new key diversification algorithm, a new secure messaging, or a new secure storage. X-mode communication When used in combination with a reader IC supporting innovative "X" features, MIFARE SAM AV3 provides a significant boost in performance to the reader along with faster communication between reader and module. The "X" feature is a new way to use the SAM in a system, with SAM connected to the microcontroller and the reader IC simultaneously. Secured communication The connection between the SAM and the reader is performed using security protocols based on either AES symmetric cryptography or PKI RSA asymmetric cryptography. The protocols comply with the state-of-art standards and thereby ensure data confidentiality and integrity.

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 2 / 31

2 Features and benefits

2.1 Cryptography

• Supports MIFARE Crypto1, DES, TDEA (112 and 168 bits), AES (128, 192 and 256 bits), RSA (up to 2048 bits) and ECC (up to 256 bits) cryptography
• Supported NXP’s products: – MIFARE DESFire, MIFARE DESFire EV1, MIFARE DESFire EV2 – MIFARE Plus, MIFARE Plus EV1 – MIFARE Classic, MIFARE Classic EV1 – MIFARE Ultralight EV1, MIFARE Ultralight C – MIFARE DESFire Light – NTAG DNA – ICODE DNA – UCODE DNA
• Secure storage and updating of keys – 128 key entries for symmetric cryptography – 3 RSA key entries for asymmetric cryptography – 8 ECC public key entries for signature verification – 4 ECC curves entries – 48 EMV CA public key entries (supports 8 RID minimum)
• SHA-1, SHA-224 and SHA-256 hashing computation
• TDEA and AES-based key diversification
• Generic cryptography commands for user-defined schemes
• Supports EMVCo terminal functionality
• True random number generator (TRNG) compliant to AIS-31

2.2 Communication

• ISO/IEC 7816 (part 2 and 3) contact interface – Support Class A, B and C operating condition – Support ISO/IEC 7816 baud rates – Support high-speed baud rates up to 1.5 Mbit/s
• Optional I2C slave mode host interface (only available on HVQFN package)
• Communication protocol compliant with ISO/IEC 7816-3 T=1 protocol
• Up to four logical channels; simultaneous multiple card support
• Support for MIFARE DESFire and MIFARE Plus authentication (with related secure messaging and session key generation)
• Secure Host to SAM and back end to SAM communication with symmetric cryptography including 3-pass authentication for confidentiality and integrity
• Secure Host to SAM and back end to SAM communication with RSA-based cryptography for key updating
• X-mode direct interface with NXP’s contactless reader ICs (RC663, RC52x, PN512)

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 3 / 31

2.3 Programmable logic (restricted feature) 2

• Up to 32 kB of code and data in EEPROM for user customized functionality
• 1 kB of RAM for user’s dynamic data
• Internal Host access to all MIFARE SAM AV3 commands

2.4 Security evaluation and certification

• CC EAL6+ certified hardware platform (based on NXP’s SmartMX2 P6022y VB)
• Composite certified with MIFARE Security Evaluation Scheme (Equivalent to EMVCo Security Evaluation) (Evaluation lab: TÜViT, Certification lab: UL)
• FIPS140-2 CAVP certified

2.5 New features

This section gives an overview of the new features compared to MIFARE SAM AV2. Please see [1] for details.

• All new features from MIFARE DESFire EV2 requiring cryptographic operations. This includes EV2 secure messaging and Transaction MAC support (incl CommitReaderID).
• All new features from MIFARE Plus EV1 requiring cryptographic operations. This includes EV1 secure messaging, Transaction MAC support (incl CommitReaderID) and Sector Security Level Switching.
• New Virtual Card Selection and Proximity Check protocols.
• Post-Delivery Configuration support.
• MIFARE Ultralight EV1 password authentication.
• AES authentication according to ISO/IEC 29167-10 for UCODE and ICODE support.
• LRP support for DESFire secure messaging, as supported by DESFire Light and NTAG42x(TT) and for Offline Crypto operations.
• ECC originality signature verification as supported by all recent MIFARE products.
• Generic CMAC-based key derivation for a.o. Transaction MAC session key generation and (e.g. UCODE) key diversification.
• Fine-grained key access control.
• EMV terminal support for certificate verification, offline authentication and pin code verification.
• Programmable Logic feature to allow customized business logic and a.o. key diversifications to be run within the SAM.
• Personalization SAM feature to generate cryptogram to export keys for injection in another SAM for AES variant and for RSA variant.
• AES-256 support for Offline Crypto and SAM-Host protection.
• RSA OAEP encryption and decryption.
• ATR configuration.
• I2C slave interface in addition to ISO/IEC 7816 interface (for HVQFN only). 2 Note: The PL code uploading functionality is only available to a limited set of customers.

3 Ordering information

Table 1. Ordering information

4 Block diagram

Figure 1. Block diagram

5 Pinning information

5.1 Pin description

Figure 2. Pin configuration PCM1.5 Table 2. Pin description PCM 1.5 MIFARE SAM AV3

5.1.2 HVQFN32 pin configuration

Remark: Central pad is isolated. Figure 3. Pin configuration HVQFN32

Table 3. Pin description HVQFN32 MIFARE SAM AV3

1 GND ground (reference voltage) input

3 IO3 used for I2C communication to RC (SCL)

5 IO1 input/output for serial data (ISO7816 or SDA_Slave for I2C host

7 IO2 used for I2C communication to RC (SDA)

24 VCC power supply voltage input

22 RST_N reset input, active LOW

18 CLK_N clock input

29 TP2 SCL_Slave: used for I2C communication to Host when I2C host

30 TP1 I2C_Enable: enable I2C host communication when high

6 Limiting values

Table 4. Limiting values [1] If IO2 and IO3 are available. Testing - Human Body Model (HBM) - Component Level. [3] Only available if enabled via OEF setting. [4] In accordance with JEDEC JESD22-C101 for Charged-Device Model (CDM). [5] Depending on appropriate thermal resistance of the package. Semiconductors Contact & Dual Interface Chip Card Module Specification (16). precautions for handling electrostatic sensitive devices. JESD625-A or equivalent standards.

7 Recommended operating conditions

Table 5. Operating conditions [1] All described supply voltages according to ISO/IEC 7816-3. voltage range described in Figure 4. Figure 4. Operating conditions over voltage range

8 Static characteristics

8.1 Measurement conventions

the Smart Card IC are considered positive.

8.2 Levels and currents

Table 6. Electrical DC characteristics of Input/Output: IO1, IO2 and IO3

0.7 VDD ≤ VI ≤ VDD;

0.3 VDD < VI ≤ VDD;

0 V ≤ VI ≤ VDD;

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 11 / 31 Symbol Parameter Conditions Min Typ Max Unit IILIH Leakage input current at input voltage beyond VDD in "weak pull-up" input mode VDD < VI ≤ VDD + 0.3 V; -25 °C ≤ Tamb ≤ +85 °C; Test conditions: VI = VDD + 0.3 VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +85 °C - - 20 μA -0.3 V ≤ VI < 0 V; -25 °C ≤ Tamb ≤ +30 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +30 °C - - -50 μAIILIL Leakage input current at input voltage below VSS in "weak pull-up" input mode -0.3 V ≤ VI < 0 V; +30 °C < Tamb ≤ +85 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +85 °C - - -275 μA IILIHQ Leakage input current at input voltage beyond VDD (only in "quasi- bidirectional" mode) VDD < VI ≤ VDD + 0.3 V; -25 °C ≤ Tamb ≤ +85 °C Test conditions: VI = VDD +

0.3 V; VDD = VDD(max) of the

respective supply voltage class A, B or C; Tamb = +85 °C - - 100 μA -0.3 V ≤ VI < 0 V; -25 °C ≤ Tamb ≤ +30 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +30 °C - - -75 μAIILILQ Leakage input current at input voltage below VSS (only in "quasi- bidirectional" mode) -0.3 V ≤ VI < 0 V; +30 °C < Tamb ≤ +85 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +85 °C - - -300 μA IOH = -20 μA; Class A condition [2] 3.8

0.7 VDD

• - VVOH HIGH level output voltage IOH = -20 μA; Class B or C condition [2] 0.7 VDD - - V Class A or B condition; IOL = 1.0 mA - - 0.3 VVOL LOW level output voltage Class C condition; IOL = 1.0 mA IOL = 0.5 mA - - 0.3

0.15 VDD

V

Figure 5 shows the input characteristic of this quasi-bidirectional port mode. current of IOH = -20 μA - the strong output drive mode must be used. Table 7. Electrical DC characteristics of Inputs CLK and RST_N[1][2]

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 13 / 31 Symbol Parameter Conditions Min Typ Max Unit -0.3 V ≤ VI < 0 V; +30 °C < Tamb ≤ +85 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +85 °C - - -200 μA Input CLK (during IC reset) VIH2 HIGH level input voltage 0.7 VDD - VDD + 0.3 V VIL2 LOW level input voltage -0.3 - 0.25 VDD V IIH2 HIGH level input current (weak pull-up is on) Test conditions for the maximum absolute value: IIH2(max): VI = 0.7 VDD, VDD = VDD(max) of the respective supply voltage class A, B or C 0 - -20 μA IIL2 HIGH level input current (weak pull-up is on) 0 V ≤ VI ≤ 0.3 VDD; Test conditions for the maximum absolute value: IIL2(max): VI = 0V, VDD = VDD(max) of the respective supply voltage class A, B or C - - -20 μA II2 Input current (weak pull-up is on) Test conditions for the maximum absolute value: II2(max): VI = 0 V, VDD = VDD(max) of the respective supply voltage class A, B or C 0 - -20 μA IILIH2 Leakage input current at input voltage beyond VDD VDD < VI ≤ VDD + 0.3 V; -25 °C ≤ Tamb ≤ +85 °C Test conditions: VI = VDD + 0.3 VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +85 °C - - 20 μA -0.3 V ≤ VI < 0 V; -25 °C ≤ Tamb ≤ +30 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +30 °C - - -50 μAIILIL2 Leakage input current at input voltage below VSS -0.3 V ≤ VI < 0 V; +30 °C < Tamb ≤ +85 °C Test conditions: VI = -0.3 V; VDD = VDD(max) of the respective supply voltage class A, B or C; Tamb = +85 °C - - -200 μA

level, in order to minimize the power consumption. VDD. Figure 8 shows this input characteristic. Table 8. Electrical DC characteristics of TP1 and TP2

0.7 VDDAE ≤ VI ≤ VDDAE;

Figure 7. Input characteristic of CLK when the IC is not in reset and of RST_N Figure 8. Input characteristic of CLK during IC reset

8.3 General and ISO/IEC 7816 I/O interface at ISO/IEC 7816-3: A/5 V, class

Table 9. Electrical characteristics of IC supply current[1]

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 17 / 31 Symbol Parameter Conditions Supply voltage class Min Typ Max Unit no coprocessor active fCLK = 10 MHz, CPU at fCLK A (5 V) B (3 V) C (1.8 V) - 1.60 4.00 mA no coprocessor active fCLK = 10 MHz, CPU in free running mode A (5 V) B (3 V) C (1.8 V) - 2.50 4.00 mA DES coprocessor active (DES int. 32 MHz) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 4.00 6.00 mA DES coprocessor active (DES int. 96 MHz) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 8.60 10.50 mA AES coprocessor active (AES int. 32 MHz) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 3.10 5.00 mA AES coprocessor active (AES int. 96 MHz) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 5.60 8.00 mA Fame2 coprocessor active (Fame2 clock = 16 MHz, double multiplier mode) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 3.90 6.50 mA Fame2 coprocessor active (Fame2 clock = 48 MHz, double multiplier mode) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 5.40 8.50 mA Fame2 coprocessor active (Fame2 clock = free running, double multiplier mode) fCLK = 10 MHz, CPU at int. 4 MHz A (5 V) B (3 V) C (1.8 V) - 5.40 10.50 mA IDD(ID) supply current CPU IDLE mode (this parameter should not be mixed-up with the ETSI "idle state") fCLK = 10 MHz, Tamb = 25 °C A (5 V) B (3 V) C (1.8 V) - 0.80 1.50 mA IDD(SLP) supply current SLEEP mode (this parameter should not be mixed-up with the ETSI "idle state") fCLK = 10 MHz, Tamb = 25 °C (VDDCO power domain switched off) A (5 V) B (3 V) C (1.8 V) - 175.00 150.00 200.00 μA A (5 V) - 80.00 200.00 μAIDD(PD) supply current CLOCKSTOP mode VDDmin ≤ VDD ≤ VDDmax; Clock to input CLK stopped, Tamb = 25 °C (VDDCO power domain and CLIF switched off) B (3 V) C (1.8 V) - 60.00 100.00 μA [1] Typical values are only referenced for information. They are subject to change without notice.

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 18 / 31

9 Dynamic characteristics

Remark: The P6022y VB only supports one single IO1.

9.1 General, ISO/IEC 7816 I/O and ISO/IEC 14443 I/O interfaces

Table 10. Electrical AC characteristics of IO1, IO2, IO3, CLK and RST_N

applications

tCLKW, Tamb and VDD in their spec'd limits tCLKW Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK) [5] 40 - 60 % trCLK CLK input rise time [6] - - see [6] tfCLK CLK input fall time [6] - - see [6] trRST RST_N input rise time [7] - - 400 μs tfRST RST_N input fall time [7] - - 400 μs tRW Reset pulse width (RST_N low) 40 - - μs tWKP Wake-up time from SLEEP mode fCLKmin ≤ fCLK ≤ fCLKmax - 17 20 μs level triggered ext.int. - 20 - μstWKPIO I/Ox LOW time for wake-up from SLEEP mode edge triggered ext.int. - 20 - μs tWKPRST RST_N LOW time for wake-up from SLEEP mode 40 - - μs Inputs: CLK, RST_N, IO1, IO2, IO3 CPIN Pin capacitances CLK, RST_N, IO1, IO2, IO3 Test frequency = 1 MHz; Tamb = 25 °C - - 10 pF [1] Typical values are only referenced for information. They are subject to change without notice.

minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example. matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221. yields the allowed limits of 0.85 MHz and 11.5 MHz. level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD (see Figure 9). maximum allowed CLK rise and fall time is 50 ns, if 10% of the CLK period is shorter than 50 ns. [7] The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively. Figure 9. External clock drive and AC test timing reference points of CLK, RST_N, IO1, IO2 and IO3 (see [1] and [2]) level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD. [2] tr is defined as rise time between 10% and 90% of the signal amplitude. tf is defined as fall time between 90% and 10% of the signal amplitude. Table 11. Electrical AC characteristics of TP1 and TP2

9.2 Non-Volatile memory

Table 12. Non-volatile memory characteristics [1] Typical values are only referenced for information. They are subject to change without notice. [2] Given value specifies physical access times of EEPROM memory only.

9.3 I2C Slave interface bus timing

Table 13. Non-volatile memory characteristics

Figure 10. Timing for I2C Slave bus

Figure 11. Package outline SOT617-3

Figure 12. Package outline SOT658-1

11 Packing information

leader : lenght of trailer shall be 400mmmin. trailer : lenght of trailer shall be 160mmmin. Figure 13. Packing information for HVQFN32 package - Reel

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 25 / 31

12 References

[1] Data sheet — MF4SAM3 MIFARE SAM AV3 secure access module product daa sheet, Doc No. 32353 3 denote the document version number

Table 14. Revision history

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 27 / 31

14 Legal information

14.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 28 / 31 No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. MIFARE — is a trademark of NXP B.V. DESFire — is a trademark of NXP B.V. ICODE and I-CODE — are trademarks of NXP B.V. UCODE — is a trademark of NXP B.V. MIFARE Plus — is a trademark of NXP B.V. MIFARE Ultralight — is a trademark of NXP B.V. MIFARE Classic — is a trademark of NXP B.V. NTAG — is a trademark of NXP B.V.

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 29 / 31 Tables Tab. 3. Pin description HVQFN32 MIFARE SAM Tab. 6. Electrical DC characteristics of Input/Output: Tab. 7. Electrical DC characteristics of Inputs CLK Tab. 10. Electrical AC characteristics of IO1, IO2,

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Product short data sheet Rev. 3.0 — 2 August 2019 COMPANY PUBLIC 561930 30 / 31 Figures Fig. 5. Input characteristic of IO1, IO2, IO3 in Fig. 6. Input characteristic of IO1, IO2, IO3 in "weak Fig. 7. Input characteristic of CLK when the IC is not Fig. 9. External clock drive and AC test timing reference points of CLK, RST_N, IO1, IO2 Fig. 13. Packing information for HVQFN32 package

NXP Semiconductors MF4SAM3 MIFARE SAM AV3 secure access module Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2019. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 August 2019 Document identifier: MF4SAM3 Document number: 561930

Contents

8.3 General and ISO/IEC 7816 I/O interface at

ISO/IEC 7816-3: A/5 V, class B/3 V or class

9.1 General, ISO/IEC 7816 I/O and ISO/IEC