MF38M1-L6DAGXX

MF38M1-L6DAGXX MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

Mitsubishi’s Static RAM cards provide large memory capacities on a device approximately the size of a credit card (85.6mm × 54mm × 5.0mm). The cards use an 8/16 bit data bus. Availabale in 8MB capacities, Mitsubishi’s SRAM cards conform to the JEIDA/PCMCIA standard. Mitsubishi acheived high density memory, while maintaining credit size by using a thin small outline packaging technology(TSOP). The TSOP surpasses conventional memory card chip-on-board packaging technology where larger, surface-mount devices result in a tradeoff between card size and optimum memory density. This allows up to 16 memory Ics (plus interface circuitry) to be mounted in a card that in only 5.0mm thick. MF38M1-L6DAGXX

FEATURES

nUses TSOP (Thin Small Outline Package) to achieve very high memory density coupled with high reliability, without enlarging card size. nOne to 16 memory ICs can be mounted in a card that is only 5.0mm thick. nElectrostatic discharge protection to 15kV nBuffered interface nWrite protect switch nAttribute memory n68pin JEIDA/PCMCIA APPLICATION S nOffice automation nIndustrial nData Communication nTelecommunications nComputers nConsumer PRODUCT LIST Item Memory Data Bus Attribute Auxialiary Memory Outline Main battery Type name capacity width(bits) memory battery organization drawing holder MF38M1-L6DAGXX 8MB 8/16 YES NO 4M bit SRAM × 16 68P-010 Screw type

Two-Piece Type (68-pin) Pin Pin No. No.

1 GND Ground 35 GND Ground

2 D3 36 CD1# Card detect 1

3 D4 37 D11

4 D5 Data I/O 38 D12

5 D6 39 D13 Data I/O

6 D7 40 D14

7 CE1# Card enable 1 41 D15

8 A10 Address input 42 CE2# Card enable 2

9 OE# Output enable 43 NC

10 A11 44 NC No connection

11 A9 45 NC

12 A8 Address input 46 A17

13 A13 47 A18

14 A14 48 A19 Address input

15 WE# Write enable 49 A20

16 NC No connection 50 A21

17 V CC Power supply voltage 51 V CC Power supply voltage

18 NC No connection 52 NC No connection

19 A16 53 A22 Address input

20 A15 54 NC

21 A12 55 NC

22 A7 56 NC

23 A6 57 NC No connection

24 A5 Address input 58 NC

25 A4 59 NC

26 A3 60 NC

27 A2 61 REG # REG function

28 A1 62 BVD2 Battery voltage detect 2

29 A0 63 BVD1 Battery voltage detect 1

30 D0 64 D8

31 D1 Data I/O 65 D9 Data I/O

32 D2 66 D10

33 WP Write protect 67 CD2# Card detect 2

34 GND Ground 68 GND Ground

WRITE PROTECT MODE (WP) When the write protect switch is switched on, this card goes into a write protect mode that can read but not write data. In this mode, WP pin becomes “H” level. At the shipment the write protect switch is switched off (Normal mode : The card can be written ; WP pin indicates “L” level). SymbolSymbol FunctionFunction

BLOCK DIAGRAM (8MB) FUNCTION TABLE Mode REG# CE1# CE2# OE# WE# A0 I/O (D15~D8) I/O (D7~D0) I CC Standby X H H X X X High-impedance High-impedance standby Read A (16bit) common H L L L H X Odd Byte Data out Even Byte Data out Active Write A (16bit) common H L L H L X Odd Byte Data in Even Byte Data in Active H L H L H L High-impedance Even Byte Data out Active H L H L H H High-impedance Odd Byte Data out Active H L H H L L High-impedance Even Byte Data in Active H L H H L H High-impedance Odd Byte Data in Active Read C (8bit) common H H L L H X Odd Byte Data out High-impedance Active Write C (8bit) common H H L H L X Odd Byte Data in High-impedance Active Output disable X X X H H X High-impedance High-impedance Active Read A (16bit) attribute L L L L H X Data out (unknown) Even Byte Data out Active L L H L H L High-impedance Even Byte Data out Active L L H L H H High-impedance Data out (unknown) Active Read C (8bit) attribute L H L L H X Data out (unknown) High-impedance Active Write A (16bit) attribute L L L H L X don’t care Even Byte Data in Active L L H H L L don’t care Even Byte Data in Active L L H H L H don’t care don’t care Active Write C (8bit) attribute L H L H L X don’t care don’t care Active Note 1 : H=V IH , L=V IL, X=V IH or V IL Read B (8bit) common Write B (8bit) common Read B (8bit) attribute Write B (8bit) attribute A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 D15 D14 D13 D12 D11 D10 BVD2 WE# OE# CE1# CE2# REG# WP# WRITE PROTECT ONOFF CD1# CD2# BR2325 V CC VOLTAGE DETECTOR POWER CONTROLLER ATTRIBUTE MEMORY 64Kbit E 2 PROM × 1MODE CONTROL LOGIC ADDRESS- BUS BUFFERS ADDRESS- DECODER COMMON MEMORY 4Mbit SRAM × 16 CS# DATA-BUS BUFFERS GND OE# WE# OE# WE# CS# 8 TO INTERNAL POWER SUPPLY BVD1

Symbol Parameter Conditions Ratings Unit V CC Supply voltage -0.3~6.0 V Vi Input voltage With respect to GND -0.3~V CC +0.3 V V o Output voltage 0~V CC V T opr1 Operating temperature 1 Read, Write, Operation 0~70 °C T opr2 Operating temperature 2 Data retention 0~70 °C T stg Storage temperature -30~80 °C RECOMMENDED OPERATING CONDITIONS (Ta=0~55°C, unless otherwise noted) Limits Min. Typ. Max. V CC V CC supply voltage 4.75 5.0 5.25 V GND System ground 0 V V IH High input voltage 2.4 V CC V V IL Low input voltage 0 0.8 V ELECTRICAL CHARACTERISTICS (Ta=0~55°C, V CC =5V±5%, unless otherwise noted) Limits Min. Typ. Max. V OH High output voltage I OH =-1.0mA, Other outputs 2.4 V V OL Low output voltage I OL =2mA 0.4 V I IH High input current V I =V CC V 10 µA I IL Low input current V I =0V CE1#, CE2#, WE#, OE#, REG# -10 -70 µA Other inputs -10 I OZH High output current CE1#=CE2#=V IH or OE#=V IH WE#=V IH , 10 µA in off state V O =V CC I OZL Low output current CE1#=CE2#=V IH or OE#=V IH WE#=V IH , -10 µA in off state V O =0V I CC 1 • 1 Active supply current 1 CE1#=CE2#=V IL , other inputs V IH or V IL ,Outputs=open 280 mA I CC 1 • 2 Active supply current 2 CE1#=CE2# ≤ 0.2V, other inputs ≤ 0.2V or ≥ V CC -0.2V, Outputs=open 270 mA I CC 2 • 1 Standby supply current 1 CE1#=CE2#=V IH other inputs=V IH or V IL 10 mA I CC 2 • 2 Standby supply current 2 CE1#=CE2# ≥ V CC -0.2V other inputs ≤ 0.2V or ≥ V CC -0.2V 1 mA VBDET1 Battery detect Vcc=5V,Ta=25 °C V reference voltage 1 ¬ VBDET 2 Battery detect Vcc=5V,Ta=25 °C V reference voltage 2 ¬ Note 2 : Currents flowing into the IC are taken as positive (unsigned). 3 : Typical values are measured at V CC =5V, Ta=25°C.¬Pin asserted when battery voltage drops below specified level. Unit Symbol Parameter Unit 2.37 2.65 2.75 Symbol Parameter Test conditions 2.47 2.55 2.27

Min. Typ. Max. C I Input capacitance V I =GND, V I =25mVrms 30 pF f=1 MH Z , Ta=25°C C O Output capacitance V O =GND, V O =25mVrms f=1 MH Z , Ta=25°C 20 pF Note 4 : These parameters are not 100% tested. SWITCHING CHARACTERISTICS Read Cycle (Ta=0~55°C, V CC =5V±5%, unless otherwise noted) Limits Symbol Parameter Min. Typ. Max. Unit t CR Read cycle time 200 ns t a (A) Address access time 200 ns t a (CE) Card enable access time 200 ns t a (OE) Output enable accese time 100 ns t dis (CE) Output disable time (from CE#) 90 ns t dis (OE) Output disable time (from OE#) 90 ns t en (CE) Output enable time (from CE#) 5 ns t en (OE) Output enable time (from OE#) 5 ns t V (A) Data valid time (after address change) 0 ns TIMING REQUIREMENTS Write Cycle (Ta=0~55°C, V CC =5V±5%, unless otherwise noted) Limits Symbol Parameter Min. Typ. Max. Unit t CW Write cycle time 200 ns t w(WE) Write pulse width 120 ns t su(A) Address set up time 20 ns t su(A-WEH) Address set up time with respect to WE# high 140 ns t su(CE-WEH) Card enable set up time with respect to WE# high 140 ns t su(D-WEH) Data set up time with respect to WE# high 60 ns t h(D) Data hold time 30 ns t rec(WE) Write recovery time 30 ns t dis(WE) Output disable time (from WE#) 90 ns t dis(OE) Output disable time (from OE#) 90 ns t en(WE) Output enable time (from WE#) 5 ns t en(OE) Output enable time (from OE#) 5 ns t su(OE-WE) OE# set up time with respect to WE# low 10 ns t h(OE-WE) OE# hold time with respect to WE# high 10 ns Symbol UnitParameter Test conditions

WE#=“H” level REG#=“H” level Note 5 : Indicates the don’t care input Write Cycle (WE# control) REG#=“H” level tCR ta (A) ta (CE) ten (CE) ten (OE) tdis (OE) tV(A) ta (OE) OUTPUT VALID Hi-Z tdis(CE) An V IH Dm (D OUT ) V OH V OL OE# V IH V IL CE# V IH V IL V IL Dm (D OUT ) V OH V OL Hi-Z ten(OE) tCW tSU(CE-WEH) tSU(A-WEH) tSU(A) th (OE-WE) V IH V IL An tW(WE) tSU(OE-WE) CE# V IH V IL tdis(OE) tdis(WE) Dm (D IN ) V IH V IL V IL WE# V IH OE# V IH V IL trec(WE) th(D)tSU(D-WEH) ten(WE) DATA INPUT STABLEHi-Z

Write Cycle (CE# control) OE#=“H” level REG#=“H” level tCW tSU(CE-WEH) V IH V IL An CE# V IH V IL Dm (D IN ) V IH V IL V IL WE# V IH tSU(A) trec(WE) th(D)tSU(D-WEH) DATA INPUT STABLEHi-Z

SWITCHING CHARACTERISTICS (Attribute) Read Cycle (Ta=0~55°C, V CC =5V±5%, unless otherwise noted) Limits Symbol Parameter Min. Typ. Max. Unit t CR R Read cycle time 300 ns t a(A) R Address access time 300 ns t a(CE) R Card enable access time 300 ns t a(OE) R Output enable access time 150 ns t dis(CE) R Output disable time (from CE#) 100 ns t dis(OE) R Output disable time (from OE#) 100 ns t en(CE) R Output enable time (from CE#) 5 ns t en(OE) R Output enable time (from OE#) 5 ns t V(A) R Data valid time after address change 0 ns TIMING REQUIREMENTS (Attribute) Writte Cycle (Ta=0 ∼55 °C, V CC =5V ±5%, unless otherwise noted) Limits Symbol Paramete Min. Typ. Max. Unit t AS R Address setup time 30 ns t AH R Address hold time 30 ns t CS R CE# setup time 40 ns t CH R CE# hold time 30 ns t DS R Data setup time 120 ns t DH R Data hold time 40 ns t ODS R OE# setup time 30 ns t OEH R OE# hold time 40 ns t WP R Write pulse width 170 ns t DL R Data latch time 120 ns t BL R Byte load time 100 µs t BLC R Byte load cycle time 0.3 30 µs t WC R Write cycle time 10 ms ten (OE) R Output enable time from OE# 5 ns t DF R Output disable time from OE# 0 100 ns

TIMING DIAGRAM (Attribute) Read Cycle WE#=“H” level REG#=“L” level BYTE WRITE TIMING CHART REG#=“L” level tCR R ta (A) R ta (CE) R ten (CE) R ten (OE) R tdis (OE) R tV(A) R ta (OE) R OUTPUT VALID Hi-Z tdis(CE) R An V IH Dm (D OUT ) V OH V OL OE# V IH V IL CE# V IH V IL V IL D OUT V OH V OL Hi-Z ten(OE) R tAH R tCH R tWP RtAS R V IH V IL An tCS R tBL R CE# V IH V IL tDF R tDS R D IN V IH V IL V IL WE# V IH OE# V IH V IL tOES R tDH R Hi-Z tWC R tOE R

PAGE MODE WRITE TIMING CHART REG#=“L” level Note 6 : Test Conditions Input pulse levels : V IL =0.4V, V IH =2.8V Input pulse rise, fall time : tr=tf=10ns Reference voltage Input : V IL =0.8V, V IH =2.4V Output : V OL =0.8V, V OH =2.0V (ten and tdis are measured when output voltage is± 500mV from steady state. ) Load : 100pF+1 TTL gate 5pF+1 TTL gate (at ten and tdis measuring) 7 : Writing is executed in overlap of CE# and WE# are “L” level. (only for Common Memory) 8 : Don’t apply inverted phase signal externally when Dm pin is in output mode. 9 : CE# is indicated as follows: Read A/Write A : CE#=CE1#=CE2# Read B/Write B : CE#=CE1#, CE2#=“H” level Read C/Write C : CE#=CE2#, CE1#=“H” level tDF R Hi-Z An=(n>6) An (A 0 ~A 5 ) CE# OE# WE# D IN tWP R tDL R tOES R tAS R tBLC R tCH R tAH R tCS R tDS R tDH R 0h 2h 4h 3Ch 3Eh D OUT Hi-Z tBL R tWC R tOEH R

ELECTRICAL CHARACTERISTICS

BATTERY BACKUP (Ta=0~55°C, unless otherwise noted) Limits Symbol Parameter Test Conditions Min. Typ. Max. Unit V BATT Back-up enable battery voltage All pins open 2.6 V V I(CE) Card enable voltage 2.4V ≤V CC ≤5.25V 2.4 V 0V ≤V CC <2.4V V CC -0.1 V CC VCC+0.1 All pins open, I CC (BUP) Battery back-up supply current V BATT =3V, 17 µA Ta=25°C I CC (BUP) Battery back-up supply current All pins open, 400 µA V BATT =3V TIMING REQUIREMENTS (Ta=0~55°C, unless otherwise noted) Limits Symbol Parameter Min. Typ. Max. Unit t pr Power supply rise time 0.1 300 ms t pf Power supply fall time 3 300 ms t su(VCC) Setup time at power on 20 ms t rec(VCC) Recovery time at power off 1000 ns CARD INSERTION/REMOVAL TIMING DIAGRAM V CC MIN means Minimum Operating Voltage=4.50V. Note 10: When the card is holding valuable data, the battery must not be removed unless V CC is present. BATTERY SPECIFICATIONS A replaceable battery (type BR2325) with a capacity of 165mAH is used: Estimated battery life when the card is left continuously. MF38M1-L6DAGXX 1.0years Conditions Temperature : 25 °C Humidity : 60%RH trec(V CC ) tpf 90% VIH 10% V CC CE1#, CE2# tsu(V CC ) tpr 90% VIH 10% V CC CE1, CE2 V CC MIN V CC MIN