MF283C154-L16

80C154 TEMIC | Alldatasheet

Document overview

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Technical content

Features

16 Kbytes of ROM (83C154)

32 Programmable I/O lines (programmable impedance)

Three 16 bit timer/counters (including watchdog and 32 bit timer)

64 K program memory space

64 K data memory space

0.8µ CMOS process Boolean processor 6 interrupt sources Programmable serial port Temperature range : commercial, industrial, automotive, military Optional Secret ROM : Encryption Secret TAG : Identification number CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller

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Figure 1. Block Diagram

Figure 2. Pin Configuration

Rev.F (14 Jan. 97)

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Circuit Ground Potential. VCC Supply voltage during normal, Idle, and Power Down operation. Port 0 Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program verification in the 83C154. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs. Port 1 Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address byte during program verification. In the 83C154, Port 1 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. 2 inputs of PORT 1 are also used for timer/counter 2 : P1.0 [T2] : External clock input for timer/counter 2. P1.1 [T2EX] : A trigger input for timer/counter 2, to be reloaded or captured causing the timer/counter 2 interrupt. Port 2 Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. It also receives the high-order address bits and control signals during program verification in the 83C154. Port 2 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. Port 3 Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special features of the TEMIC 51 Family, as listed below. Port Pin Alternate Function P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) TD (Timer 0 external input) T1 (Timer 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe) Port 3 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. RST A high level on this for two machine cycles while the oscillator is running resets the device. An internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC. As soon as the result is applied (Vin), PORT 1, 2 and 3 are tied to 1. This operation is achieved asynchronously even if the oscillator is not start up.

Rev.F (14 Jan. 97)

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PCON : Power Control Register (MSB) (LSB) SMOD HPD RPD – GF1 GF0 PD IDL Symbol Position Name and Function SMOD PCON.7 Double Baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. HPD PCON.6 Hard power Down bit. Setting this bit allows CPU to enter in Power Down state on an external event (1 to 0 transition) on bit T1 (p. 3.5) the CPU quit the Hard Power Down mode when bit T1 p. 3.5) goes high or when reset is activated. RPD PCON.5 Recover from Idle or Power Down bit. When 0 RPD has no effetc. When 1, RPD permits to exit from idle or Power Down with any non enabled interrupt source (except time 2). In this case the program start at the next address. When interrupt is enabled, the appropriate interrupt routine is serviced. GF1 PCON.3 General-purpose flag bit. GF0 PCON.2 General-purpose flag bit. PD PCON.1 Power Down bit. Setting this bit activates power down operation. IDL PCON.0 Idle mode bit. Setting this bit activates idle mode operation. If 1’s are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000). Idle Mode The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle mode the CPU status is preserved in its entirety : the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during idle. In the idle mode, the internal clock signal is gated off to the CPU, but interrupt, timer and serial port functions are maintained. Table 1 describes the status of the external pins during Idle mode. There are three ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed will be the one following the instruction that wrote 1 to PCON.0. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. The second way of terminating the Idle mode is with a hardware reset. Since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation. The third way to terminate the Idle mode is the activation of any disabled interrupt when recover is programmed (RPD = 1). This will cause PCON.0 to be cleared. No interrupt is serviced. The next instruction is executed. If interrupt are disabled and RPD = 0, only a reset can cancel the Idle mode. Power Down Mode The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator is stopped. The contents of the onchip RAM and the Special Function Register is saved during power down mode. The three ways to terminate the Power Down mode are the same than the Idle mode. But since the onchip oscillator is stopped, the external interrupts, timers and serial port must be sourced by external clocks only, via INT0, INT1, T0, T1. In the Power Down mode, VCC may be lowered to minimize circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator has restarted and stabilized. When using voltage reduction : interrupt, timers and serial port functions are guaranteed in the VCC specification limits. Table 1 describes the status of the external pins while in the power down mode. It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the port switches from 0 to 1, the port pin is held high during the power down mode by the strong pullup, T1, shown in figure 4.

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Figure 6. External Drive Configuration. are selected by bits in T2CON as shown in Table 2. Table 2.Timer 2 Operating Modes. The capture mode is illustrated in Figure 7. the 16 bit reload and set EXF2. The auto-reload mode is illustrated in Figure 8. Figure 7. Timer 2 in Capture Mode. Figure 8. Timer 2 in Auto-Reload Mode.

Rev.F (14 Jan. 97) 9MA TRA MHS (MSB) (LSB) TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1. Symbol Position Name and Significance TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 OR TCLK = 1. EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. C/T2 T2CON.1 Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). CP/RL2 T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2 overflows or negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Timer Functions In fact, timer 0 & 1 can be connected by a software instruction to implement a 32 bit timer function. Timer 0 (mode 3) or timer 1 (mode 0, 1, 2) or a 32 bit timer consisting of timer 0 + timer 1 can be employed in the watchdog mode, in which case a CPU reset is generated upon a TF1 flag. The internal pull-up resistances at ports 1~3 can be set to a ten times increased value simply by software.

32 Bit Mode and Watching Mode

The 83C154 has two supplementary modes. They are accessed by bits WDT and T32 of register IOCON. Figure 10 showns how IOCON must be programmed in order to have access to these functions Figure 9. 32 bit timer [IOCON bit 6 (T32) = 1] Watchdog timer

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T32 IOCON.6 – If T32 = 1 and if C/T0 = 0, T1 and T0 are programmed as a 32 bit TIMER. – If T32 = 1 and if C/T0 = 1, T1 and T0 are programmed as a 32 bit COUNTER. WATCHDOG is configured from TIMERS 0 and 1.

32 Bit Mode

Figure 10.32 Bit Timer/counter. T32 = 1 starts the timer/counter and T32 = 0 stops it. 1 assume the configuration specified by register TMOD.

32 Bit Timer

Figure 12 illustrates the 32 bit TIMER mode. Figure 11. 32 Bit Timer Configuration. 32 bit TIMER is signalled by setting TF1 (S5P1) to 1.

32 Bit Counter

Figure 13 illustrates the 32 bit COUNTER mode. Figure 12. 32 Bit Counter Configuration. machine cycle or, in other words, every OSC ÷ 12. Figure 13. Counter Incrementation Condition. detected during state S5P2 of cycle Ci + n. should be used to calculate the operating frequency. Figure 14. The Different Watchdog Configurations.

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the values shown in Table 3. Table 3. Content of the SFRS after a reset triggered is in the WATCHDOG MODE (T32 = ICON.7 = 1).

Rev.F (14 Jan. 97) 13MA TRA MHS 83C154 with Secret ROM TEMIC offers 83C154 with the encrypted secret ROM option to secure the ROM code contained in the 83C154 microcontrollers. The clear reading of the program contained in the ROM is made impossible due to an encryption through several random keys implemented during the manufacturing process. The keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. This encryption is activated during the following phases : – Everytime a byte is addressed during a verify of the ROM content, a byte of the encryption array is selected. – MOVC instructions executed from external program memory are disabled when fetching code bytes from internal memory. – EA is sampled and latched on reset, thus all state modification are disabled. For further information please refer to the application note (ANM053) available upon request. 83C154 with Secret TAG TEMIC offers special 64-bit identifier called “SECRET TAG” on the microcontroller chip. The Secret Tag option is available on both ROMless and masked microcontrollers. The Secret Tag feature allows serialization of each microcontroller for identification of a specific equipment. A unique number per device is implemented in the chip during manufacturing process. The serial number is a 64-bit binary value which is contained and addressable in the Special Function Registers (SFR) area. This Secret Tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. This routine is implemented inside the microcontroller ROM memory in case of masked version which can be kept secret (and then the value of the Secret Tag also) by using a ROM Encryption. For further information, please refer to the application note (ANM031) available upon request.

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Electrical Characteristics

Absolute Maximum Ratings* Ambiant Temperature Under Bias : ** This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = 0°C to 70°C ; Vcc = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz TA = –40°C + 85°C ; Vcc = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 Vcc – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 Vcc + 1.4 Vcc + 0.5 V VIH1 Input High V oltage (for XTAL and RST) 0.7 Vcc Vcc + 0.5 V VOL Output Low V oltage (Port 1, 2 and 3) 0.3 0.45 1.0 V V V IOL = 100 µA IOL = 1.6 mA (note 2) IOL = 3.5 mA VOL1 Output Low V oltage (Port 0, ALE, PSEN) 0.3 0.45 1.0 V V V IOL = 200 µA IOL = 3.2 mA (note 2) IOL = 7.0 mA VOH Output High V oltage Port 1, 2 and 3 Vcc – 0.3 V IOH = – 10 µA Vcc – 0.7 V IOH = – 30 µA Vcc – 1.5 V IOH = – 60 µA VCC = 5 V ± 10 % VOH1 Output High V oltage (Port 0, ALE, PSEN) Vcc – 0.3 V IOH = – 200 µA Vcc – 0.7 V IOH = – 3.2 mA Vcc – 1.5 V IOH = – 7.0 mA VCC = 5 V ± 10 % IIL Logical 0 Input Current (Ports 1, 2 and 3) – 50 µA Vin = 0.45 V ILI Input leakage Current +/– 10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) – 650 µA Vin = 2.0 V IPD Power Down Current 50 µA Vcc = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 KOhm CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, Ta = 25/C0095C ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq ≥ 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA 1.8 mA mA mA mA Vcc = 5.5 V

Rev.F (14 Jan. 97) 15MA TRA MHS Absolute Maximum Ratings* Ambient Temperature Under Bias : ** This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = –40°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 Vcc – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 Vcc + 1.4 Vcc + 0.5 V VIH1 Input High V oltage (for XTAL and RST) 0.7 Vcc Vcc + 0.5 V VOL Output Low V oltage (Port 1, 2 and 3) 0.3 0.45 1.0 V IOL = 100 µA IOL = 1.6 mA (note 2) IOL = 3.5 mA VOL1 Output Low V oltage (Port 0, ALE, PSEN) 0.3 0.45 1.0 V IOL = 200 µA IOL = 3.2 mA (note 2) IOL = 7.0 mA VOH Output High V oltage Port 1, 2 and 3 Vcc – 0.3 V IOH = – 10 µA Vcc – 0.7 V IOH = – 30 µA Vcc – 1.5 V IOH = – 60 µA VCC = 5 V ± 10 % VOH1 Output High V oltage (Port 0, ALE, PSEN) Vcc – 0.3 V IOH = – 200 µA Vcc – 0.7 V IOH = – 3.2 mA Vcc – 1.5 V IOH = – 7.0 mA VCC = 5 V ± 10 % IIL Logical 0 Input Current (Ports 1, 2 and 3) – 50 µA Vin = 0.45 V ILI Input leakage Current ±10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) – 750 µA Vin = 2.0 V IPD Power Down Current 75 µA Vcc = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 KOhm CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, Ta = 25/C0095C ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq ≥ 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA 1.8 mA mA mA mA Vcc = 5.5 V

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Absolute Maximum Ratings* Ambient Temperature Under Bias : ** This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = –55°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 Vcc – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 Vcc + 1.4 Vcc + 0.5 V VIH1 Input High V oltage (for XTAL and RST) 0.7 Vcc Vcc + 0.5 V VOL Output Low V oltage (Port 1, 2 and 3) 0.45 V IOL = 1.6 mA (note 2) VOL1 Output Low V oltage (Port 0, ALE, PSEN) 0.45 V IOL = 3.2 mA (note 2) VOH Output High V oltage (Port 1, 2, 3) 2.4 V IOH = – 60 µA Vcc = 5 V ± 10 %

0.75 Vcc V IOH = – 25 µA

0.9 Vcc V IOH = – 10 µA

(Port 0 in External Bus Mode, ALE, PEN)

2.4 V IOH = – 400 µA

Vcc = 5 V ± 10 %

0.75 Vcc V IOH = – 150 µA

0.9 Vcc V IOH = – 40 µA

IIL Logical 0 Input Current (Ports 1, 2 and 3) – 75 µA Vin = 0.45 V ILI Input leakage Current ±10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) – 750 µA Vin = 2.0 V IPD Power Down Current 75 µA Vcc = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 KOh m CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, Ta = 25/C0095C ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq ≥ 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA 1.8 mA mA mA mA Vcc = 5.5 V

Rev.F (14 Jan. 97) 17MA TRA MHS Absolute Maximum Ratings* Ambient Temperature Under Bias : ** This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = 0°C to 70°C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 16 MHz TA = –40°C to 85°C ; Vcc = 2.7 V to 5.5 V SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 VCC – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 VCC + 1.4 V VCC + 0.5 V VIH1 Input High V oltage to XTAL1 0.7 VCC VCC + 0.5 V VIH2 Input High V oltage to RST for Reset 0.7 VCC VCC + 0.5 V VPD Power Down V oltage to Vcc in PD Mode 2.0 6.0 V VOL Output Low V oltage (Ports 1, 2, 3) 0.45 V IOL = 0.8 mA (note 2) VOL1 Output Low V oltage Port 0, ALE, PSEN 0.45 V IOL = 1.6 mA (note 2) VOH Output High V oltage Ports 1, 2, 3 0.9 Vcc V IOH = – 10 µA VOH1 Output High V oltage (Port 0 in External Bus Mode), ALE, PSEN IIL Logical 0 Input Current Ports 1, 2, 3 – 50 µA Vin = 0.45 V ILI Input Leakage Current ± 10 µA 0.45 < Vin < VCC ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3) – 650 µA Vin = 2.0 V IPD Power Down Current 50 µA VCC = 2 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 kΩ CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, TA = 25/C0095C Maximum Icc (mA) OPERATING (NOTE 1) IDLE (NOTE 1) 1 MHz 0.8 mA 1 mA 1.1 mA 1.8 mA 400 µA 500 µA 600 µA 1 mA 6 MHz 4 mA 5 mA 6 mA 10 mA 1.5 mA 1.7 mA 2 mA 4 mA 12 MHz 8 mA 10 mA 12 mA 2.5 mA 3 mA 3.5 mA 16 MHz 10 mA 12 mA 14 mA 3 mA 3.8 mA 4.5 mA Freq > 12 MHz (Vcc = 5.5 V) Icc (mA) = 1.3 × Freq (MHz) + 4.5 Icc Idle (mA) = 0.36 × Freq (MHz) + 2.7

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slighty higher if a crystal oscillator used. Trigger use is not necessary. Figure 15. ICC Test Condition, Idle Mode. All other pins are disconnected. Figure 16. ICC Test Condition, Active Mode. All other pins are disconnected. Figure 17. ICC Test Condition, Power Down Mode. All other pins are disconnected. Figure 18. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.

Rev.F (14 Jan. 97) 19MA TRA MHS Explanation of the AC Symbol Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example : TA VLL = Time for Address Valid to ALE low. TLLPL = Time for ALE low to PSEN low. A : Address. C : Clock. D : Input data. H : Logic level HIGH I : Instruction (program memory contents). L : Logic level LOW, or ALE. P : PSEN. Q : Output data. R : READ signal. T : Time. V : Valid. W : WRITE signal. X : No longer a valid logic level. Z : Float. AC Parameters TA = 0 to + 70°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz TA = –55° + 125°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz TA = –55° + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz (Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF) External Program Memory Characteristics

16 MHz 20 MHz 25 MHz 30 MHz 36 MHz

SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX TLHLL ALE Pulse Width 110 90 70 60 50 TA VLL Address valid to ALE 40 30 20 15 10 TLLAX Address Hold After ALE 35 35 35 35 35 TLLIV ALE to valid instr in 185 170 130 100 80 TLLPL ALE to PSEN 45 40 30 25 20 TPLPH PSEN pulse Width 165 130 100 80 75 TPLIV PSEN to valid instr in 125 110 85 65 50 TPXIX Input instr Hold After PSEN 0 0 0 0 0 TPXIZ Input instr Float After PSEN 50 45 35 30 25 TPXA V PSEN to Address Valid 55 50 40 35 30 TA VIV Address to Valid instr in 230 210 170 130 90 TPLAZ PSEN low to Address Float 10 10 8 6 5 External Program Memory Read Cycle TAVIV

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External Data Memory Characteristics SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX TRLRH RD pulse Width 340 270 210 180 120 TWLWH WR pulse Width 340 270 210 180 120 TLLAX Address Hold After ALE 85 85 70 55 35 TRLDV RD to Valid in 240 210 175 135 110 TRHDX Data hold after RD 0 0 0 0 0 TRHDZ Data float after RD 90 90 80 70 50 TLLDV ALE to Valid Data In 435 370 350 235 170 TA VDV Address to Valid Data IN 480 400 300 260 190 TLLWL ALE to WR or RD 150 250 135 170 120 130 90 115 70 100 TA VWL Address to WR or RD 180 180 140 115 75 TQVWX Data valid to WR transition 35 35 30 20 15 TQVWH Data Setup to WR transition 380 325 250 215 170 TWHQX Data Hold after WR 40 35 30 20 15 TRLAZ RD low to Address Float 0 0 0 0 0 TWHLH RD or WR high to ALE high 35 90 35 60 25 45 20 40 20 40 External Data Memory Write Cycle TAVWL TQVWX External Data Memory Read Cycle

Rev.F (14 Jan. 97) 21MA TRA MHS Serial Port Timing – Shift Register Mode SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX TXLXL Serial Port Clock Cycle Time 750 600 480 400 330 TQVXH Output Data Setup to Clock Rising Edge 563 480 380 300 220 TXHQX Output Data Hold after Clock Rising Edge 63 90 65 50 45 TXHDX Input Data Hold after Clock Rising Edge 0 0 0 0 0 TXHDV Clock Rising Edge to Input Data Valid 563 450 350 300 250 Shift Register Timing Waveforms

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External Clock Drive Characteristics (XTAL1) SYMBOL PARAMETER MIN MAX UNIT FCLCL Oscillator Frequency 36 MHz TCLCL Oscillator period 27.8 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. Iol/IoH ≥ ± 20 mA.

Rev.F (14 Jan. 97) 23MA TRA MHS Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.

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Ordering Information

blank : Commercial I : Industrial A : Automotive M : Military Part Number 83C154 Rom 16 K × 8 80C154 External ROM 83C154C Secret ROM version 83C154T Secret Tag version Customer Rom Code I /C0120/C0120/C0120/C008383C154C –12 : 12 MHz version –16 : 16 MHz version –20 : 20 MHz version –25 : 25 MHz version –30 : 30 MHz version –36 : 36 MHz version –L16 : Low Power (Vcc : 2.7-5.5 V Freq : 0-16 MHz) R : Tape and Reel D : Dry Pack /C0045/C0051/C0054 /C0068 Package Type P: PDIL 40 S: PLCC 44 F1: PQFP 44 (Foot print 13.9 mm) F2: PQFP 44 (Foot print 12.3 mm) V: VQFP (1.4 mm) T: TQFP (1.0 mm) D: CDIL 40 Q: CQFP 44 R: LCC 44 Flow /883: MIL 883 Compliant P883: MIL 883 Compliant with PIND test.