MF0UL1101DUD

NXP Semiconductors

MIFARE Ultralight EV1 - contactless ticket IC Rev. 3.0-19 February 2013

Manufacturer: NXP Semiconductors

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Technical content

General description NXP Semiconductors developed the MIFARE Ultralight EV1 MF0ULx1 for use in a contactless smart ticket, smart card or token in combination with a Proximity Coupling Device (PCD). The MF0ULx1 is designed to work in an ISO/IEC 14443 Type A compliant environment (see Ref. 1 ). The target applications include single trip or limited use tickets in public transportation networks, loyalty cards or day passes for events. The MF0ULx1 serves as a replacement for conventional ticketing solutions such as paper tickets, magnetic stripe tickets or coins. It is also a perfect ticketing counterpart to contactless card families such as MIFARE DESFire or MIFARE Plus. The MIFARE Ultralight EV1 is succeeding the MIFARE Ultralight ticketing IC and is fully functional backwards compatible. Its enhanced feature and command set enable more efficient implementations and offer more flexibility in system designs. The mechanical and electrical specifications of MIFARE Ultralight EV1 are tailored to meet the requirements of inlay and paper ticket manufacturers.

1.1 Contactless energy and data transfer

In a MIFARE system, the MF0ULx1 is connected to a coil with a few turns. The MF0ULx1 fits the TFC.0 (Edmondson) and TFC.1 (ISO) ticket formats as defined in Ref. 8. The MF0ULx1 chip, which features a 17 pF on-chip resonance capacitor, supports both TFC.1 and TFC.0 ticket formats.

1.2 Anticollision

An intelligent anticollision function allows more than one card to operate in the field simultaneously. The anticollision algorithm selects each card individually. It ensures that the execution of a transaction with a selected card is performed correctly without interference from another card in the field. MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC Rev. 3.0 — 19 February 2013 234530 Product data sheet COMPANY PUBLIC Fig 1. Contactless system aaa-006271 energy data ISO/IEC 14443 A PCD

1.3 Simple integration and user convenience

complete ticketing transactions to be handled in less than 35 ms.

1.4 Security

Manufacturer programmed 7-byte UID for each device
32-bit user definable One-Time Programmable (OTP) area
3 independent 24-bit true one-way counters
Field programmable read-only locking function per page (per 2 pages for the extended memory section)
ECC based originality signature
32-bit password protection to prevent unintended memory operations

1.5 Naming conventions

Table 1. Naming conventions

0 Ultralight product family

2.1 EEPROM

Table 2. Quick reference data

Table 3. Ordering information

7.1 Pinning

The pinning for the MF0ULx1DAx is shown Figure 3 for a contactless MOA8 module. Table 4. Pin allocation table

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8.1 Block description

The MF0ULx1 chip consists of a 640-bit or a 1312-bit EEPROM, RF interface and Digital Control Unit (DCU). Energy and data are transferred via an antenna consisting of a coil with a few turns which is directly connected to the MF0ULx1. No further external components are necessary. Refer to Ref. 2 for details on antenna design.

RF interface: – modulator/demodulator – rectifier – clock regenerator – Power-On Reset (POR) – voltage regulator
Anticollision: multiple cards may be selected and managed in sequence
Command interpreter: processes memory access commands that the MF0ICU1 supports
EEPROM interface
EEPROM: 640 bit, organized in 20 pages of 4 byte per page. – 208 bit reserved for manufacturer and configuration data – 16 bit used for the read-only locking mechanism – 32 bit available as OTP area – 384 bit user programmable read/write memory
EEPROM: 1312 bit, organized in 41 pages of 4 byte per page. – 208 bit reserved for manufacturer and configuration data – 31 bit used for the read-only locking mechanism – 32 bit available as OTP area – 1024 bit user programmable read/write memory

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8.2 RF interface

The RF-interface is based on the ISO/IEC 14443 Type A standard for contactless smart cards. During operation, the reader generates an RF field. This RF field must always be present (with short pauses for data communication), as it is used for the power supply of the card. For both directions of data communication, there is one start bit at the beginning of each frame. Each byte is transmitted with an odd parity bit at the end. The LSB of the byte with the lowest address of the selected block is transmitted first. The maximum length of a PCD to PICC frame is 199 bits (20 data bytes + 2 CRC bytes = 209 + 29 + 1 start bit). The maximum length for a fixed size PICC to PCD frame is 307 bits (32 data bytes + 2 CRC bytes = 329 + 29 + 1 start bit). The FAST_READ response has a variable frame length depending on the start and end address parameters. When issuing this command, take into account the maximum frame length that the PCD supports. For a multi-byte parameter, the least significant byte is always transmitted first. As an example, take reading from the memory using the READ command. Byte 0 from the addressed block is transmitted first after which, byte 1 to byte 3 are transmitted. The same sequence continues for the next block and all subsequent blocks.

8.3 Data integrity

Following mechanisms are implemented in the contactless communication link between reader and card to ensure very reliable data transmission:

16 bits CRC per block
parity bits for each byte
bit count checking
bit coding to distinguish between “1”, “0” and “no information”
channel monitoring (protocol sequence and bit stream analysis)

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8.4 Communication principle

The reader initiates the commands and the Digital Control Unit of the MF0ULx1 controls them. The command response is depending on the state of the IC and for memory operations also on the access conditions valid for the corresponding page. Remark: In all states, the command interpreter returns to the idle state on receipt of an unexpected command. If the IC was previously in the HALT state, it returns to that state Remark: The VCSL command is only allowed in the ACTIVE state Fig 4. State diagram aaa-006274 VCSL READ (16 Byte) FAST_READ WRITE , COMPATIBILITY _WRITE (4 Byte) INCR _CNT READ_CNT CHK_TEARING _EVENT GET_VERSION READ_SIG PWD_AUTH SELECT cascade level 2 SELECT cascade level 1 WUPA REQA WUPA READY 1 READY 2 ACTIVE AUTHENTICATED IDLEHALT POR ANTICOLLISION ANTICOLLISION READ from page 0 READ from page 0 HLTA HLTA identification and selection procedure memory operations

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8.4.1 IDLE state

After a power-on reset (POR), the MF0ULx1 switches to the IDLE state. It only exits this state when a REQA or a WUPA command is received from the PCD. Any other data received while in this state is interpreted as an error and the MF0ULx1 remains in the IDLE state. Refer to Ref. 4 for implementation hints for a card polling algorithm that respects relevant timing specifications from ISO/IEC 14443 Type A. After a correctly executed HLTA command, for example out of the ACTIVE or AUTHENTICATED state, the default waiting state changes from IDLE to HALT. This state can then be exited with a WUPA command only.

8.4.2 READY1 state

In this state, the PCD resolves the first part of the UID (3 bytes) using the ANTICOLLISION or SELECT commands in cascade level 1. This state is exited correctly after execution of either of the following commands:

SELECT command from cascade level 1: the PCD switches the MF0ULx1 into READY2 state where the second part of the UID is resolved.
READ command (from address 0): all anticollision mechanisms are bypassed and the MF0ULx1 switches directly to the ACTIVE state. Remark: If more than one MF0ULx1 is in the PCD field, a READ command from address 0 selects all MF0ULx1 devices. In this case, a collision occurs due to the different serial numbers. Any other data received in the READY1 state is interpreted as an error. Depending on its previous state, the MF0ULx1 returns to either the IDLE state or HALT state.

8.4.3 READY2 state

In this state, the MF0ULx1 supports the PCD in resolving the second part of its UID (4 bytes) with the cascade level 2 ANTICOLLISION command. This state is usually exited using the cascade level 2 SELECT command. Alternatively, READY2 state can be skipped using a READ command (from address 0) as described for the READY1 state. Remark: The response of the MF0ULx1 to the cascade level 2 SELECT command is the select acknowledge (SAK) byte. In accordance with ISO/IEC 14443, this byte indicates if the anticollision cascade procedure has finished. It also defines the type of device selected for the MIFARE architecture platform. The MF0ULx1 is now uniquely selected and only this device communicates with the PCD even when other contactless devices are present in the PCD field. If more than one MF0ULx1 is in the PCD field, a READ command from address 0 selects all MF0ULx1 devices. In this case, a collision occurs due to the different serial numbers. Any other data received when the device is in this state is interpreted as an error. Depending on its previous state the MF0ULx1 returns to either the IDLE state or HALT state.

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8.4.4 ACTIVE state

All memory operations and other functions like the originality signature read-out are operated in the ACTIVE state. The ACTIVE state is gratefully exited with the HLTA command and upon reception the MF0ULx1 transits to the HALT state. Any other data received when the device is in this state is interpreted as an error. Depending on its previous state the MF0ULx1 returns to either the IDLE state or HALT state. The MF0ULx1 transits to the AUTHENTICATED state after successful password verification using the PWD_AUTH command.

8.4.5 AUTHENTICATED state

In this state, all operations on memory pages, which are configured as password verification protected, can be accessed. The AUTHENTICATED state is gratefully exited with the HLTA command and upon reception the MF0ULx1 transits to the HALT state. Any other data received when the device is in this state is interpreted as an error. Depending on its previous state the MF0ULx1 returns to either the IDLE state or HALT state.

8.4.6 HALT state

The HALT and IDLE states constitute the two wait states implemented in the MF0ULx1. An already processed MF0ULx1 can be set into the HALT state using the HLTA command. In the anticollision phase, this state helps the PCD to distinguish between processed cards and cards yet to be selected. The MF0ULx1 can only exit this state on execution of the WUPA command. Any other data received when the device is in this state is interpreted as an error and the MF0ULx1 state remains unchanged. Refer to Ref. 4 for correct implementation of an anticollision procedure based on the IDLE and HALT states and the REQA and WUPA commands.

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8.5 Memory organization

The EEPROM memory is organized in pages with 4 bytes per page. The MF0UL11 variant has 20d pages and the MF0UL21 variant has 41d pages in total. The memory organization can be seen in Figure 5 and Figure 6, the functionality of the different memory sections is described in the following sections. (1) counter pages are only accessible with READ_CNT and INCR_CNT commands Fig 5. Memory organization MF0UL11 (1) counter pages are only accessible with READ_CNT and INCR_CNT commands Fig 6. Memory organization MF0UL21 aaa-006275 Byte number within a page 0 31 2 serial number internal lock bytes OTP OTP OTP OTP PACK serial number serial number user memory CFG0 CFG1 PWD RFUI Hex 10h 11h 12h 13h

Description

... One-Way counters1) Counter pages Dec ... Page Adr aaa-006276 28h ... 24h 25h 26h 27h 23h 22h ... Byte number within a page 0 31 2 serial number internal lock bytes OTP OTP OTP OTP PACK serial number serial number user memory CFG0 CFG1 PWD RFUI one-way counters1) Counter pages lock bytes Lock bytesRFUI HexDec Page Adr

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8.5.1 UID/serial number

The unique 7-byte serial number (UID) and its two check bytes are programmed into the first 9 bytes of memory covering page addresses 00h, 01h and the first byte of page 02h. The second byte of page address 02h is reserved for internal data. These bytes are programmed and write protected in the production test. In accordance with ISO/IEC 14443-3 check byte 0 (BCC0) is defined as CT  SN0  SN1  SN2. Check byte 1 (BCC1) is defined as SN3  SN4  SN5  SN6. SN0 holds the Manufacturer ID for NXP Semiconductors (04h) in accordance with ISO/IEC 14443-3 and ISO/IEC 7816-6 AMD.1

8.5.2 Lock byte 0 and byte 1

The bits of byte 2 and byte 3 of page 02h represent the field programmable read-only locking mechanism. Each page from 03h (OTP) to 0Fh can be individually locked by setting the corresponding locking bit Lx to logic 1 to prevent further write access. After locking, the corresponding page becomes read-only memory. The three least significant bits of lock byte 0 are the block-locking bits. Bit 2 deals with pages 0Ah to 0Fh, bit 1 deals with pages 04h to 09h and bit 0 deals with page 03h (OTP). Once the block-locking bits are set, the locking configuration for the corresponding memory area is frozen. For example if BL15-10 is set to logic 1, then bits L15 to L10 (lock byte 1, bit[7:2]) can no longer be changed. A WRITE command or COMPATIBILITY_WRITE command to page 02h, sets the locking and block-locking bits. Byte 2 and byte 3 of the WRITE or Fig 7. UID/serial number 001aai001 MSB LSB page 0 byte check byte 0 serial number part 1 serial number part 2 manufacturer ID for NXP Semiconductors (04h)00000100 0123 page 1 0123 page 2 0123 internal check byte 1 lock bytes Fig 8. Lock bytes 0 and 1 aaa-006277 L L L L L OTP BL 15-10 BL 9-4 BL OTP MSB page 2 Lx locks page x to read-only BLx blocks further locking for the memory area x lock byte 0 lock byte 1 123 LSB L L L L L L L L MSB LSB

Rev. 3.0 — 19 February 2013 234530 13 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC COMPATIBILITY_WRITE command, and the contents of the lock bytes are bit-wise OR’ed and the result then becomes the new content of the lock bytes. This process is irreversible. If a bit is set to logic 1, it cannot be changed back to logic 0. The contents of bytes 0 and 1 of page 02h are unaffected by the corresponding data bytes of the WRITE or COMPATIBILITY_WRITE command. The default value of the static lock bytes is 00 00h. Any write operation to the lock bytes, features anti-tearing support.

8.5.3 Lock byte 2 to byte 4

To lock the pages of the MF0UL21 starting at page address 10h onwards, the lock bytes 2-4 located in page 24h are used. Those three lock bytes cover the memory area of 80 data bytes. The granularity is 2 pages, compared to a single page for the first 512 bits as shown in Figure 9. Remark: Set all bits marked with RFUI to 0, when writing to the lock bytes. The default value of lock bytes 2-4 is 00 00 00h. The value of byte 3 on page 36 (see Figure 9 ) is always BDh when read. Any write operation to the lock bytes, features anti-tearing support. Fig 9. Lock bytes 2-4 aaa-006278 0 1 2 3page lock byte 2 lock byte 3 36 (24h) LO CK P AGE 30-31 LO CK P AGE 28-29 LO CK P AGE 26-27 LO CK P AGE 24-25 LO CK P AGE 22-23 LO CK P AGE 20-21 LO CK P AGE 18-19 LO CK P AGE 16-17 RFUI RFUI RFUI RFUI RFUI RFUI LO CK P AGE 34-35 LO CK P AGE 32-33 RF UI RF UI RF UI BL 32- 35 BL 28- 31 BL 24- 27 BL 20- 23 BL 16- 19 MSB LSB bit 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 lock byte 4

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8.5.4 OTP bytes

Page 03h is the OTP page and it is preset so that all bits are set to logic 0 after production. These bytes can be bit-wise modified using the WRITE or COMPATIBILITY_WRITE command. The parameter bytes of the WRITE command and the current contents of the OTP bytes are bit-wise OR’ed. The result is the new OTP byte contents. This process is irreversible and once a bit is set to logic 1, it cannot be changed back to logic 0. The default value of the OTP bytes is 00 00 00 00h. Any write operation to the OTP bytes features anti-tearing support.

8.5.5 Data pages

Pages 04h to 0Fh for the MF0UL11 and 04h to 23h for the MF0UL21 are the user memory read/write area. The access to a part of the user memory area can be restricted using a password verification. See Section 8.6 for further details. Remark: The default content of the data blocks at delivery is not defined. This memory area can be used as a 32 tick one-time counter. Fig 10. OTP bytes 001aak571 byte 12 13 14 15 page 3 example OTP bytes OTP bytes default value 00000000 00000000 00000000 00000000 1st write command to page 3 11111111 11111100 00000101 00000111 result in page 3 11111111 11111100 00000101 00000111 2nd write command to page 3 11111111 00000000 00111001 10000000 result in page 3 11111111 11111100 00111101 10000111

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8.5.6 Configuration pages

Pages 10h-13h for the MF0UL11 and pages 25h-28h for the MF0UL21 variant, are used to configure the memory access restriction of the MF0ULx1. They are also used to configure the response to a VCSL command. The memory content of the configuration pages is detailed in Table 5, Table 6 and Table 7. [1] page address for MF0UL11/MF0UL21 Table 5. Configuration Pages Table 6. ACCESS configuration byte Table 7. Configuration parameter descriptions AUTH0 defines the page address from which the password verification is required. Valid address range for byte AUTH0 is 00h to FFh. If AUTH0 is set to a page address which is higher than the last user configuration page, the password protection is effectively disabled. PROT 1 0b One bit inside the ACCESS byte defining the memory protection 0b ... write access is protected by the password verification 1b ... read and write access is protected by the password verification CFGLCK 1 0b Write locking bit for the user configuration 0b ... user configuration open to write access 1b ... user configuration permanently locked against write access AUTHLIM 3 000b Limitation of negative password verification attempts 000b... limiting of negative password verification attempts disabled 001b-111b ... maximum number of negative password verification attempts VCTID 8 05h Virtual Card Type Identifier which represents the response to a VCSL command. To ensure infrastructure compatibility, do not change the default value of 05h. PWD 32 FFFF FFFFh 32-bit password used for memory access protection PACK 16 0000h 16-bit password acknowledge used during password verification RFUI - all 0b Reserved for future use - implemented. Write all bits and bytes denoted as RFUI as 0b.

Rev. 3.0 — 19 February 2013 234530 16 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC Remark: The CFGLCK bit activates the permanent write protection of the first two configuration pages. The write lock is only activated after a power cycle of the MF0ULx1. If write protection is enabled, each write attempt leads to a NAK response.

8.6 Password verific ation protection

The memory write or read/write access to a configurable part of the memory can be constrained to a positive password verification. The 32-bit secret password (PWD) and the 16-bit password acknowledge (PACK) are typically programmed into the configuration pages at ticket issuing or personalization. The use of a chip individual password acknowledge response raises the trust level on the PCD side into the PICC. The AUTHLIM parameter specified in Section 8.5.6 can be used to limit the negative verification attempts. In the initial state of the MF0ULx1, an AUTH0 value of FFh disables password protection. PWD and PACK are freely writable in this state. Access to the configuration pages and any part of the user memory, can be restricted by setting AUTH0 a page address within the available memory space. The page address is the first one protected. Remark: Note that the password verification method available in then MF0ULx1 does not offer a high security protection. It is an easy and convenient way to prevent unauthorized memory access. If a higher level of protection is required, cryptographic methods on application layer can be used to increase overall system security.

8.6.1 Programming of PWD and PACK

Program the 32-bit PWD and the 16-bit PACK into the configuration pages, see Section 8.5.6 . The password as well as the password acknowledge, are written LSByte first. This byte order is the same as the byte order used during the PWD_AUTH command and its response. The PWD and PACK bytes can never be read out of the memory. Instead of transmitting the real value on any valid READ or FAST_READ command, only 00h bytes are replied. If the password verification does not protect the configuration pages, PWD and PACK can be written with normal WRITE and COMPATIBILITY_WRITE commands. If the password verification protects the configuration pages, PWD and PACK can be written after a successful PWD_AUTH command. The PWD and PACK are writable even if the CFGLCK bit is set to 1b. Therefore it is strongly recommended to set AUTH0 to the page where the PWD is located after the password has been written. This page is 12h for the MF0UL11 and 27h for the MF0UL21. Remark: To improve the overall system security, it is strongly recommended to diversify the password and the password acknowledge using a die individual parameter, that is, the 7-byte UID available on the MF0ULx1.

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8.6.2 Limiting negative verification attempts

To prevent brute-force attacks on the password, the maximum allowed number of negative password verification attempts can be set using AUTHLIM. This mechanism is disabled by setting AUTHLIM to a value of 000b which is also the initial state of the MF0ULx1. If AUTHLIM is not equal to 000b, each negative authentication verification is internally counted. The count operation features anti-tearing support. As soon as this internal counter reaches the number specified in AUTHLIM, any further negative password verification leads to a permanent locking of the protected part of the memory for the specified access modes. Specifically, whether the provided password is correct or not, each subsequent PWD_AUTH fails. Any successful password verification, before reaching the limit of negative password verification attempts, resets the internal counter to zero.

8.6.3 Protection of special memory segments

The configuration pages can be protected by the password authentication as well. The protection level is defined with the PROT bit. The protection is enabled by setting the AUTH0 byte to a value that is within the addressable memory space. All counters can always be incremented and read without prior password verification.

8.7 Counter functionality

The MF0ULx1 features three independent 24-bit one-way counters. These counters are located in a separate part of the NVM which is not directly addressable using READ, FAST_READ, WRITE or COMPATIBILITY_WRITE commands. The actual value can be retrieved by using the READ_CNT command, the counters can be incremented with the INCR_CNT command. The INCR_CNT command features anti-tearing support, thus no undefined values originating from interrupted programing cycles are possible. Either the value is unchanged or the correct, incremented value is correctly programmed into the counter. The occurrence of a tearing event can be checked using the CHECK_TEARING_EVENT command. In the initial state, the counter values are set to 000000h. The counters can be incremented by an arbitrary value. The incremented value is valid immediately and does not require a RF reset or re-activation. Once counter value reaches FFFFFFh and an increment is performed via a valid INCR_CNT command, the MF0ULx1 replies a NAK. If the sum of the addressed counter value and the increment value in the INCR_CNT command is higher than FFFFFFh, the MF0ULx1 replies a NAK and does not update the respective counter. An increment by zero (000000h) is always possible, but does not have any impact on the counter value.

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8.8 Originality function

The MF0ULx1 features a cryptographically supported originality check. With this feature, it is possible to verify with a certain probability, that the ticket is using an NXP Semiconductors manufactured silicon. This check can also be performed on personalized tickets. Each MF0ULx1 holds a 32-byte cryptographic signature based on elliptic curve cryptography. This signature can be retrieved using the READ_SIG command and can be verified using the corresponding ECC public key in the PCD.

8.9 Virtual Card Architecture Support

The MF0ULx1 supports the virtual card architecture by replying to a Virtual Card Select Last (VCSL) command with a virtual card type identifier. The VCTID that is replied can be programmed in the configuration pages. It enables infrastructure supporting this feature to process MIFARE cards across different MIFARE families in a common way. For example, a contactless system is enabled to select a specific virtual MIFARE card inside a mobile phone. It can use the same card identification principle to detect that the MF0ULx1 belongs to the system.

ISO/IEC 14443 HLTA command, or the MIFARE Ultralight commands can be performed. For more details about the card activation, refer to Ref. 1.

9.1 MIFARE Ultralight EV1 command overview

All available commands for the MIFARE Ultralight are shown in Table 8. [1] Unless otherwise specified, all commands use the coding and framing as described in Ref. 1. Table 8. Command overview

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9.2 Timing

The command and response timings shown in this document are not to scale and values are rounded to 1 s. All given command and response transmission times refer to the data frames including start of communication and end of communication. They do not include the encoding (such as Miller pulses). A PCD data frame, contains the start of communication (1 “start bit”) and the end of communication (one logic 0 + 1 bit length of unmodulated carrier). A PICC data frame, contains the start of communication (1 “start bit”) and the end of communication (1 bit length of no subcarrier). The minimum command response time is specified according to Ref. 1 as an integer n which specifies the PCD to PICC frame delay time. The frame delay time from PICC to PCD is at least 87 s. The maximum command response time is specified as a time-out value. Depending on the command, the TACK value specified for command responses defines the PCD to PICC frame delay time. It does it for either the 4-bit ACK value specified in Section 9.3 or for a data frame. All command timings are according to ISO/IEC 14443-3 frame specification as shown for the Frame Delay Time in Figure 11. For more details, refer to Ref. 1. Remark: Due to the coding of commands, the measured timings usually excludes (a part of) the end of communication. Consider this factor when comparing the specified times with the measured times. Fig 11. Frame Delay Time (from PCD to PICC), T ACK and TNAK aaa-006279 last data bit transmitted by the PCD FDT = (n* 128 + 84)/fc first modulation of the PICC FDT = (n* 128 + 20)/fc 128/fc logic „1“ 128/fc logic „0“ 256/fc end of communication (E) 256/fc end of communication (E) 128/fc start of communication (S) 128/fc start of communication (S)

9.3 MIFARE Ultralight ACK and NAK

The MIFARE Ultralight uses a 4-bit ACK / NAK as shown in Table 9.

9.4 ATQA and SAK responses

For details on the type identification procedure, refer to Ref. 3. Table 10. It replies to a Select CL2 command with the SAK value shown in Table 11. The 2-byte ATQA value is transmitted with the least significant byte first (44h). ISO/IEC 14443 independent from the settings of the UID usage. LSB = bit 0. So 1 byte counts bit 1 to bit 8 instead of bit 0 to 7. Table 9. ACK and NAK values Table 10. ATQA response of the MF0ULx1 Table 11. SAK response of the MF0ULx1

MIFARE Ultralight EV1 commands

10.1 GET_VERSION

product version, storage size and other product data required to identify the MF0ULx1. identifying products across platforms and evolution steps. Table 13 shows the required timing. Table 12. GET_VERSION command Table 13. GET_VERSION timing These times exclude the end of communication of the PCD.

user memory size is between 2n and 2n+1. 5d and the least significant bit is 1b. The user memory for the MF0UL21 is 128 bytes. This memory size is exactly 128d. Table 14. GET_VERSION response for MF0UL11 and MF0UL21

10.2 READ

Table 13 shows the required timing. Table 15. READ command Table 16. READ timing These times exclude the end of communication of the PCD.

Rev. 3.0 — 19 February 2013 234530 25 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC In the initial state of the MF0ULx1, all memory pages are allowed as Addr parameter to the READ command.

page address 00h to 13h for the MF0UL11
page address 00h to 28h for the MF0UL21 Addressing a memory page beyond the limits above results in a NAK response from the MF0ULx1. A roll-over mechanism is implemented to continue reading from page 00h once the end of the accessible memory is reached. Reading from address 11h on a MF0UL11 results in pages 11h, 12h, 13h and 00h being returned. The following conditions apply if part of the memory is password protected for read access:
if the MF0ULx1 is in the ACTIVE state – addressing a page which is equal or higher than AUTH0 results in a NAK response – addressing a page lower than AUTH0 results in data being returned with the roll-over mechanism occurring just before the AUTH0 defined page
if the MF0ULx1 is in the AUTHENTICATED state – the READ command behaves like on a MF0ULx1 without access protection Remark: PWD and PACK values can never be read out of the memory. When reading from the pages holding those two values, all 00h bytes are replied to the PCD instead.

10.3 FAST_READ

Table 18 shows the required timing.

page address 00h to 13h for the MF0UL11
page address 00h to 28h for the MF0UL21 Addressing a memory page beyond the limits above results in a NAK response from the MF0ULx1. The EndAddr parameter must be equal to or higher than the StartAddr. The following conditions apply if part of the memory is password protected for read access: Fig 14. FAST_READ command

Table 17. FAST_READ command Table 18. FAST_READ timing These times exclude the end of communication of the PCD.

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if the MF0ULx1 is in the ACTIVE state – if any requested page address is equal or higher than AUTH0 a NAK is replied
if the MF0ULx1 is in the AUTHENTICATED state – the FAST_READ command behaves like on a MF0ULx1 without access protection Remark: PWD and PACK values can never be read out of the memory. When reading from the pages holding those two values, all 00h bytes are replied to the PCD instead. Remark: The FAST_READ command is able to read out the whole memory with one command. Nevertheless, receive buffer of the PCD must be able to handle the requested amount of data as there is no chaining possibility.

10.4 WRITE

Table 20 shows the required timing.

page address 02h to 13h for the MF0UL11
page address 02h to 28h for the MF0UL21 Addressing a memory page beyond the limits above results in a NAK response from the MF0ULx1. Pages which are locked against writing cannot be reprogrammed using any write command. The locking mechanisms include lock bits as well as the locking of the configuration pages. The following conditions apply if part of the memory is password protected for write access: Fig 15. WRITE command

Table 19. WRITE command Table 20. WRITE timing These times exclude the end of communication of the PCD.

Rev. 3.0 — 19 February 2013 234530 29 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC

if the MF0ULx1 is in the ACTIVE state – writing to a page which address is equal or higher than AUTH0 results in a NAK response
if the MF0ULx1 is in the AUTHENTICATED state – the WRITE command behaves like on a MF0ULx1 without access protection The MF0ULx1 features tearing protected write operations to specific memory content. The following pages are protected against tearing events during a WRITE operation:
page 2 containing lock bits
page 3 containing OTP bits
page 36 containing the additional lock bits for the MF0UL21

10.5 COMPATIBILITY_WRITE

Table 22 shows the required timing. Table 21. COMPATIBILITY_WRITE command

to the COMPATIBILITY_WRITE command.

page address 02h to 13h for the MF0UL11
page address 02h to 28h for the MF0UL21 Addressing a memory page beyond the limits above results in a NAK response from the MF0ULx1. Pages which are locked against writing cannot be reprogrammed using any write command. The locking mechanisms include lock bits as well as the locking of the configuration pages. The following conditions apply if part of the memory is password protected for write access:
if the MF0ULx1 is in the ACTIVE state – writing to a page which address is equal or higher than AUTH0 results in a NAK response
if the MF0ULx1 is in the AUTHENTICATED state – the COMPATIBILITY_WRITE command behaves the same as on a MF0ULx1 without access protection The MF0ULx1 features tearing protected write operations to specific memory content. The following pages are protected against tearing events during a COMPATIBILITY_WRITE operation:
page 2 containing lock bits
page 3 containing OTP bits
page 36 containing the additional lock bits for the MF0UL21

Table 22. COMPATIBILITY_WRITE timing These times exclude the end of communication of the PCD.

10.6 READ_CNT

Table 24 shows the required timing. Table 23. READ_CNT command Table 24. READ_CNT timing These times exclude the end of communication of the PCD.

10.7 INCR_CNT

INCR_CNT command is shown in Figure 19 and Table 25. Table 26 shows the required timing. significant byte is ignored. Table 25. INCR_CNT command Table 26. INCR_CNT timing These times exclude the end of communication of the PCD.

Rev. 3.0 — 19 February 2013 234530 34 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC The order of bytes in the increment argument follows the same order that the bytes are sent via the communication interface. This means from the LSbyte (IncrValue0) to MSbyte (IncValue3), where the last valid byte is actually IncrValue2. It is in line with the arguments consisting of multiple bytes for other commands. As an example, an increment of the counter 00h by 01h, is formulated as INCR CNT 00 01 00 00 00. The INCR_CNT command features anti-tearing support.

10.8 PWD_AUTH

Table 20 shows the required timing. ticket issuing and set the AUTH0 value to the PWD page. Table 27. PWD_AUTH command Table 28. PWD_AUTH timing These times exclude the end of communication of the PCD.

10.9 READ_SIG

Table 30 shows the required timing. Ref. 7 describes the signature verification procedure. Table 29. READ_SIG command Table 30. READ_SIG timing These times exclude the end of communication of the PCD.

10.10 CHECK_TEARING_EVENT

Table 13 shows the required timing. The application can use this information to base business logic decisions on. Table 31. CHECK_TEARI NG_EVENT command Table 32. CHECK_TEARI NG_EVENT timing These times exclude the end of communication of the PCD.

10.11 VCSL

information, the reader can decide whether the ticket belongs to the installation or not. The command structure is shown in Figure 23 and Table 33. Table 34 shows the required timing. Table 33. VCSL command Table 34. VCSL timing These times exclude the end of communication of the PCD.

the device. Exposure to limiting values for extended periods can affect device reliability. Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 36. Characteristics

13.1 Fail die identification

mechanical/visual inspection. No ink dots are applied. Table 37. Wafer specifications MF0ULx1

Rev. 3.0 — 19 February 2013 234530 41 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC 14. Package outline For more details on the contactless MOA8 module, refer to Ref. 5. Fig 24. Package outline SOT500-4 ReferencesOutline version European projection Issue date IEC JEDEC JEITA sot500-4_po 11-02-18 Unit mm max nom min 0.26 35.05 35.00 34.95 A (1) Dimensions Note 1. Total package thickness, exclusive punching burr. PLLMC: plastic leadless module carrier package; 35 mm wide tape SOT500-4 D For unspecified dimensions see PLLMC-drawing given in the subpackage code. 0 10 20 mm scale X D detail X A

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14.1 Bare die outline

For more details on the wafer delivery forms, see Ref. 6. Fig 25. Bare die outline MF0ULx1 aaa-006293 typ. 505,0 (1) typ. 59 0,0 (1) 43,0 423,0 508,0 typ. 20,0 (1) min. 5,0 typ. 20,0 (1) min. 5.0 Bump size x [µm] y [µm] LA, LB, GND, TP 60 60 Chip Step 505(1) 590(1) MF0ULx1 LBGND LA TP (1) the air gap and thus the step size may vary due to varying foil expansion (2) all dimensions in µm, pad locations measured from metal ring edge (see detail) X Y 43,0

Table 38. Abbreviations and symbols

Rev. 3.0 — 19 February 2013 234530 44 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC 16. References [1] ISO/IEC 14443 — International Organization for Standardization [2] MIFARE (Card) Coil Design Guide — Application note, BU-ID Document number 01171 [3] MIFARE Type Identification Procedure — Application note, BU-ID Document number 01841 [4] MIFARE ISO/IEC 14443 PICC Selection — Application note, BU-ID Document number 13081 [5] Contactless smart card module specification MOA8 — Delivery Type Description, BU-ID Document number 16361 [6] General specification for 8" wafer on UV-tape; delivery types — Delivery Type Description, BU-ID Document number 10051 [7] AN073121 MIFARE Ultralight Features and Hints — Application note, BU-ID Document number 0731 [8] ISO/IEC 15457-1 Identification cards — Thin flexible cards 1. ** ... document version number

Table 39. Revision history

Security status changed into “COMPANY PUBLIC”
Added default values for configuration elements in Table 7
Corrected response timing in Figure 18
Corrected PCDCAPS length in Table 33
Changed EEPROM reliability parameters for counters 234521 20120928 Preliminary data sheet - 234520 Modifications:
Editorial changes
Changed EEPROM reliability parameters 234520 20120525 Objective data sheet - -
Initial version

Rev. 3.0 — 19 February 2013 234530 46 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC 18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

Rev. 3.0 — 19 February 2013 234530 47 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE Ultralight — is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Table 14. GET_VERSION response for MF0UL11 and

Rev. 3.0 — 19 February 2013 234530 49 of 50 NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC 21. Figures Fig 11. Frame Delay Time (from PCD to PICC), T

NXP Semiconductors MF0ULx1 MIFARE Ultralight EV1 - contactless ticket IC © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 February 2013 234530 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents 9.1 MIFARE Ultralight EV1 command overview . . 19

Product Information

MF0UL1101DUD specifications and overview.

Summary

MIFARE Ultralight EV1 - contactless ticket IC Rev. 3.0-19 February 2013

Description

MIFARE Ultralight EV1 - contactless ticket IC Rev. 3.0-19 February 2013

Source title MF0UL1101DUD Datasheet(PDF) - NXP Semiconductors

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