MCDP6000 KINETIC | Alldatasheet
Document overview
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Technical content
June 2021 – Revision 03g Page 1 of 5 Company Confidential MCDP6000 USB Type-C DP Alt-Mode Switching Retimer Kinetic Technologies cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Kinetic Technologies product. No intellectual property or circuit patent licenses are implied. Kinetic Technologies reserves the right to change the circuitry and specifications without notice at any time . Datasheet Brief
June 2021 – Revision 03g Page 2 of 5 Company Confidential Datasheet Brief MCDP6000
Features
- Integrated USB Type-C DisplayPort alternate mode lane switch to support − Flip-ability of USB Type-C − Simultaneous USB 3.2 x1 Enhanced SuperSpeed (ESS) and 2 lane DP1.4a − 4/2/1-Lane DP1.4a(RBR/HBR/HBR2/HBR3)
- Power Supply Voltages − 1.8 V for I/O, 1.2 V for core
- USB3.2 Appendix.E x1 Compliant Retimer − 5 Gbps and 10 Gbps support − Link training participation − Spread-spectrum clocking as per USB 3.2 standard − LFPS polling and processing − LFPS Based PWM support − Pass-Through / Local loopback − Loopback BERT for USB 3.2 SS − Lane polarity inversion − BLR (Bit-Level Retimer) for SS mode o Low latency data path o Link layer snooping ▪ Link power management support − SRIS (Separate Reference clock Independent SSC) for SSP mode o 128b/132b coding o Scrambler / De-scrambler o Link power management support o SKP OS handling / Elastic buffer for USB for clock offset compensation o DC balance tracking / control o Error correction − Transmitter Emphasis o 3-tap FIR TXEQ for SSP o 2-tap TXEQ for SS − Adaptive Receiver Equalization o DFE + CTLE for SSP to support -23dB insertion loss compensation @5GHz o CTLE for SS to support -20dB insertion loss compensation @2.5GHz − Support of custom PHY configuration through TWI (Two Wire Interface)
- DP1.4a Compliant Repeater − Data rate 1.62 Gbps / 2.7 Gbps / 5.4 Gbps / 8.1 Gbps − Transparent mode / Non-transparent mode support − AUX_CH transaction snooping − DP1.4a Compliant Retimer DPCD registers − 8b/10b coding − Pattern generator and Error Checker − Down-spreading of link clock − Error detection − Adjustable TXEQ during the link training through AUX_CH − Adaptive equalizer with CTLE and DFE o DFE + CTLE for HBR3 to compensate -27dB insertion loss @4.05GHz o CTLE for HBR2 / HBR / RBR − Support of custom PHY configuration through TWI
- Real time Eye Opening Monitor (EOM)
- TWI slave to configure the integrated lane mapping and operation mode − Compatible with I2C master − Support up to 4 unique TWI device ID
- Configuration pins for the integrated lane switch and operation mode
- Low Power Operation − 520 mW in USB 3.2 x1 SSP + Two lanes of DisplayPort HBR3 operation with 1.2 V and 1.8 V power supply − 850 µW in standby mode
- ESD Specification − 2kV HBM, ±500V CDM
- Package − 46 Ex-VQFN (6.5 mm x 4.5 mm)
Applications
- Desktop PC / Notebook / Tablet / Smartphone motherboard enabling USB Type-C DP alternate mode
Figure 1. MCDP6000 System Block Diagram
Type-C switch targeted for desktop / mobile PC motherboard-down application. Table 1. DP1.4a Repeater Mode
the pin mapping of the USB Type-C DP Alt-mode. The MCDP6000 operates at 1.8 V and 1.2 V.
- 520 mW with an active 4 lane retimer (USB 3.2 x1 SSP TX/RX and DP 2 lanes HBR3)
The MCDP6000 is offered in a 46-pin, 6.5 mm x 4.5 mm Ex-VQFN package. enabling USB Type-C DP alternate mode. the link training is initiated by the DP source through the AUX_CH. Figure 2. MCDP6000 Motherboard-Down Use Case