KTD2151 KINETIC | Alldatasheet

Document overview

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  • PDF pages: 21

Technical content

Features

  • Input voltage range (2.7V to 5.5V)
  • Dual output regulator with single inductor
  • High efficiency above 85%
  • Charge pump with PFM mode at light load
  • Programmable output voltages
  • Positive output voltage range  +4.0V to +6.3V (100mV/step)
  • Negative output voltage range  -4.0V to -6.3V (100mV/step)
  • Programmable regulator offset voltage
  • 1.0% output voltage accuracy
  • Regulated output current up to 80mA
  • Programmable active discharge
  • I2C compatible interface
  • 1 µA shutdown supply current
  • Pb-free WLCSP-15 and TDFN-14 packages
  • RoHS and Green Compliant
  • -40°C to +85°C Temperature Range

Applications

  • Smartphone TFT-LCD
  • Tablet TFT-LCD
  • General Dual Power Supply Applications Brief Description The KTD2151 is a TFT-LCD power supply IC for small and medium size displays for smartphones and tablet s. The positive and negative output rails provide bias supplies for TFT LCD panels via the Source Driver IC. The device only requires a single inductor, to reduce the total PCB area. It features a n integrated step -up DC -DC converter with input voltage range from 2.7V to 5.5V. An LDO and charge pump generate dual regulated outputs, whose voltages can be programmed via an I2C compatible interface. Optimized step-up, LDO and charge pump converters maximize conversion efficiency, exceeding 85%. KTD2151 integrates all compensation and soft -start circuitry, which results in a simpler and smaller solution with much fewer external components . High switching frequency ( 1.8MHz) allows the use of a smaller inductor and capacitor to further reduce the solution size. The I2C compatible interface allows control of the positive and negative outputs from + 4.0V to +6.3V and from -4.0V to -6.3V, respectively, as well as programming additional registers on the device. KTD2151 is available in a RoHS and Green compliant 15- bump 2.2mm x 1.45mm x 0.62mm WLCSP and 14 -lead TDFN 2.5 x 3.0 x 0.75mm. Typical Application ENP ENN SCL SDA CFLY1 CFLY2 AGND PGND OUTP REG OUTN VIN SW Positive Enable Negative Enable I2C Interface Clock I2C Interface Data CFLY 2.2µF CNEG 4.7µF VNEG -5.0V CREG 4.7µF CPOS 4.7µF VPOS +5.0V CIN 4.7µF 4.7µH LVIN 2.7V to 5.5V Programmable Dual Output LCD Bias Power

t KTD2151 April 2020 – Revision 04f Page 2 Company Confidential Pin Descriptions Pin # (WLCSP-15) Pin # (TDFN-14) Name Function

14 ENN Enable input pin for negative output (OUTN)

A2 1 OUTN Charge pump output pin of the negative power A3 2 CFLY2 Negative charge pump flying capacitor pin B1 12 ENP Enable input pin for positive power (OUTP) B2 13 SCL SCL Clock input pin of the I²C interface B3, E1 3, 8 PGND Power GND connection C1 10 VIN Input supply pin for the IC C2 11 SDA SDA bi-direction data pin of the I²C interface C3 4 CFLY1 Negative charge pump flying capacitor pin D1 9 SW Switch node pin of step-up converter D2 5 AGND Analog ground D3, E2 6 REG Step-up converter output pin E3 7 OUTP Positive LDO output pin WLCSP-15 15-Bump 2.2mm x 1.45mm x 0.62mm Top Mark XX = Device Code YY = Date Code, Z = Assembly Code TDFN-14 Top View TOP VIEW TOP VIEW ENN XX YYZ OUTN CFLY2 ENP SCL PGND VIN SDA CFLY1 SW AGND REG PGND REG OUTPE D C B A 1 2 3 ENN SCL ENP SDA VIN SW OUTN CFLY2 PGND CFLY1 AGND REG PGNDOUTP

t KTD2151 April 2020 – Revision 04f Page 3 Company Confidential Absolute Maximum Ratings1 (TA = 25C unless otherwise noted) Symbol Description Value Units VIN Input voltage -0.3 to 6 V SW High voltage switching node DC Voltage -0.3 to 7 V Transient Voltage -0.3 to 7.7 2 V CFLY1 Charge pump pin -0.3 to 7 V OUTP, REG Output voltage pin -0.3 to 7 V OUTN, CFLY2 Output voltage pin and charge pump voltage -7 to 0.3 V ENP, ENN, SCL, SDA Control pins -0.3 to VIN+0.3 V TJ Operating Temperature Range -40 to 150 C Ts Storage Temperature Range -65 to 150 C TLEAD Maximum Soldering Temperature (at pins, 10 sec) 300 C ESD HBM electrical static discharge 2.0 kV 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. 2. Transient voltage rating is with 300ns maximum duration and 50% maximum duty cycle. Thermal Capabilities Symbol Description Value Units θJA Thermal Resistance – Junction to Ambient3 77 C/W PD Maximum Power Dissipation at TA = 25°C 1.3 W ΔPD/ΔT Derating Factor Above TA = 25°C -13 mW/°C 3. Junction to Ambient thermal resistance is highly dependent on PCB layout. Values are based on thermal properties of the device when soldered to an EV board.

Ordering Information

KTD2151EUO-TR GRYYZ +5.0V -5.0V 6µA -40°C to +85°C Level 1 WLCSP-15 KTD2151EUO-CC-TR GZYYZ +5.2V -5.2V 6µA -40°C to +85°C Level 1 WLCSP-15 KTD2151BEUO-TR6 HMYYZ +5.0V -5.0V 100nA -40°C to +85°C Level 1 WLCSP-15 KTD2151BEUO-BB-TR6 HXYYZ +5.1V -5.1V 100nA -40°C to +85°C Level 1 WLCSP-15 KTD2151BEUO-CC-TR6 HOYYZ +5.2V -5.2V 100nA -40°C to +85°C Level 1 WLCSP-15 KTD2151BEUO-FF-TR6 HSYYZ +5.5V -5.5V 100nA -40°C to +85°C Level 1 WLCSP-15 KTD2151BEUO-GG-TR6 MJYYZ +5.6V -5.6V 100nA -40°C to +85°C Level 1 WLCSP-15 KTD2151BEUO-JJ-TR6 MKYYZ +5.8V -5.8V 100nA -40°C to +85°C Level 1 WLCSP-15 KTD2151EXH-TR GRYYZ +5.0V -5.0V 6µA -40°C to +85°C Level 1 TDFN-14 4. “YYZ” is the date code and assembly code. 5. Shutdown current with VIN = 3.6V, ENP = ENN = 0 and SDA = SCL = 1.8V. 6. KTD2151B I2C inputs are disabled when both ENP and ENN are logic low.

t KTD2151 April 2020 – Revision 04f Page 4 Company Confidential Electrical Characteristics7 Unless otherwise noted, t he Min and Max specs are applied over the full operation temp erature range of –40°C to +85 °C, while Typ values are specified at room temp erature (25°C). VIN = 3.7V, ENN = ENP = VIN, VPOS = +5V, VNEG = -5V Symbol Description Conditions Min Typ Max Units IC Supply VIN Input operating range 2.7 5.5 V UVLO Input under voltage lockout Rising VIN 2.5 V UVLOHYST UVLO hysteresis 0.2 V IQ IC standby current Not switching 620 A IC operating current Switching, no load 1.2 mA ISHDN Shutdown current ENP = ENN = 0V, SDA = SCL = VIN 0.1 A Step-Up DC-DC Converter ILIM Peak NMOS current limit 0.9 A FSW Oscillator frequency 1.8 MHz Dmax Maximum duty cycle 80 86 % TS Start-up time 0.7 ms OUTP Positive Output VPOS VPOS Positive output voltage range 4.0 6.3 V VPOS_ACC Positive output voltage accuracy TA = 25°C -1.0 +1.0 % ILIM_POS Positive output current limit 200 mA VDROP Dropout voltage IOUT = 150mA 150 mV VLINE Line regulation VIN = 3.2V to 4.2V, IOUT = 30mA 0.06 %/V VLOAD Load regulation ΔIOUT = 80mA 6 mV RDISCHARGE Discharge resistance 70 Ω OUTN Negative Output VNEG VNEG Negative output voltage range -4.0 -6.3 V VNEG_ACC Negative output voltage accuracy TA = 25°C -1.0 +1.0 % ILIM_NEG Negative output max regulated current 80 mA FSW_CP Charge pump switching frequency 0.9 MHz VLINE Line regulation VIN = 3.2V to 4.2V, IOUT = 30mA 0.02 %/V VLOAD Load regulation ΔIOUT = 80mA 14 mV RDISCHARGE Discharge resistance 20 Ω Logic Control: ENP, ENN VTH-L ENP, ENN pin logic low threshold VIN = 2.5V to 5.5V 0.4 V VTH-H ENP, ENN pin logic high threshold 1.4 V RENP ENP pull down resistor 500 kΩ RENN ENN pull down resistor 500 kΩ 7. KTD2151 is guaranteed to meet performance specifications over the –40°C to +85 °C operating temperature range by design, characterization and correlation with statistical process controls.

  1. KTD2151 is guaranteed to meet p erformance specification s over the –40°C to +85 °C operating temperature range by design,

characterization and correlation with statistical process controls.

  1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

  1. A fast -mode device can be used in a standard -mode system, but the requirement t SU_DAT = to 250ns must then be met. This is

the SCL signal, it must output the next data bit to the SDA line tR max + tSU_DAT = 1000 + 250 = 1250nsec before the SCL line is released. Figure 1. I2C Compatible Interface Timing

t KTD2151 April 2020 – Revision 04f Page 6 Company Confidential Typical Characteristics VIN = 3.7V, L = 4.7µH (Coilcraft LPS4018 -472), C IN = C REG = C POS = C NEG = 4.7µF, I POS = -INEG = 40mA, Temp = 25°C unless otherwise specified. Default setting: VPOS/VNEG = +/-5.0V, VREG Offset = 200mV. Efficiency vs. Output Current (VPOS/VNEG = +/-5.0V, VREG Offset = 200mV) ENP / ENN Logic Threshold Voltage Quiescent Current Shutdown Current (no load) (ENP = ENN = low) Step-up Converter Switching Frequency 100 1 10 100 Efficiency (%) Output Current (mA) 0.5 0.6 0.7 0.8 0.9 1.0 Vth (V) Input Voltage (V) Vth-H Vth-L Input Supply Current (mA) Input Voltage (V) 100 Shutdown Current (nA) Input Voltage (V) 1.50 1.55 1.60 1.65 1.70 Frequency (MHz) Input Voltage (V) Shutdown Current (µA)

t KTD2151 April 2020 – Revision 04f Page 7 Company Confidential Typical Characteristics VIN = 3.7V, L = 4.7µH (Coilcraft LPS4018 -472), C IN = C REG = C POS = C NEG = 4.7µF, I POS = -INEG = 40mA, TA = 25°C unless otherwise specified. Default setting OUTP/N = +/-5.0V, VREG Offset = 200mV. OUTP Line Regulation OUTN Line Regulation OUTP Load Regulation OUTN Load Regulation Power-up Power-down (40mA load) (40mA load) 4.80 4.85 4.90 4.95 5.00 5.05 5.10 Output Voltage (V) Input Voltage (V) Load = 40mA Load = 10mA -5.10 -5.05 -5.00 -4.95 -4.90 -4.85 -4.80 -4.75 -4.70 Output Voltage (V) Input Voltage (V) Load = 10mA Load = 40mA 4.98 4.99 5.00 5.01 5.02 0 20 40 60 80 Output Voltage (V) Output Current (mA) L = 4.7uH, Reg Offset = 200mV L = 2.2uH, Reg Offset = 200mV -5.02 -5.01 -5.00 -4.99 -4.98 0 20 40 60 80 Output Voltage (V) Output Current (mA) L = 4.7uH, Reg Offset = 200mV L = 2.2uH, Reg Offset = 200mV

t KTD2151 April 2020 – Revision 04f Page 8 Company Confidential Typical Characteristics VIN = 3.7V, L = 4.7µH (Coilcraft LPS4018 -472), C IN = C REG = C POS = C NEG = 4.7µF, I POS = -INEG = 40mA, Temp = 25°C unless otherwise specified. Default setting OUTP/N = +/-5.0V, VREG Offset = 200mV. Switching Waveform Steady-state Operation (IPOS = INEG = 40mA) (IPOS = -INEG = 2mA) Steady-state Operation Steady-state Operation (IPOS = -INEG = 10mA) (IPOS = -INEG = 40mA) Load Transient (5mA to 40mA step load) 400ns / div OUTN AC Coupled 50mV / div OUTP AC Coupled 20mV / div Inductor Current 200mA / div LX 5V / div 10µs / div OUTN AC Coupled 50mV / div OUTP AC Coupled 20mV / div 10µs / div OUTN AC Coupled 50mV / div OUTP AC Coupled 20mV / div 2µs / div OUTN AC Coupled 20mV / div OUTP AC Coupled 20mV / div 100µs / div OUTN AC Coupled 50mV / div OUTP AC Coupled 50mV / div LOAD 50mA / div

t KTD2151 April 2020 – Revision 04f Page 9 Company Confidential Functional Block Diagram Functional Description The KTD2151, powered from single -cell Li-Ion/Polymer batteries from 2.7V to 5.5V, is a dual output converter only requiring a single inductor. The KTD2151 is a dual switching converter to generate both a positive and a negative power supplies that are required by TFT-LCD display panels . The KTD2151 integrates a boost regulator, LDO and charge pump, to generate two regulated output rails OUTP and OUTN, whose voltages can be adjusted by I2C compatible interface. The step-up converter generates a positive voltage on the REG pin that is used by both the positive output and negative output converters. The internal LDO gets its power from the REG pin, drops down the voltage with optimized high efficiency linear control, delivering the positive supply (OUTP). The negative supply ( OUTN) is generated by an integrated inverting voltage regulator charge pump driven from the step-up converter output. The REG offset voltage, equal to the voltage between REG and the Max (OUTP, -OUTN), can be set to 200mV and 300mV depending on the maximum output currents on OUTP and OUTN . Higher output current requires higher offset voltage (headroom) in order to guarantee the best regulation. By adjusting the offset voltage to the lower level 200mV, the overall converter efficiency can be optimized for the application. The device can operate with independent current setting on each output, even with no load on one output and full load on the other. The device integrates full compensation and soft-start circuitry, which results in a simpler and smaller solution with fewer external components. High switching frequency (1.8MHz) allows the use of a smaller inductor and capacitors to further reduce the solution size. Under Voltage Lockout (UVLO) The KTD2151 integrates an Under Voltage Lockout circuit to prevent the IC from operating until VIN pin exceeds the UVLO threshold. Output voltages will not be activated until ena ble signals are applied. All of the internal converters will be disabled as soon as the VIN voltage falls below the UVLO threshold minus the UVLO hysteresis (UVLOHYST). SW OUTP VIN AGND PGND OUTN SCL SDA ENP ENN REG CFLY1 CFLY2 VPOS VNEG Negative Charge-pump Regulator Low Dropout Regulator I2C Interface Digital Control High Efficiency Step-up Converter

t KTD2151 April 2020 – Revision 04f Page 10 Company Confidential Active Discharge The positive rail OUTP and/or the negative rail OUTN can be actively discharged by KTD 2151. The output discharge settings can be programmed by the I2C interface; the default value is ON. When the supply output is powered down, KTD2151 will discharge the corresponding output(s) through the associated R DISCHARGE resistor connected to ground. The power -down happens when both enable signals (ENN, ENP) go low, or when one enable goes low while the other enable is already low . If one output is turned OFF while the other output stays ON, the discharge circuit is inactive for both outputs. Step-Up DC-DC Converter Operation The step-up converter uses a current mode design operating at 1.8 MHz in full load, allowing the use of small value 2.2μH or 4.7μH inductors. The converter dynamically adjusts the output to optimize the highest efficiency depending on OUTP and OUTN voltage requirements. Power-Up and Soft-Start The step-up converter operates when either enable signal, ENN or ENP, is pulled high or I 2C bits are set, and VIN voltage is greater than UVLO. If the enable signal is already high when VIN reaches the UVLO threshold, the step-up converter will start switc hing immediately. An integrated soft-start circuit controls excessive inrush current from the battery during startup. Power-Down The step-up converter powers down when VIN goes below UVLO minus UVLOHYST or after both OUTP and OUTN have been disabled, if VIN is still above UVLO. LDO Regulator Operation (OUTP) The internal LDO gets its power from the REG pin and drops down the voltage, generating the positive voltage rail OUTP. The LDO’s ripple rejection characteristics help to filter the output of the boost converter in order to provide a well-controlled supply for the source driver IC of the TFT-LCD panel. Power-Up and Soft-Start (OUTP) The LDO is activated immediately when ENP signal is asserted, and VIN voltage is above the UVLO threshold and the step-up converter has reached its target voltage. OUTP has a soft-start circuit which slowly ramps-up its output. Power-Down and Discharge (OUTP) The LDO stops operating when VIN drops below the UVLO threshold minus the hysteresis, or when ENP is de- asserted. The positive supply output can be actively discharged to GND through the IC’s R DISCHARGE internal resistor. The discharge selection bit by default is ON, and can be reset or set through register programming. Setting the Output Voltage (OUTP) The output voltage of the LDO is programmable via an I2C compatible interface with 5 bits, from 4.0V to 6.3V with 100mV steps. Regulated Inverting Charge Pump Operation (OUTN) The inverting charge pump generates the negative voltage rail OUTN from the output voltage of the boost converter (VREG). The converter uses a four-switch topology with single external flying capacitor to generate the negative output voltage. The first swi tching phase turns on t wo of the switches to charge the flying capacitor equal to VREG, and the second phase inverts the drive logic of all four switches, negatively connecting the flying capacitor to OUTN. Power-Up and Soft-Start (OUTN) The charge pump is activated immediately when ENN signal is asserted, and VIN voltage is above the UVLO threshold and the step -up converter has reached its target voltage. OUTN has a soft -start circuit which slowly ramps-up its output. Power-Down and Discharge (OUTN) The charge pump stops operating when VIN drops below the UVLO threshold minus UVLO hysteresis or when the ENN is de-asserted. The negative rail can be actively discharged to GND during power -down if required. A discharge selection bit is available to enable or disable this function.

t KTD2151 April 2020 – Revision 04f Page 11 Company Confidential Setting the Output Voltage (OUTN) The output voltage of the charge pump is programmable via an I2C compatible interface with 5 bits, from -4.0V to -6.3V with 100mV steps. Flying Capacitor Selection (OUTN) The charge pump needs a n external flying capacitor with a minimum value of 2.2μF. Ceramic X5R di electric material or better is recommended for best performance. For higher current tablet application, a larger 4.7μF capacitor can be used. For proper operation, the flying capacito r value must be lower than the output capacitor of the boost converter on VREG pin. Thermal Shutdown A thermal shutdown feature is included in the KTD2151. When the IC’s junction temperature (TJ) reaches 150°C, the IC will immediately enter shutdown mode. Once T J drops 15°C to approximately 135 °C, the IC will resume normal operation. I2C interface or Enable Control The KTD2151 can be turned on/off by pulling the ENP/ENN inputs high without using the I2C interface. If the I2C interface is not used, both SDA and SCL inputs should be tied high (for example to VIN directly) or through pull- up resistors. These two inputs should never be left floating (unconnected). KTD2151 can be controlled via the I2C interface, even when both the ENP and ENN inputs are low. KTD2151B I2C inputs are disabled when both ENP and ENN are low. KTD2151B can be controlled via the I 2C interface when ENN or ENP are logic high.

Application Information

Figure 2. I2C Mode Timing Diagram are made through the open-drain I/O lines SDA and SCL.

  • Data transfer may be initiated only when the bus is not busy.
  • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy Both data and clock lines remain HIGH. Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid The state of the data line represents valid data when, after a START co ndition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge -related clock pulse. Of course, setup and hold times must be taken into account. A master mu st signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Figure 3. Data Transfer on I2C Serial Bus

t KTD2151 April 2020 – Revision 04f Page 13 Company Confidential Depending upon the state of the R/W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A tran sfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The KTD2151 can operate in the following two modes: 1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see Figure 4 for Interface). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7 - KTD2151 address followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. After the KTD2151 acknowledges the slave address + write bit, the master transmits a register address to the KTD2151. This sets the register pointer on the KTD2151. The master may then transmit zero or more bytes of data, with the KTD2151 acknowledging each byte received. The address pointer will increment after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the KTD2151 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. The slave address byte is the first byte received after the master generates a S TART condition. The slave address byte contains the 7-bit KTD2151 address followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. The KTD2151 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The KTD2151 must receive a “not acknowledge” to end a read.

The 7-bit slave device address is 0111110 binary (or 3Eh). Figure 4. I2C Write – Slave Receiver Mode Figure 5. I2C Read – Slave Transmitter Mode Figure 6. Example of Read Command written or read via the I2C interface.

0 VPOS

0 VNEG

0 Discharge OUTN

  • When writing to a register, always write a “0” in the reserved bits.

t KTD2151 April 2020 – Revision 04f Page 15 Company Confidential VPOS Positive Voltage Output Setting Register (ADDR 00h, Default 0Ah or 0Ch) VPOS Voltage Setting 4.0V to 6.3V in 100mV steps. VPOS = 4.0V + (code * 100mV). Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Reserved VPOS VPOS VPOS VPOS VPOS OUTP Output Voltage Dec Binary Hex Voltage (V) 0 0000 0000 00h 4.0 1 0000 0001 01h 4.1 2 0000 0010 02h 4.2 3 0000 0011 03h 4.3 4 0000 0100 04h 4.4 5 0000 0101 05h 4.5 6 0000 0110 06h 4.6 7 0000 0111 07h 4.7 8 0000 1000 08h 4.8 9 0000 1001 09h 4.9 10 0000 1010 0Ah 5.0 11 0000 1011 0Bh 5.1 12 0000 1100 0Ch 5.2 13 0000 1101 0Dh 5.3 14 0000 1110 0Eh 5.4 15 0000 1111 0Fh 5.5 16 0001 0000 10h 5.6 17 0001 0001 11h 5.7 18 0001 0010 12h 5.8 19 0001 0011 13h 5.9 20 0001 0100 14h 6.0 21 0001 0101 15h 6.1 22 0001 0110 16h 6.2 23 0001 0111 17h 6.3

t KTD2151 April 2020 – Revision 04f Page 16 Company Confidential VNEG Negative Voltage Output Setting Register (ADDR 01h, Default 0Ah or 0Ch) VNEG Voltage Setting -4.0V to -6.3V in 100mV steps. VNEG = -4.0V – (code * 100mV). Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Reserved VNEG VNEG VNEG VNEG VNEG OUTN Output Voltage Dec Binary Hex Voltage (V) 0 0000 0000 00h -4.0 1 0000 0001 01h -4.1 2 0000 0010 02h -4.2 3 0000 0011 03h -4.3 4 0000 0100 04h -4.4 5 0000 0101 05h -4.5 6 0000 0110 06h -4.6 7 0000 0111 07h -4.7 8 0000 1000 08h -4.8 9 0000 1001 09h -4.9 10 0000 1010 0Ah -5.0 11 0000 1011 0Bh -5.1 12 0000 1100 0Ch -5.2 13 0000 1101 0Dh -5.3 14 0000 1110 0Eh -5.4 15 0000 1111 0Fh -5.5 16 0001 0000 10h -5.6 17 0001 0001 11h -5.7 18 0001 0010 12h -5.8 19 0001 0011 13h -5.9 20 0001 0100 14h -6.0 21 0001 0101 15h -6.1 22 0001 0110 16h -6.2 23 0001 0111 17h -6.3

t KTD2151 April 2020 – Revision 04f Page 17 Company Confidential Control Register 1 (ADDR 03h, Default 03h) REG Offset Control The REG output (output of the step-up controller) voltage is set to the following value: VREG = Max (VPOS, -VNEG) + VOFFSET VREG default value is the maximum of either (VPOS or -VNEG) + 200mV. For example, if VPOS = 5.1V and VNEG = -5V, then the default VREG = 5.1V + 0.2V = 5.3V Fast Discharge Allows quick discharge of the OUTP and OUTN nodes when the outputs are disabled. Default is ON (1). Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Reserved* REG Offset Setting 0 = 200mV (Default) 1 = 300mV Reserved* Discharge OUTP 0 = Disable 1 = Enable (Default) Discharge OUTN 0 = Disable 1 = Enable (Default) * When writing to the register, always write “0” in the reserved bits. For example, to set the REG offset to 300mV and Discharge OUTP/OUTN enable, write 0x43 in the Control register. Capacitor Selection Small size X5R or X7R ceramic capacitors are recommended for the KTD2151 application. 4.7μF capacitors are suggested for the input VIN, and for the outputs REG, OUTP, OUTN. The input capacitor should be placed as close as possible to the input pin and the PGND pin of the KTD2151. For better input voltage filtering, this value can be increased. For the output capacitors, higher capacitor values can be used to improve the load transient response. For higher output current up to 80mA, the REG and OUTN output capacitors can be increased to 10μF. The capacitor data sheet determines what value of capacitor is required to guarantee a minimum capacitance value for a given bias voltage and over operating temperature. Capacitor Comments 2.2µF/16V CFLY 4.7µF/16V CIN, CPOS, CNEG, CREG 10µF/16V CNEG, CREG Manufacturer Website Murata www.murata.com AVX www.avx.com Taiyo Yuden www.t-yuden.com

t KTD2151 April 2020 – Revision 04f Page 18 Company Confidential Inductor Selection An inductor in the range of 2.2µH to 10µH with low DCR can be selected for the boost converter. To estimate the inductance required for applications, calculate the maximum input average current as the following where η is the converter efficiency and can be approximated as 90% for the typical case. In order to have smaller current ripple (to improve efficiency and minimize output voltage ripple), larger inductance will be required. If inductor ripple current needs to be less than 40% of the average input current, then Where duty cycle can be estimated as Then Therefore the inductance can be calculated as where fS is the switching frequency of the boost converter. For smartphone applications with load currents up to 40mA per outputs, a 4.7µH inductor is recommended. For tablet applications with higher load currents up to 80mA per outputs, a 2.2µH inductor is recommended. Inductor Part Number Value (µH) DCR (Ω) Saturation Current (A) Dimensions (mm) Manufacturer LPS3015-472ML 4.7 0.20 max 1.3 3 × 3 × 1.5 Coilcraft LPS3015-222ML 2.2 0.11 max 2.0 3 × 3 × 1.5 Coilcraft IN MAXOUTOUT MAXIN V IVI IN MAXOUTOUTSIN L V IV L TDVI %40 OUT INOUT V VVD −=  −= IN MAXOUTOUT OUT SINOUTIN L V IV VL TVVVI %40)( SMAXOUTOUT INOUTIN fIV VVVL  − %40 )( 

vias. The KTD2151 CSP recommended layout is shown in Figure 7. Figure 7. CSP Recommended PCB Layout

t KTD2151 April 2020 – Revision 04f Page 20 Company Confidential Packaging Information TDFN2.5x3-14 TDFN2.5x3 D E L A Top View Bottom View Side View b e PIN 1 ID 7 1 14 8 1 7 θ Dimension mm Min. Typ. Max. A 0.70 0.75 0.80 A1 0.00 0.025 0.05 A3 0.175 0.20 0.225 D 2.9 3.0 3.1 E 2.4 2.5 2.6 e 0.40 TYP b 0.15 0.20 0.25 L 0.7 0.75 0.8 θ 0° 2° 4°

t KTD2151 April 2020 – Revision 04f Page 21 Company Confidential WLCSP-15 Recommended Footprint Kinetic Technologies cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Kinetic Technologies product. No intellectual property or circuit patent licenses are implied. Kinetic Technologies reserves the right to change the circuitry and specifications without notice at any time. TOP SIDE COATING BUMP A1 CORNER 0.62 ± 0.043mm 2.2mm ± 0.050mm 1.45mm ± 0.050mm 2 X 0.4mm 4 X 0.40mm

15 X Ø

0.25+/-0.025mm 0.025mm ± 0.003mm Top View Bottom ViewSide View WLCSP Landing Pattern * Dimensions are in millimeters. 0.40mm 0.40mm 0.21mm Copper Pad Diameter (NSMD Pad Type) 0.31mm Solder Mask Opening 0.80mm 1.60mm