MAX9000 ALTERA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 42
Technical content
December 2002, ver. 6.4 Data Sheet Usable gates6,0008,00010,00012,000 Flipflops484580676772 Macrocells320400480560 Logic array blocks (LABs)20253035 Maximum user I/O pins168159175216 tPD1 (ns)10151010 tFSU (ns)3.053.03.0 tFCO (ns)4.574.84.8 fCNT (MHz)144118144144
2 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet EPM932060 (2) 132 – 168 – 168 EPM9320A60 (2) 132 ––– 168 EPM940059 (2) 139159 ––– EPM9480 – 146175 ––– EPM9560 – 153 191216216216 EPM9560A – 153 191 –– 216
MAX 9000 Programmable Logic Device Family Data Sheet EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A 16-bit loadable counter16144118100MHz 16-bit up/down counter16144118100MHz 16-bit prescaled counter16144118100MHz 16-bit address decode15.6 (10)7.9 (15)10 (20)ns 16-to-1 multiplexer17.7 (12.1)10.9 (18)16 (26)ns
4 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
MAX 9000 Programmable Logic Device Family Data Sheet
6 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet IOCIOC IOC IOC IOC IOC IOC IOC IOC IOC IOCIOC IOCIOC IOC IOC
MAX 9000 Programmable Logic Device Family Data Sheet To Peripheral Bus and Other LABs in the Device DIN2 GCLR 16 16 Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 GCLK1 GCLK2 DIN3 DIN4 GOE To Peripheral Bus DIN1 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16
8 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet VCC Product- Term Select Matrix
16 Local
(from Other Macrocells) Clear Select Global Clear Global Clocks Clock/ Enable Select PRN CLRN D/TQ ENA To Row or Column FastTrack Interconnect Local Array Feedback
MAX 9000 Programmable Logic Device Family Data Sheet
10 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
16 Shared
MAX 9000 Programmable Logic Device Family Data Sheet Preset Clock Clear Product- Term Select Matrix Preset Clock Clear Product- Term Select Matrix From Previous Macrocell To Next Macrocell
12 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
MAX 9000 Programmable Logic Device Family Data Sheet LAB LAB LAB LAB IOC1 IOC10 IOC1 IOC10 IOC1 IOC8 IOC1 IOC8 IOC1 IOC10IOC1 IOC10 IOC1 IOC8 IOC1 IOC8 EPM9320, EPM9320A45 EPM940055 EPM948065 EPM9560, EPM9560A75
14 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet Macrocell 1 Macrocell 2 To LAB Local Array LAB
MAX 9000 Programmable Logic Device Family Data Sheet IOC8 IOC110 Row FastTrack Interconnect
16 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet 1717 Column FastTrack Interconnect IOC10IOC1
MAX 9000 Programmable Logic Device Family Data Sheet Slew-Rate Control From Row or Column FastTrack Interconnect To Row or Column FastTrack Interconnect OE [7..0] CLK [3..0] ENA [5..0] CLR [1..0] Peripheral Control Bus [12..0] CLRN DQ ENA VCC VCC VCC
18 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet Row CRow ERow FRow G Row BRow ERow FRow F Row ARow ERow ERow E Row BRow BRow BRow B Row ARow ARow ARow A Row DRow DRow DRow D Row CRow CRow CRow C Row B/ Row B/ Row B/ Row B/ Row A/ Row A/ Row A/ Row A/ Row DRow DRow DRow D Row CRow CRow CRow C
MAX 9000 Programmable Logic Device Family Data Sheet
20 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet SAMPLE/PRELOADAllows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTESTAllows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASSPlaces the 1-bit bypass register between the and pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. IDCODESelects the IDCODE register and places it between and , allowing the IDCODE to be shifted out of . Supported by the EPM9320A, EPM9400, EPM9480, and EPM9560A devices only. UESCODE Selects the user electronic signature (UESCODE) register and allows the UESCODE to be shifted out of serially. This instruction is supported by MAX9000A devices only. ISP InstructionsThese instructions are used when programming MAX9000 devices via the JTAG ports with the BitBlaster or ByteBlasterMV download cable, or using a Jam File ( .jam), Jam Byte-Code File (.jbc), or Serial Vector Format (.svf) File via an embedded processor or test equipment.
MAX 9000 Programmable Logic Device Family Data Sheet EPM9320, EPM9320A504 EPM9400552 EPM9480600 EPM9560, EPM9560A648 EPM9320A (3) EPM9400 EPM9480 EPM9560A (3)
22 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet tJCP clock period 100ns tJCH clock high time 50ns tJCL clock low time 50ns tJPSU JTAG port setup time 20ns tJPH JTAG port hold time 45ns tJPCO JTAG port clock to output25ns tJPZX JTAG port high impedance to valid output25ns tJPXZ JTAG port valid output to high impedance25ns tJSSU Capture register setup time20ns tJSH Capture register hold time45ns tJSCO Update register clock to output25ns tJSZX Update register high impedance to valid output25ns tJSXZ Update register valid output to high impedance25ns TDO TCK tJPZX tJPCO tJPH tJPXZ tJCP tJPSU tJCL tJCH TDI TMS Signal to Be Captured Signal to Be Driven tJSZX tJSSU tJSH tJSCO tJSXZ
MAX 9000 Programmable Logic Device Family Data Sheet VCC To Test System C1 (includes JIG capacitance) Device input rise and fall times < 3 ns Device Output 464 (703 250 (8.06 K
24 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet VCC Supply voltageWith respect to ground (2) –2.07.0V VI DC input voltage –2.07.0V VCCISP Supply voltage during in-system programming –2.07.0V IOUT DC output current, per pin –2525mA TSTG Storage temperatureNo bias –65150 C TAMB Ambient temperatureUnder bias –65135 C TJ Junction temperatureCeramic packages, under bias150 C PQFP and RQFP packages, under bias135 C VCCINT Supply voltage for internal logic and input buffers (3), (4) 4.75 (4.50) 5.25 (5.50) V VCCIO Supply voltage for output drivers, 5.0-V operation (3), (4) 4.75 (4.50) 5.25 (5.50) V Supply voltage for output drivers, 3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.60) V VCCISP Supply voltage during in-system programming 4.755.25V VI Input voltage –0.5V CCINT + 0.5 V VO Output voltage 0V CCIO V TA Ambient temperatureFor commercial use070 C For industrial use –4085 C TJ Junction temperatureFor commercial use090 C For industrial use –40105 C tR Input rise time 40ns tF Input fall time 40ns
MAX 9000 Programmable Logic Device Family Data Sheet VIH High-level input voltage (7) 2.0V CCINT + 0.5 V VIL Low-level input voltage –0.50.8V VOH 5.0-V high-level TTL output voltageI OH = –4 mA DC, VCCIO = 4.75 V (8) 2.4V 3.3-V high-level TTL output voltageI OH = –4 mA DC, VCCIO = 3.00 V (8) 2.4V 3.3-V high-level CMOS output voltageI OH = –0.1 mA DC, VCCIO = 3.00 V (8) VCCIO – 0.2 V VOL 5.0-V low level TTL output voltageI OL = 12 mA DC, VCCIO = 4.75 V (8) 0.45V 3.3-V low-level TTL output voltageI OL = 12 mA DC, VCCIO = 3.00 V (8) 0.45V 3.3-V low-level CMOS output voltageI OL = 0.1 mA DC, VCCIO = 3.00 V (8) 0.2V II I/O pin leakage current of dedicated input pins VI = –0.5 to 5.5 V (9) –1010 A IOZ Tri-state output off-state currentV I = –0.5 to 5.5 V –4040 A C DIN1 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz18pF C DIN2 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz18pF C DIN3 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz17pF C DIN4 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz20pF C I/O I/O pin capacitanceV IN = 0 V, f = 1.0 MHz12pF C DIN1 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz16pF C DIN2 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz10pF C DIN3 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz10pF C DIN4 Dedicated input capacitanceV IN = 0 V, f = 1.0 MHz12pF C I/O I/O pin capacitanceV IN = 0 V, f = 1.0 MHz8pF ICC1 ICC supply current (low-power mode, standby, typical) VI = ground, no load (11) 106132140146mA
26 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet ICC1 ICC supply current (low-power mode, standby, typical) VI = ground, no load (11) 99174mA 12345 150 120 VCCIO = 5.0 V IOL IOH Room Temperature 12345 150 120 VCCIO = 3.3 V IOL IOH Room Temperature 3.3 Typical I Output Current (mA) Output Voltage (V)Output Voltage (V) O Typical I Output Current (mA) O 5.0-V3.3-V
MAX 9000 Programmable Logic Device Family Data Sheet
28 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet Macrocell tRD tCOMB tSU tH tPRE tCLR Macrocell/ Register Delays Logic Array Delay tLAD Register Control Delay Shared Expander Delay tSEXP Global Input Delays I/O Pin tINREG tIODR tIODC I/O Register DelaysOutput Data Delay I/O Cell Control Delay Input Delay Output Delays tIORD tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 IOC tCOL tROW tLOCAL Parallel Expander Delay tPEXP tDIN_D tDIN_CLK tDIN_CLR tDIN_IO tDIN_IOC FastTrack Drive Delay tINCOMB I/O Register Feedback Delay tIOFD tLAC tIC tEN tFTD tIOC
MAX 9000 Programmable Logic Device Family Data Sheet tPD1 Row I/O pin input to row I/O pin output C1 = 35 pF (2) 10.015.020.0ns tPD2 Column I/O pin input to column I/O pin output C1 = 35 pF (2) EPM9320A10.8ns EPM932016.023.0ns EPM940016.223.2ns EPM948016.423.4ns EPM9560A11.4ns EPM956016.623.6ns tFSU Global clock setup time for I/O cell 3.05.06.0ns tFH Global clock hold time for I/O cell 0.00.00.0ns tFCO Global clock to I/O cell output delay tCNT Minimum internal global clock period (4) 6.98.510.0ns fCNT Maximum internal global clock frequency (4) 144.9117.6100.0MHz
30 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet tLAD Logic array delay3.54.04.5ns tLAC Logic control array delay3.54.04.5ns tIC Array clock delay3.54.04.5ns tEN Register enable time3.54.04.5ns tSEXP Shared expander delay3.55.07.5ns tPEXP Parallel expander delay0.51.02.0ns tRD Register delay0.51.01.0ns tCOMB Combinatorial delay0.41.01.0ns tSU Register setup time2.43.04.0ns tH Register hold time2.03.54.5ns tPRE Register preset time3.54.04.5ns tCLR Register clear time3.74.04.5ns tFTD FastTrack drive delay0.51.02.0ns tLPA Low-power adder (5) 10.015.020.0ns
MAX 9000 Programmable Logic Device Family Data Sheet tIODR I/O row output data delay0.20.21.5ns tIODC I/O column output data delay0.40.21.5ns tIOC I/O control delay (6) 0.51.02.0ns tIORD I/O register clock-to-output delay 0.61.01.5ns tIOCOMB I/O combinatorial delay0.21.01.5ns tIOSU I/O register setup time before clock 2.04.05.0ns tIOH I/O register hold time after clock 1.01.01.0ns tIOCLR I/O register clear delay1.53.03.0ns tIOFD I/O register feedback delay0.00.00.5ns tINREG I/O input pad and buffer to I/O register delay 3.54.55.5ns tINCOMB I/O input pad and buffer to row and column delay 1.52.02.5ns tOD1 Output buffer and pad delay, Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF 1.82.52.5ns tOD2 Output buffer and pad delay, Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF 2.33.53.5ns tOD3 Output buffer and pad delay, Slow slew rate = on, VCCIO = 5.0 V or 3.3 V C1 = 35 pF 8.310.010.5ns tXZ Output buffer disable delayC1 = 5 pF2.52.52.5ns tZX1 Output buffer enable delay, Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF 2.52.52.5ns tZX2 Output buffer enable delay, Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF 3.03.53.5ns tZX3 Output buffer enable delay, Slow slew rate = on, VCCIO = 3.3 V or 5.0 V C1 = 35 pF 9.010.010.5ns
32 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet tLOCAL LAB local array delay0.50.50.5 ns tROW FastTrack row delay (6) 0.91.42.0 ns tCOL FastTrack column delay (6) 0.91.73.0 ns tDIN_D Dedicated input data delay4.04.55.0 ns tDIN_CLK Dedicated input clock delay2.73.54.0 ns tDIN_CLR Dedicated input clear delay4.55.05.5 ns tDIN_IOC Dedicated input I/O register clock delay 2.53.54.5 ns tDIN_IO Dedicated input I/O register control delay 5.56.06.5 ns
MAX 9000 Programmable Logic Device Family Data Sheet EPM93200.810.330.056 EPM9320A0.560.310.024 EPM94000.600.330.053 EPM94800.680.290.064 EPM95600.680.260.052 EPM9560A0.560.310.024
34 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet Frequency (MHz) 1000 200 400 600 800 50 75 10012525
118 MHz
Frequency (MHz) 1000 200 400 600 800 50 75 10012525
144 MHz
59 MHz
42 MHz
(mA) Typical ICC Active (mA) Frequency (MHz) Frequency (MHz) 1000 200 400 600 800 50 75 10012525 (mA) Typical ICC Active (mA)
MAX 9000 Programmable Logic Device Family Data Sheet Frequency (MHz)
42 MHz 59 MHz
Frequency (MHz) 1000 200 400 600 800 50 75 10012525 (mA) Typical ICC Active (mA) 1182V10AD13 84183U10AF14 )13153V17AD1 )724W2AC24 4378A9A18 5549D6E23 4279C11A13 30108A18D3
36 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet 6, 18, 24, 25, 48, 61, 67, 70 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16 A9, A22, A25, A26, B25, B26, D2, E1, E26, F2, G1, G25, G26, H2, J1, J25, J26, K2, L26, M26, N1, N25, P26, R2, T1, U2, U26, V1, V25, W25, Y26, AA2, AB1, AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 (5.0 V only) 14, 21, 28, 57, 64, 71 10, 19, 30, 45, 112, 128, 139, 148 D15, E8, E10, E12, E14, R7, R9, R11, R13, R14, T14 D26, F1, H1, K26, N26, P1, U1, W26, AE26, AF25, AF26 (3.3 or 5.0V) 15, 37, 60, 795, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 D14, E7, E9, E11, E13, R6, R8, R10, R12, T13, T15 A1, A2, A21, B1, B10, B24, D1, H26, K1, M25, R1, V26, AA1, AC25, AF5, AF8, AF19 No Connect (N.C.) 109, 140, 141, 142, 144, 145, 146, 147, 149, 150, 151 B6, K19, L2, L4, L18, L19, M1, M2, M3, M4, M16, M17, M18, M19, N1, N2, N3, N4, N16, N17, N18, N19, P1, P2, P3, P17, P18, P19, R1, R2, R3, R17, R18, R19, T1, T2, T3, T17, T18, T19, U1, U2, U3, U17, U18, U19, V1, V2, V19, W1 B4, B5, B6, B7, B8, B9, B11, B12, B13, B14, B15, B16, B18, B19, B20, B21, B22, B23, C4, C23, D4, D23, E4, E22, F4, F23, G4, H4, H23, J23, K4, L4, L23, N4, P4, P23, R3, R26, T2, T3, T4, T5, T22, T23, T24, T25, T26, U3, U4, U5, U22, U23, U24, U25, V2, V3, V4, V5, V22, V23, V24, W1, W2, W3, W4, W5, W22, W23, W24, Y1, Y2, Y3, Y4, Y5, Y22, Y23, Y24, Y25, AA3, AA4, AA5, AA22, AA23, AA24, AA25, AA26, AB2, AB3, AB4, AB5, AB23, AB24, AB25, AC1, AC2, AC23, AD4, AD23, AE4, AE5, AE6, AE7, AE9, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 (4) 5648C4E25 Total User I/O Pins (5) 60132168168
MAX 9000 Programmable Logic Device Family Data Sheet )2182210 )1183211 )12153187 )744234 437891 544968 427992 31108114 66, 69, 73 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 (5.0 V only)16, 23, 30, 56, 63, 7010, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, 137, 157, 177 127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 144, 145, 146, 147, 149, 150, 151 12, 13, 168, 169, 170, 171, 172, 173, 174, 175, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 (3) 554867 Total User I/O Pins (4) 59139159
38 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet )182210 )183211 )153187 )4234 7891 4968 7992 108114 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 (5.0 V only)10, 19, 30, 45, 112, 128, 139, 148 4, 24, 44, 64, 117, 137, 157, 177 127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 No Connect (N.C.)6, 7, 8, 9, 109, 149, 150, 151 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 (2) 4867 Total User I/O Pins (3) 146175
MAX 9000 Programmable Logic Device Family Data Sheet 182210V10266AD13 183211U10267AF14 )153187V17237AD1 )4234W2296AC24 7891A9114A18 4968D685E23 7992C11115A13 108114A18144D3 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 5, 14, 25, 34, 45, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16 62, 73, 74, 102, 121, 138, 155, 166, 167, 186, 187, 206, 207, 226, 254, 273, 290 A9, A22, A25, A26, B25, B26, D2, E1, E26, F2, G1, G25, G26, H2, J1, J25, J26, K2, L26, M26, N1, N25, P26, R2, T1, U2, U26, V1, V25, W25, Y26, AA2, AB1, AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 (5.0 V only) 10, 19, 30, 45, 112, 128, 139, 148 137, 157, 177 D15, E8, E10, E12, E14, R7, R9, R11, R13, R14, T14 12, 32, 52, 72, 157, 177, 197, 217 D26, F1, H1, K26, N26, P1, U1, W26, AE26, AF25, AF26 (3.3 or 5.0V) 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 101, 116, 136, 156, 176, 192, 205, 220, 235 D14, E7, E9, E11, E13, R6, R8, R10, R12, T13, T15 3, 23, 43, 63, 91, 108, 127, 156, 176, 196, 216, 243, 260, 279 A1, A2, A21, B1, B10, B24, D1, H26, K1, M25, R1, V26, AA1, AC25, AF5, AF8, AF19
40 Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet No Connect (N.C.) 109 – B6, W11, 2, 76, 77, 78, 84, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 297, 298, 299, 300, 301, 302, 303, 304 B4, B5, B6, B7, B8, B9, B11, B12, B13, B14, B15, B16, B18, B19, B20, B21, B22, B23, C4, C23, D4, D23, E4, E22, F4, F23, G4, H4, H23, J23, K4, L4, L23, N4, P4, P23, T4, T23, U4, V4, V23, W4, Y4, AA4, AA23, AB4, AB23, AC23, AD4, AD23, AE4, AE5, AE6, AE7, AE9, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 (3) 4867C475E25 Total User I/O Pins (4) 153191216216216
MAX 9000 Programmable Logic Device Family Data Sheet
MAX 9000 Programmable Logic Device Family Data Sheet
42 Altera Corporation
Printed on Recycled Paper.