EPF81500A

FLEX8000_1 ALTERA | Alldatasheet

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Table 1. FLEX 8000 Device Features

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FLEX 8000 Programmable Logic Device Family Data Sheet ...and More

Features

■ Peripheral register for fast setup and clock-to-output delay ■ Fabricated on an advanced SRAM process ■ Available in a variety of packages with 84 to 304 pins (see Table 2) ■ Software design support and automatic place-and-route provided by the Altera® MAX+PLUS® II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest Note: (1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. General

Description

Altera’s Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and field- programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources. JTAG BST circuitry Yes No Yes Yes No Yes Table 2. FLEX 8000 Package Options & I/O Pin Count Note (1)

performance and LE requirements for typical applications. Table 3. FLEX 8000 Performance

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FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a FLEX 8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. The FLEX 8000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry- standard PC- and UNIX workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. The MAX+PLUS II software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUS II development system includes DesignWare functions that are optimized for the FLEX 8000 architecture. f For more information on the MAX+PLUS II software, go to the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. Functional The FLEX 8000 architecture incorporates a large matrix of compact building blocks called logic elements (LEs). Each LE contains a 4-input LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability. The fine-grained structure of the LE provides highly efficient logic implementation. Eight LEs are grouped together to form a logic array block (LAB). Each FLEX 8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing.

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LAB provides the coarse-grained structure of the FLEX 8000 architecture. diagram of the FLEX 8000 LAB. Figure 2. FLEX 8000 Logic Array Block

Each LAB provides four control signals that can be used in all eight LEs. driven into the local interconnect of the target LAB. architecture, with a compact size that provides efficient logic utilization. and cascade chain. Figure 3 shows a block diagram of an LE. Figure 3. FLEX 8000 LE bypassed and the output of the LUT goes directly to the output of the LE.

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FLEX 8000 Programmable Logic Device Family Data Sheet The FLEX 8000 architecture provides two dedicated high-speed data paths—carry chains and cascade chains—that connect adjacent LEs without using local interconnect paths. The carry chain supports high- speed counters and adders; the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in an LAB and all LABs in the same row. Heavy use of carry and cascade chains can reduce routing flexibility. Therefore, the use of carry and cascade chains should be limited to speed-critical portions of a design. Carry Chain The carry chain provides a very fast (less than 1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit moves forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 8000 architecture to implement high-speed counters and adders of arbitrary width. The MAX+PLUS II Compiler can create carry chains automatically during design processing; designers can also insert carry chain logic manually during design entry. Figure 4 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register is typically bypassed for simple adders, but can be used for an accumulator function. Another portion of the LUT and the carry chain logic generate the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to another LE, where it can be used as a general-purpose signal. In addition to mathematical functions, carry chain logic supports very fast counters and comparators.

Figure 4. FLEX 8000 Carry Chain Operation effective width of a function, with a delay as low as 0.6 ns per LE.

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LAB cascades to the first LE of the next LAB. chain, 4.2 ns is needed to decode a 16-bit address. Figure 5. FLEX 8000 Cascade Chain Operation inputs to the LE provide clock, clear, and preset control for the register. designing for the operating mode that supports the desired application.

Figure 6. FLEX 8000 LE Operating Modes

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FLEX 8000 Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the MAX+PLUS II Compiler automatically selects the carry-in or the DATA3 signal as an input. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. The LE-Out signal—the data output of the LE—is either the combinatorial output of the LUT and cascade chain, or the data output (Q)of the programmable register. Arithmetic Mode The arithmetic mode offers two 3-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT provides a 3-bit function; the other generates a carry bit. As shown in Figure 6, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three bits: a, b, and the carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports a cascade chain. Up/Down Counter Mode The up/down counter mode offers counter enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals, without using the LUT resources. Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control; the clear function is substituted for the cascade-in signal in the up/down counter mode. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a synchronous clear.

FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable signals select the signal that drives the bus. However, if multiple output enable signals are active, contending signals can be driven onto the bus. Conversely, if no output enable signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The MAX+PLUS II software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The clear and preset control structure of the LE is used to asynchronously load signals into a register. The register can be set up so that LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register. During compilation, the MAX+PLUS II Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active-low, the Compiler automatically assigns a logic high to an unused clear or preset. The clear and preset logic is implemented in one of the following six asynchronous modes, which are chosen during design entry. LPM functions that use registers will automatically use the correct asynchronous mode. See Figure 7. ■ Clear only ■ Preset only ■ Clear and preset ■ Load with clear ■ Load with preset ■ Load without clear or preset

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Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes

FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl asynchronously loads a 1 into the register. Alternatively, the MAX+PLUS II software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes. Asynchronous Clear & Preset When implementing asynchronous clear and preset, LABCTRL1 controls the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC; therefore, asserting LABCTRL1 asynchronously loads a 1 into the register, effectively presetting the register. Asserting LABCTRL2 clears the register. Asynchronous Load with Clear When implementing an asynchronous load with the clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. LABCTRL2 implements the clear by controlling the register clear. Asynchronous Load with Preset When implementing an asynchronous load in conjunction with a preset, the MAX+PLUS II software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 clears the register, while asserting LABCTRL1 loads the register. The MAX+PLUS II software inverts the signal that drives the DATA3 signal to account for the inversion of the register’s output. Asynchronous Load without Clear or Preset When implementing an asynchronous load without the clear or preset, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear.

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between logic resources and reduces performance. interconnect can then drive I/O pins or feed other LABs in the device. Figure 8 shows how an LE drives the row and column interconnect. Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect

16 Column

(1) See Table 4 for the number of row channels.

with access to 8 row channels. Table 4. FLEX 8000 FastTrack Interconnect Resources

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Figure 9. FLEX 8000 Device Interconnect Resources Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device. appropriate. Figure 10 shows the IOE block diagram.

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Figure 11. FLEX 8000 Row-to-IOE Connections (1) n = 13 for EPF8282A and EPF8282AV devices. n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. n = 27 for EPF81500A devices. of the 16 column channels through an 8-to-1 multiplexer. Numbers in parentheses are for EPF81500A devices. See Note (1).

Figure 12. FLEX 8000 Column-to-IOE Connections they can feed the local interconnect of each LAB in the device. IOEs are located at the ends of the row and column interconnect channels. from the row and column interconnect when appropriate. output enable signals are shared with one clock and one clear signal.

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Figure 13. The number of row channels in a row that can drive the EPF81500A devices) can be accessed by each IOE. Figure 13. FLEX 8000 Peripheral Bus (1) n = 13 for EPF8282A and EPF8282AV devices. n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. n = 27 for EPF81500A devices. Numbers in parentheses are for EPF8 1500A devices.

operation for FLEX 8000 devices. slew rate to all pins on a global basis. Note 75 (High-Speed Board Designs). Table 5. Row Sources of FLEX 8000 Peripheral Control Signals

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(VCCINT), and another set for I/O output drivers (VCCIO). compatible with 3.3-V and 5.0-V inputs. circuitry support the JTAG instructions shown in Table 6. Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions normal device operation, and permits an initial data pattern to be output at the device pins. pattern at the output pins and capturing test results at the input pins.

shows the boundary-scan register length for FLEX 8000 devices. pins. Figure 14 shows the timing requirements for the JTAG signals. Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. Table 7. FLEX 8000 Boundary-Scan Register Length

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Generic Testing Each FLEX 8000 device is functionally tested and specified by Altera. during all stages of the production flow. Table 8. JTAG Timing Parameters & Values

Figure 15. FLEX 8000 AC Test Conditions capacitance for 5.0-V FLEX 8000 devices. observable noise immunity can result. Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings Note (1)

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Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions Table 11. FLEX 8000 5.0-V Device DC Operating Conditions Notes (5), (6)

(1) See the Operating Requirements for Altera Devices Data Sheet . currents less than 100 mA and periods shorter than 20 ns. (3) The maximum V CC rise time is 100 ms. (4) Numbers in parentheses are for industrial-temperature-range devices. (5) Typical values are for T A = 25° C and V CC = 5.0 V. (6) These values are specified in Table 10 on page 28. (8) Capacitance is sample-tested only. capacitance for 3.3-V FLEX 8000 devices. Table 12. FLEX 8000 5.0-V Device Capacitance Note (8) Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings Note (1) Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions

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(1) See the Operating Requirements for Altera Devices Data Sheet . for input currents less than 100 mA and periods shorter than 20 ns. (3) The maximum V CC rise time is 100 ms. VCC must rise monotonically. (4) These values are specified in Table 14 on page 29 . (5) The I OH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. (6) Typical values are for T A = 25° C and VCC = 3.3 V. (7) Capacitance is sample-tested only. Specification, Revision 2.2. Table 15. FLEX 8000 3.3-V Device DC Operating Conditions Note (4) Table 16. FLEX 8000 3.3-V Device Capacitance Note (7)

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Figure 18. Output Drive Characteristics of EPF8282AV Devices prediction, and device-wide performance analysis.

Table 17. FLEX 8000 Internal Timing Parameters Note (1) Table 18. FLEX 8000 LE Timing Parameters Note (1)

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(2) These values are specified in Table 10 on page 28 or Table 14 on page 29. OD3 and tZX3 parameters, VCCIO = 3.3 V or 5.0 V. timing analysis is required to determine actual worst-case performance. subset of signal paths is tested to approximate typical device applications. (6) For more information on test conditions, see Application Note 76 (Understanding FLEX 8000 Timing ). parameter applies to global and non-global clocking, and for LE and I/O element registers. (Understanding FLEX 8000 Timing). Table 19. FLEX 8000 Interconnect Timing Parameters Note (1) Table 20. FLEX 8000 External Reference Timing Characteristics Note (5)

Figure 19. FLEX 8000 Timing Model

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Table 21. FLEX 8000 Timing Model Interconnect Paths Table 22. EPF8282A Internal I/O Element Timing Parameters

Table 23. EPF8282A Interconnect Timing Parameters

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Table 24. EPF8282A LE Timing Parameters Table 25. EPF8282A External Timing Parameters

Table 26. EPF8282AV I/O Element Timing Parameters Table 27. EPF8282AV Interconnect Timing Parameters

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Table 28. EPF8282AV Logic Element Timing Parameters Table 29. EPF8282AV External Timing Parameters

Table 30. EPF8452A I/O Element Timing Parameters Table 31. EPF8452A Interconnect Timing Parameters

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Table 32. EPF8452A LE Timing Parameters Table 33. EPF8452A External Timing Parameters

Table 34. EPF8636A I/O Element Timing Parameters Table 35. EPF8636A Interconnect Timing Parameters

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Table 36. EPF8636A LE Timing Parameters Table 37. EPF8636A External Timing Parameters

Table 38. EPF8820A I/O Element Timing Parameters Table 39. EPF8820A Interconnect Timing Parameters

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Table 40. EPF8820A LE Timing Parameters Table 41. EPF8820A External Timing Parameters

Table 42. EPF81188A I/O Element Timing Parameters Table 43. EPF81188A Interconnect Timing Parameters

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Table 44. EPF81188A LE Timing Parameters Table 45. EPF81188A External Timing Parameters

Table 46. EPF81500A I/O Element Timing Parameters Table 47. EPF81500A Interconnect Timing Parameters

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Table 48. EPF81500A LE Timing Parameters Table 49. EPF81500A External Timing Parameters

current that each LE typically consumes. the device and the environmental operating conditions. for several LE utilization values. Table 50. Values for Constant K

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Figure 20. FLEX 8000 ICCACTIVE vs. Operating Frequency Devices) and Application Note 38 (Configuring Multiple FLEX 8000 Devices).

500 LEs

200 LEs

150 LEs

100 LEs

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resets registers, enables I/O pins, and begins to operate as a logic device. called command mode; normal device operation is called user mode. distributing new configuration files. six configuration schemes, chosen on the basis of the target application. shows the data source for each of the six configuration schemes. Table 51. Data Source for Configuration

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pins in each FLEX 8000 device package. Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 1 of 3)

Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 2 of 3)

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Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 3 of 3)

Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)

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Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)

Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)

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Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)

Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)

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FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables: (1) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices) for more information. (2) This pin is a dedicated pin and is not available as a user I/O pin. (3) SDOUT will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the MAX+PLUS II software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUS II software and use SDOUT as a user I/O pin. (4) If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin. (5) JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins. (6) If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration. (7) TRST is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used. (8) Pin 52 is a V CC pin on EPF8452A devices only. (9) The user I/O pin count includes dedicated input pins and all I/O pins. (10) Unused dedicated inputs should be tied to ground on the board. (11) SDOUT does not exist in the EPF8636GC192 device. (12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices. (13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins. (14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is not used, TDI, TCK, TMS, and TRST should be tied to GND. Revision History The information contained in the FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 supersedes information published in previous versions. The FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 contains the following change: minor textual updates.