EPM7128STC100-10N ALTECH | Alldatasheet
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Table 1. MAX 7000 Device Features
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MAX 7000 Programmable Logic Device Family Data Sheet ...and More
Features
■ Open-drain output option in MAX 7000S devices ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable power-saving mode for a reduction of over 50% in each macrocell ■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell ■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages ■ Programmable security bit for protection of proprietary designs ■ 3.3-V or 5.0-V operation –M u l t i V o l t TM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages) – Pin compatible with low-voltage MAX 7000A and MAX 7000B devices ■ Enhanced features available in MAX 7000E and MAX 7000S devices – Six pin- or logic-driven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Fast input setup times provided by a dedicated path from I/O pin to macrocell registers – Programmable output slew-rate control ■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Table 2. MAX 7000S Device Features
MAX 7000 Programmable Logic Device Family Data Sheet ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest ■ Programming support – Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices –T h e B i t B l a s t e rTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX 7000S devices General
Description
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades. Table 3. MAX 7000 Speed Grades
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(1) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. (2) The MultiVolt I/O interface is not available in 44-pin packages. Table 4. MAX 7000 Device Features
RQFP, and TQFP packages. See Table 5. the Operating Requirements for Altera Devices Data Sheet. Table 5. MAX 7000 Maximum User I/O Pins Note (1)
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MAX 7000 Programmable Logic Device Family Data Sheet MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 7000 family provides programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000 devices (except 44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing MAX 7000 devices to be used in mixed-voltage systems. The MAX 7000 family is supported byAltera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)— and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry- standard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Functional The MAX 7000 architecture includes the following elements: ■ Logic array blocks ■ Macrocells ■ Expander product terms (shareable and parallel) ■ Programmable interconnect array ■ I/O control blocks
EPM7064, and EPM7096 devices. Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram
36 I/O
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Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 7000S Device Block Diagram (LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2.
6 Output Enables 6 Output Enables
EPM7064, and EPM7096 devices is shown in Figure 3. Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
36 Signals
16 Expander
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Figure 4 shows a MAX 7000E and MAX 7000S device macrocell. Figure 4. MAX 7000E & MAX 7000S Device Macrocell allocation according to the logic requirements of the design. clock control. The flipflop can be bypassed for combinatorial operation. operation for each registered function to optimize resource utilization.
MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: ■ By a global clock signal. This mode achieves the fastest clock-to- output performance. ■ By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. ■ By an array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. In EPM7032, EPM7064, and EPM7096 devices, the global clock signal is available from a dedicated clock pin, GCLK1, as shown in Figure 1. In MAX 7000E and MAX 7000S devices, two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figures 3 and 4, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear of the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in the device will be set to a low state. All MAX 7000E and MAX 7000S I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be driven to an input D flipflop with an extremely fast (2.5 ns) input setup time. Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources; however, the MAX 7000 architecture also allows both shareable and parallel expander product terms (“expanders”) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.
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can feed multiple macrocells. Figure 5. Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. neighboring macrocell to implement fast, complex logic functions. 15 parallel expanders provided by neighboring macrocells in the LAB.
16 Shared
automatically to the macrocells that require additional product terms. borrowed from a neighboring macrocell. Figure 6. Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell.
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Figure 7. PIA Routing makes timing performance easy to predict. are driven by two dedicated active-low output enable pins (OE1 and OE2).
Figure 8. I/O Control Block of MAX 7000 Devices (1) The open-drain output option is available only in MAX 7000S devices.
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MAX 7000 Programmable Logic Device Family Data Sheet When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 7000 architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. In-System Programma- bility (ISP) MAX 7000S devices are in-system programmable via an industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1-1990). ISP allows quick, efficient iterations during design development and debugging cycles. The MAX 7000S architecture internally generates the high programming voltage required to program EEPROM cells, allowing in-system programming with only a single 5.0 V power supply. During in-system programming, the I/O pins are tri-stated and pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k¾. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. MAX 7000S devices can be programmed by downloading the information via in-circuit testers (ICT), embedded processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cables. (The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable, which can program and configure 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling and allows devices to be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. The Jam TM Standard Test and Programming Language (STAPL) can be used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor.
MAX 7000 Programmable Logic Device Family Data Sheet f For more information on using the Jam language, refer to AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor. The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 7000S device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1m s . 2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. 3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. 4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. 6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1m s .
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MAX 7000 Programmable Logic Device Family Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ A pulse time to erase, program, or read the EEPROM cells. ■ A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000S Device The time required to program a single MAX 7000S device in-system can be calculated from the following formula: where: tPROG = Programming time tPPULSE = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK =N u m b e r o f TCK cycles to program a device fTCK = TCK frequency The ISP times for a stand-alone verification of a single MAX 7000S device can be calculated from the following formula: where: tVER =V e r i f y t i m e tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK =N u m b e r o f TCK cycles to verify a device tPROG tPPULSE Cycle PTCK fTCK tVER tVPULSE Cycle VTCK fTCK
with the worst-case method using the enhanced ISP algorithm. verification times for several common test clock frequencies. Table 6. MAX 7000S tPULSE & CycleTCK Values Table 7. MAX 7000S In-System Programming Times for Different Test Clock Frequencies
10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies
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MAX 7000 Programmable Logic Device Family Data Sheet Programmable Speed/Power Control MAX 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000 device for either high-speed (i.e., with the Turbo BitTM option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tEN, and tSEXP, tACL, and tCPPW parameters. Output Configuration MAX 7000 device outputs can be programmed to meet a variety of system-level requirements. MultiVolt I/O Interface MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O interface feature, which allows MAX 7000 devices to interface with systems that have differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V V CCINT level, input voltage thresholds are at TTL levels, and are therefore compatible with both 3.3-V and 5.0-V inputs. The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V supply, the output levels are compatible with 5.0-V systems. When VCCIO is connected to a 3.3-V supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V incur a nominally greater timing delay of tOD2 instead of tOD1. Open-Drain Output Option (MAX 7000S Devices Only) MAX 7000S devices provide an optional open-drain (functionally equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane.
MAX 7000 Programmable Logic Device Family Data Sheet By using an external 5.0-V pull-up resistor, output pins on MAX 7000S devices can be set to meet 5.0-V CMOS input voltages. When VCCIO is 3.3 V , setting the open drain option will turn off the output pull-up transistor, allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. When VCCIO is 5.0 V , setting the output drain option is not necessary because the pull-up transistor will already turn off when the pin exceeds approximately 3.8 V , allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. Slew-Rate Control The output buffer for each MAX 7000E and MAX 7000S I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. In MAX 7000E devices, when the Turbo Bit is turned off, the slew rate is set for low noise performance. For MAX 7000S devices, each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. Programming with External Hardware MAX 7000 devices can be programmed on Windows-based PCs with the Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device. f For more information, see the Altera Programming Hardware Data Sheet. The Altera development system can use text- or waveform-format test vectors created with the Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 7000 device with the results of simulation. Moreover, Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. f For more information, see the Programming Hardware Manufacturers.
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MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. information) show the location of the JTAG control pins for each device. Table 9. MAX 7000 JTAG Instructions pattern output at the device pins. to adjacent devices during normal device operation. allowing the IDCODE to be serially shifted out of TDO.
information for MAX 7000S devices. EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register. (1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. Table 10. MAX 7000S Boundary-Scan Register Length Table 11. 32-Bit MAX 7000 Device IDCODE Note (1)
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Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms Boundary-Scan Testing in Altera Devices). Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
reset only when the device is reprogrammed. erased during early stages of the production flow. Figure 10. MAX 7000 AC Test Conditions exposing the leads to mechanical stress. & Development Socket Data Sheet. 1 MAX 7000S devices are not shipped in carriers. avoided for accurate measurement. for 3.3-V devices and outputs.
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capacitance for 5.0-V MAX 7000 devices. Table 13. MAX 7000 5.0-V Device Absolute Maximum Ratings Note (1) Table 14. MAX 7000 5.0-V Device Recommended Operating Conditions
Table 15. MAX 7000 5.0-V Device DC Operating Conditions Note (9) Table 16. MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices Note (13) Table 17. MAX 7000 5.0-V Device Capacitance: MAX 7000E Devices Note (13) Table 18. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Note (13)
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(1) See the Operating Requirements for Altera Devices Data Sheet. (3) Numbers in parentheses are for in dustrial-temperature-range devices. (4) V CC must rise monotonically. device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. (6) 3.3-V I/O operation is not available for 44-pin packages. (7) The V CCISP parameter applies only to MAX 7000S devices. (8) During in-system programming, the mi nimum DC input voltage is –0.3 V. (9) These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26. to high-level TTL or CMOS output current. low-level TTL, PCI, or CMOS output current. (13) Capacitance is measured at 25 ° C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF. Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices for a device-wide performance evaluation.
Figure 12. MAX 7000 Timing Model (1) Only available in MAX 7000E and MAX 7000S devices. (2) Not available in 44-pin devices. relationship of internal and external delay parameters.
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Figure 13. Switching Waveforms
Table 19. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
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Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Table 21. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
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Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Table 23. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
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Table 24. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Table 25. MAX 7000 & MAX 7000E External Timing Parameters Note (1)
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Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
information on switching waveforms. (2) This parameter applies to MAX 7000E devices only. parameter applies for both global and array clocking. (5) These parameters are measured with a 16-bit loadable , enabled, up/down counter programmed into each LAB. (6) The fMAX values represent the highest frequency for pipelined data. (7) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. running in the low-power mode. Tables 27 and 28 show the EPM7032S AC operating conditions. Table 27. EPM7032S External Timing Parameters (Part 1 of 2) Note (1)
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Table 28. EPM7032S Internal Timing Parameters Note (1) Table 27. EPM7032S External Timing Parameters (Part 2 of 2) Note (1)
information on switching waveforms. parameter applies for both global and array clocking. (4) These parameters are measured with a 16-bit loadable , enabled, up/down counter programmed into each LAB. (5) The fMAX values represent the highest frequency for pipelined data. (6) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. devices, add an additional 0.1 ns to the PIA timing value. running in the low-power mode. Tables 29 and 30 show the EPM7064S AC operating conditions. Table 29. EPM7064S External Timing Parameters (Part 1 of 2) Note (1)
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Table 30. EPM7064S Internal Timing Parameters (Part 1 of 2) Note (1) Table 29. EPM7064S External Timing Parameters (Part 2 of 2) Note (1)
information on switching waveforms. parameter applies for both global and array clocking. (4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (5) The fMAX values represent the highest frequency for pipelined data. (6) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. devices, add an additional 0.1 ns to the PIA timing value. running in the low-power mode. Table 30. EPM7064S Internal Timing Parameters (Part 2 of 2) Note (1)
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Tables 31 and 32 show the EPM7128S AC operating conditions. Table 31. EPM7128S External Timing Parameters Note (1)
Table 32. EPM7128S Internal Timing Parameters Note (1)
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information on switching waveforms. parameter applies for both global and array clocking. (4) These parameters are measured with a 16-bit loadable , enabled, up/down counter programmed into each LAB. (5) The fMAX values represent the highest frequency for pipelined data. (6) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. devices, add an additional 0.1 ns to the PIA timing value. running in the low-power mode. Tables 33 and 34 show the EPM7160S AC operating conditions. Table 33. EPM7160S External Timing Parameters (Part 1 of 2) Note (1)
Table 34. EPM7160S Internal Timing Parameters (Part 1 of 2) Note (1) Table 33. EPM7160S External Timing Parameters (Part 2 of 2) Note (1)
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information on switching waveforms. parameter applies for both global and array clocking. (4) These parameters are measured with a 16-bit loadable , enabled, up/down counter programmed into each LAB. (5) The fMAX values represent the highest frequency for pipelined data. (6) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. devices, add an additional 0.1 ns to the PIA timing value. running in the low-power mode. Tables 35 and 36 show the EPM7192S AC operating conditions. Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2) Note (1) Table 35. EPM7192S External Timing Parameters (Part 1 of 2) Note (1)
Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2) Note (1) Table 35. EPM7192S External Timing Parameters (Part 2 of 2) Note (1)
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information on switching waveforms. parameter applies for both global and array clocking. (4) These parameters are measured with a 16-bit loadable , enabled, up/down counter programmed into each LAB. (5) The fMAX values represent the highest frequency for pipelined data. (6) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. devices, add an additional 0.1 ns to the PIA timing value. running in the low-power mode. Table 36. EPM7192S Internal Timing Parameters (Part 2 of 2) Note (1)
Tables 37 and 38 show the EPM7256S AC operating conditions. Table 37. EPM7256S External Timing Parameters Note (1)
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Table 38. EPM7256S Internal Timing Parameters Note (1)
MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more information on switching waveforms. (2) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. (3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. (4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (5) The fMAX values represent the highest frequency for pipelined data. (6) Operating conditions: V CCIO = 3.3 V ± 10% for commercial and industrial use. (7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6 , EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (8) The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Power Consumption Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 devices is calculated with the following equation: P = PINT + PIO = ICCINT × VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value, which depends on the switching frequency and the application logic, is calculated with the following equation: ICCINT = A × MCTON + B × (MCDEV – MCTON) + C × MCUSED × fMAX × togLC The parameters in this equation are shown below: MCTON = Number of macrocells with th e Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) MCDEV = Number of macrocells in the device MCUSED = Total number of macrocells in the design, as reported in the MAX+PLUS II Report File (.rpt) fMAX = Highest clock frequency to the device togLC = Average ratio of logic ce lls toggling at each clock (typically 0.125) A, B, C = Constants, shown in Table 39
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the device and the environmental operating conditions. Table 39. MAX 7000 ICC Equation Constants
Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2)
151.5 MHz
60.2 MHz
125 MHz
55.5 MHz
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Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2)
90.9 MHz
43.5 MHz
43.4 MHz
100 MHz
47.6 MHz
Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 1 of 2)
142.9 MHz
58.8 MHz
175.4 MHz
56.5 MHz
147.1 MHz
56.2 MHz
149.3 MHz
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Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2) Library for pin-out information.
125.0 MHz
55.6 MHz
128.2 MHz
Figure 16. 44-Pin Package Pin-Out Diagram Package outlines not drawn to scale. (1) The pin functions shown in parenthesis are on ly available in MAX 7000E and MAX 7000S devices. (2) JTAG ports are available in MAX 7000S devices only.
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Figure 17. 68-Pin Package Pin-Out Diagram Package outlines not drawn to scale. (2) JTAG ports are available in MAX 7000S devices only.
Figure 18. 84-Pin Package Pin-Out Diagram Package outline not drawn to scale. (1) Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices. (2) The pin functions shown in parenthesis are on ly available in MAX 7000E and MAX 7000S devices. (3) JTAG ports are available in MAX 7000S devices only.
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Figure 19. 100-Pin Package Pin-Out Diagram Package outline not drawn to scale. Figure 20. 160-Pin Package Pin-Out Diagram Package outline not drawn to scale.
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MAX 7000 Programmable Logic Device Family Data Sheet Revision History The information contained in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.7 supersedes information published in previous versions. The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.7: Version 6.7 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.7: ■ Reference to AN 88: Using the Jam Language for ISP & ICR via an Embedded Processor has been replaced by AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor. Version 6.6 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.6: ■ Added Tables 6 through 8. ■ Added “Programming Sequence” section on page 17 and “Programming Times” section on page 18. Version 6.5 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5: ■ Updated text on page 16. Version 6.4 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.4: ■ Added Note (5) on page 28. Version 6.3 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.3: ■ Updated the “Open-Drain Output Option (MAX 7000S Devices Only)” section on page 20.
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