MAX-7000A

EPM7256AEFC100-10N ALTERA | Alldatasheet

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September 2003, ver. 4.5 Data Sheet DS-M7000A-4.5 Features... ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX ®) architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system pr ogrammability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device IS P circuitry compatible with IEEE Std. 1532 ■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 ■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 ■ Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) – ISP_Done bit to ensure comple te programming (excluding EPM7128A and EPM7256A devices) – Pull-up resistor on I/O pins during in-system programming ■ Pin-compatible with the popular 5.0-V MAX 7000S devices ■ High-density PLDs ranging from 600 to 10,000 usable gates ■ Extended temperature range f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.

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MAX 7000A Programmable Logic Device Data Sheet ...and More

Features

■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to

227.3 MHz

■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space- saving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages ■ Supports hot-socketing in MAX 7000AE devices ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ PCI-compatible ■ Bus-friendly architecture, including programmable slew-rate control ■ Open-drain output option ■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls ■ Programmable power-up states for macrocell registers in MAX 7000AE devices ■ Programmable power-saving mode for 50% or greater power reduction in each macrocell ■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ 6 to 10 pin- or logic-driven output enable signals ■ Two global clock signals with optional inversion ■ Enhanced interconnect resources for improved routability ■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers ■ Programmable output slew-rate control ■ Programmable ground pins Table 1. MAX 7000A Device Features

MAX 7000A Programmable Logic Device Data Sheet ■ Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with Altera’s Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, ByteBlasterMVTM parallel port download cable, and BitBlasterTM serial download cable, as well as programming hardware from third-party manufacturers and any Jam TM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester General

Description

MAX 7000A (including MAX 7000AE) devices are high-density, high- performance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM- based MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. Table 2. MAX 7000A Speed Grades

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PQFP, and TQFP packages. See Table 3 and Table 4. design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details. Table 3. MAX 7000A Maximum User I/O Pins Note (1) Table 4. MAX 7000A Maximum User I/O Pins Note (1)

MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms, providing up to 32 product terms per macrocell. MAX 7000A devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used in mixed-voltage systems. MAX 7000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet.

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MAX 7000A Programmable Logic Device Data Sheet Functional The MAX 7000A architecture includes the following elements: ■ Logic array blocks (LABs) ■ Macrocells ■ Expander product terms (shareable and parallel) ■ Programmable interconnect array ■ I/O control blocks The MAX 7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices.

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and the programmable register. Figure 2 shows a MAX 7000A macrocell. Figure 2. MAX 7000A Macrocell allocation according to the logic requirements of the design.

36 Signals

16 Expander

MAX 7000A Programmable Logic Device Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ Global clock signal. This mode achieves the fastest clock-to-output performance. ■ Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. ■ Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 7000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE device may be set to either a high or low state. This power-up state is specified at design entry. Upon power-up, each register in EPM7128A and EPM7256A devices are set to a low state. All MAX 7000A I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be clocked to an input D flipflop with an extremely fast (as low as 2.5 ns) input setup time.

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logic resources to obtain the fastest possible speed. can feed multiple macrocells. Figure 3. MAX 7000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB.

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MAX 7000A Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The compiler can allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 × t PEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower- numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest-numbered macrocell can only lend parallel expanders, and the highest-numbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell.

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Figure 4. MAX 7000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. which selects a PIA signal to drive into the LAB.

Figure 5. MAX 7000A PIA Routing performance easy to predict.

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Figure 6. I/O Control Block of MAX 7000A Devices signals. EPM7512AE devices have 10 output enable signals.

count packages form a subset of the higher-ball-count packages. take advantage of this migration (see Figure 7). Figure 7. SameFrame Pin-Out Example

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MAX 7000A Programmable Logic Device Data Sheet In-System Programma- bility MAX 7000A devices can be programmed in-system via an industry- standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient iterations during design development and debugging cycles. The MAX 7000A architecture internally generates the high programming voltages required to program EEPROM cells, allowing in-system programming with only a single 3.3-V power supply. During in-system programming, the I/O pins are tri-stated and weakly pulled-up to eliminate board conflicts. The pull-up value is nominally 50 kΩ. MAX 7000AE devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that provides safe operation when in-system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. This feature is only available in EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices. ISP simplifies the manufacturing flow by allowing devices to be mounted on a PCB with standard pick-and-place equipment before they are programmed. MAX 7000A devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera MasterBlaster serial/USB communications cable, ByteBlasterMV parallel port download cable, and BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling. MAX 7000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. A constant algorithm uses a pre- defined (non-adaptive) programming sequence that does not take advantage of adaptive algorithm programming time improvements. Some in-circuit testers cannot program using an adaptive algorithm. Therefore, a constant algorithm must be used. MAX 7000AE devices can be programmed with either an adaptive or constant (non-adaptive) algorithm. EPM7128A and EPM7256A device can only be programmed with an adaptive algorithm; users programming these two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices. The Jam Standard Test and Programming Language (STAPL), JEDEC standard JESD 71, can be used to program MAX 7000A devices with in- circuit testers, PCs, or embedded processors.

MAX 7000A Programmable Logic Device Data Sheet f For more information on using the Jam STAPL language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor). ISP circuitry in MAX 7000AE devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 7000A device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1m s . 2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. 3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. 4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. 6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1m s .

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MAX 7000A Programmable Logic Device Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ A pulse time to erase, program, or read the EEPROM cells. ■ A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000A Device The time required to program a single MAX 7000A device in-system can be calculated from the following formula: where: tPROG = Programming time tPPULSE = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK =N u m b e r o f TCK cycles to program a device fTCK = TCK frequency The ISP times for a stand-alone verification of a single MAX 7000A device can be calculated from the following formula: where: tVER =V e r i f y t i m e tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK =N u m b e r o f TCK cycles to verify a device tPROG tPPULSE Cycle PTCK fTCK tVER tVPULSE Cycle VTCK fTCK

with the worst-case method using the enhanced ISP algorithm. verification times for several common test clock frequencies. Table 5. MAX 7000A tPULSE & CycleTCK Values Table 6. MAX 7000A In-System Programming Times for Different Test Clock Frequencies

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz

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two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices. electrical contact between the adapter and the device. f For more information, see the Altera Programming Hardware Data Sheet. manufacturers provide programming support for Altera devices. f For more information, see Programming Hardware Manufacturers. MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std. Table 7. MAX 7000A Stand-Alone Verification Times for Different Test Clock Frequencies

Table 8. MAX 7000A JTAG Instructions STAPL File, JBC File, or SVF File via an embedded processor or test equipment.

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electronic signature (UES) register length in MAX 7000A devices is 16 bits. (1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. Devices) for more information on JTAG BST. Table 9. MAX 7000A Boundary-Scan Register Length Table 10. 32-Bit MAX 7000A Device IDCODE Note (1)

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operate at maximum frequency. tEN, tSEXP, tACL, and tCPPW parameters. set for I/O output drivers (VCCIO). always be driven by 2.5-V, 3.3-V, or 5.0-V signals. Table 12 describes the MAX 7000A MultiVolt I/O support. Table 12. MAX 7000A MultiVolt I/O Support

MAX 7000A Programmable Logic Device Data Sheet Open-Drain Output Option MAX 7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. This output can also provide an additional wired-OR plane. Open-drain output pins on MAX 7000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high V IH. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V to meet CMOS VOH requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor. Programmable Ground Pins Each unused I/O pin on MAX 7000A devices may be used as an additional ground pin. In EPM7128A and EPM7256A devices, utilizing unused I/O pins as additional ground pins requires using the associated macrocell. In MAX 7000AE devices, this programmable ground feature does not require the use of the associated macrocell; therefore, the buried macrocell is still available for user logic. Slew-Rate Control The output buffer for each MAX 7000A I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal.

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MAX 7000A Programmable Logic Device Data Sheet Power Sequencing & Hot-Socketing Because MAX 7000A devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The V CCIO and VCCINT power planes can be powered in any order. Signals can be driven into MAX 7000AE devices before and during power- up (and power-down) without damaging the device. Additionally, MAX 7000AE devices do not drive out during power-up. Once operating conditions are reached, MAX 7000AE devices operate as specified by the user. MAX 7000AE device I/O pins will not source or sink more than 300 µA of DC current during power-up. All pins can be driven up to 5.75 V during hot-socketing, except the OE1 and GLCRn pins. The OE1 and GLCRn pins can be driven up to 3.6 V during hot-socketing. After VCCINT and VCCIO reach the recommended operating conditions, these two pins are 5.0-V tolerant. EPM7128A and EPM7256A devices do not support hot-socketing and may drive out during power-up. Design Security All MAX 7000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. Generic Testing MAX 7000A devices are fully tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 9. Test patterns can be used and then erased during early stages of the production flow.

Figure 9. MAX 7000A AC Test Conditions capacitance for MAX 7000A devices. observable noise immunity can result. Table 13. MAX 7000A Device Absolute Maximum Ratings Note (1)

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Table 14. MAX 7000A Device Recommended Operating Conditions

Table 15. MAX 7000A Device DC Operating Conditions Note (6) Table 16. MAX 7000A Device Capacitance Note (12)

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MAX 7000A Programmable Logic Device Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) For EPM7128A and EPM7256A devices only, V CC must rise monotonically. (4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (5) These devices support in-system programming for –40 ° to 100° C. For in-system programming support between –40° and 0° C, contact Altera Applications. (6) These values are specified under the re commended operating conditions shown in Table 14 on page 28. (7) The parameter is measured with 50 % of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. (8) The parameter is measured with 50 % of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL or CMOS output current. (9) This value is specified for normal device operation. For MAX 7000AE devices, the maximum leakage current during power-up is ±300 µA. For EPM7128A and EPM7256A devices, leakage current during power-up is not specified. (10) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system. (11) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. (12) Capacitance is measured at 25 °C and is sample-tested only. The OE1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pF. (13) The POR time for MAX 7000AE devices (except MAX 7128A and MAX 7256A devices) does not exceed 100 µs. The sufficient VCCINT voltage level for POR is 3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level.

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Figure 11. MAX 7000A Timing Model between internal and external delay parameters.

Figure 12. MAX 7000A Switching Waveforms

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Table 17. EPM7032AE External Timing Parameters Note (1)

Table 18. EPM7032AE Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 18. EPM7032AE Internal Timing Parameters (Part 2 of 2) Note (1)

Table 19. EPM7064AE External Timing Parameters Note (1)

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Table 20. EPM7064AE Internal Timing Parameters (Part 1 of 2) Note (1)

Table 20. EPM7064AE Internal Timing Parameters (Part 2 of 2) Note (1)

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Table 21. EPM7128AE External Timing Parameters Note (1)

Table 22. EPM7128AE Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 22. EPM7128AE Internal Timing Parameters (Part 2 of 2) Note (1)

Table 23. EPM7256AE External Timing Parameters Note (1)

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Table 24. EPM7256AE Internal Timing Parameters (Part 1 of 2) Note (1)

Table 24. EPM7256AE Internal Timing Parameters (Part 2 of 2) Note (1)

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Table 25. EPM7512AE External Timing Parameters Note (1)

Table 26. EPM7512AE Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 26. EPM7512AE Internal Timing Parameters (Part 2 of 2) Note (1)

Table 27. EPM7128A External Timing Parameters Note (1)

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Table 28. EPM7128A Internal Timing Parameters (Part 1 of 2) Note (1)

Table 28. EPM7128A Internal Timing Parameters (Part 2 of 2) Note (1)

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Table 29. EPM7256A External Timing Parameters Note (1)

Table 30. EPM7256A Internal Timing Parameters (Part 1 of 2) Note (1)

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Figure 12 for more information on switching waveforms. devices, add an additional 0.1 ns to the PIA timing value. (4) This parameter is measured with a 16-bit loadable , enabled, up/down counter programmed into each LAB. (5) Operating conditions: V CCIO = 2.5 ± 0.2 V for commercial and industrial use. Application Note 74 (Evaluating Power for Altera Devices). Table 30. EPM7256A Internal Timing Parameters (Part 2 of 2) Note (1)

and the environmental operating conditions. Table 31. MAX 7000A ICC Equation Constants

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Figure 13. ICC vs. Frequency for MAX 7000A Devices (Part 1 of 2)

192.3 MHz

108.7 MHz

222.2 MHz

125.0 MHz

144.9 MHz

Figure 13. ICC vs. Frequency for MAX 7000A Devices (Part 2 of 2) Library for pin-out information. Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram Package outlines not drawn to scale.

172.4 MHz

102.0 MHz

116.3 MHz

76.3 MHz

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Figure 15. 49-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outlines not drawn to scale. Figure 16. 84-Pin PLCC Package Pin-Out Diagram Package outline not drawn to scale.

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Figure 19. 144-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Figure 20. 169-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale.

Figure 21. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale.

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Figure 22. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale.

Figure 23. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. ■ Updated text in the “Power Sequencing & Hot-Socketing” section.

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations , and all other words and lo gos that are identified as trademarks and/or se rvice marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera produc ts are protected under numerous U. S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the la test version of device specifications before relying on any published information and before placing orders for products or services

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com MAX 7000A Programmable Logic Device Data Sheet

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Version 4.3 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.3: ■ Added extended temperature devices to document ■ Updated Table 14. Version 4.2 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.2: ■ Removed Note (1) from Table 2. ■ Removed Note (4) from Tables 3 and 4. Version 4.1 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.1: ■ Updated leakage current information in Table 15. ■ Updated Note (9) of Table 15. ■ Updated Note (1) of Tables 17 through 30.