MAX-3000A

EPM3064ATC100-4 ALTERA | Alldatasheet

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227.3 MHz

Table 1. MAX 3000A Device Features

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MAX 3000A Programmable Logic Device Family Data Sheet ...and More

Features

■ PCI compatible ■ Bus–friendly architecture including programmable slew–rate control ■ Open–drain output option ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable power–saving mode for a power reduction of over 50% in each macrocell ■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ Enhanced architectural features, including: – 6 or 10 pin– or logic–dr iven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Programmable output slew–rate control ■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) General

Description

MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.

ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. PLCC, PQFP, and TQFP packages. See Table 3. boundary–scan testing, four I/O pins become JTAG pins. a variety of independent combinatorial and sequential logic functions. programmed and erased up to 100 times. Table 2. MAX 3000A Speed Grades Table 3. MAX 3000A Maximum User I/O Pins Note (1)

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MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high–speed parallel expander product terms to provide up to 32 product terms per macrocell. MAX 3000A devices provide programmable speed/power optimization. Speed–critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non–speed–critical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixed–voltage systems. MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry–standard PC– and UNIX–workstation–based EDA tools. The software runs on Windows–based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Functional The MAX 3000A architecture includes the following elements: ■ Logic array blocks (LABs) ■ Macrocells ■ Expander product terms (shareable and parallel) ■ Programmable interconnect array (PIA) ■ I/O control blocks The MAX 3000A architecture includes four dedicated inputs that can be used as general–purpose inputs or as high–speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 3000A devices.

Figure 1. MAX 3000A Device Block Diagram that is fed by all dedicated input pins, I/O pins, and macrocells.

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programmable register. Figure 2 shows a MAX 3000A macrocell. Figure 2. MAX 3000A Macrocell allocation according to the logic requirements of the design.

36 Signals

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MAX 3000A Programmable Logic Device Family Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ Global clock signal mode, which achieves the fastest clock–to–output performance. ■ Global clock signal enabled by an active–high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock–to–output performance of the global clock. ■ Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 3000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product–term select matrix allocates product terms to control these operations. Although the product–term–driven preset and clear from the register are active high, active–low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active–low dedicated global clear pin (GCLRn). All registers are cleared upon power-up. By default, all registered outputs drive low when the device is powered up. You can set the registered outputs to drive high upon power-up through the Quartus ® II software. Quartus II software uses the NOT Gate Push-Back method, which uses an additional macrocell to set the output high. To set this in the Quartus II software, go to the Assignment Editor and set the Power-Up Level assignment for the register to High.

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fewest possible logic resources to obtain the fastest possible speed. Figure 3. MAX 3000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB.

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MAX 3000A Programmable Logic Device Family Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The Altera development system compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 × tPEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower– numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest–numbered macrocell can only lend parallel expanders and the highest–numbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell.

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Figure 4. MAX 3000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. which selects a PIA signal to drive into the LAB.

Figure 5. MAX 3000A PIA Routing performance easy to predict.

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Figure 6. I/O Control Block of MAX 3000A Devices

MAX 3000A Programmable Logic Device Family Data Sheet In–System Programma- bility MAX 3000A devices can be programmed in–system via an industry– standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system programmability (ISP) offers quick, efficient iterations during design development and debugging cycles. The MAX 3000A architecture internally generates the high programming voltages required to program its EEPROM cells, allowing in–system programming with only a single 3.3–V power supply. During in–system programming, the I/O pins are tri–stated and weakly pulled–up to eliminate board conflicts. The pull–up value is nominally 50 kΩ. MAX 3000A devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that ensures safe operation when in–system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board (PCB) with standard pick–and–place equipment before they are programmed. MAX 3000A devices can be programmed by downloading the information via in–circuit testers, embedded processors, the MasterBlaster communications cable, the ByteBlasterMV parallel port download cable, and the BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high–pin–count packages (e.g., QFP packages) due to device handling. MAX 3000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. The Jam STAPL programming and test language can be used to program MAX 3000A devices with in–circuit testers, PCs, or embedded processors. f For more information on using the Jam STAPL programming and test language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor) and AN 111 (Embedded Programming Using the 8051 and Jam Byte-Code). The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors.

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MAX 3000A Programmable Logic Device Family Data Sheet Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 3000A device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1m s . 2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. 3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. 4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. 6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1m s . Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ A pulse time to erase, program, or read the EEPROM cells. ■ A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device.

MAX 3000A Programmable Logic Device Family Data Sheet By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 3000A Device The time required to program a single MAX 3000A device in-system can be calculated from the following formula: where: tPROG = Programming time tPPULSE = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK = Number of TCK cycles to program a device fTCK = TCK frequency The ISP times for a stand-alone verification of a single MAX 3000A device can be calculated from the following formula: where: tVER =V e r i f y t i m e tVPULSE = Sum of the fixed times to verify the EEPROM cells CycleVTCK = Number of TCK cycles to verify a device tPROG tPPULSE Cycle PTCK fTCK tVER tVPULSE Cycle VTCK fTCK

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with the worst-case method using the enhanced ISP algorithm. verification times for several common test clock frequencies. Table 4. MAX 3000A tPULSE & CycleTCK Values Table 5. MAX 3000A In-System Programming Times for Different Test Clock Frequencies

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz

Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies

Altera Logic Programmer card, MPU, and the appropriate device adapter. contact between the adapter and the device. f For more information, see the Altera Programming Hardware Data Sheet. manufacturers also provide programming support for Altera devices. f For more information, see Programming Hardware Manufacturers. required, the JTAG pins are available as user I/O pins. Table 7. MAX 3000A JTAG Instructions

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(1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. Devices) for more information on JTAG BST. Table 8. MAX 3000A Boundary–Scan Register Length Table 9. 32–Bit MAX 3000A Device IDCODE Value Note (1)

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operate at maximum frequency. tACL, tEN, tCPPW and tSEXP parameters. set for I/O output drivers (VCCIO). always be driven by 2.5–V, 3.3–V, or 5.0–V signals. Table 11 summarizes the MAX 3000A MultiVolt I/O support. Table 11. MAX 3000A MultiVolt I/O Support

MAX 3000A Programmable Logic Device Family Data Sheet Open–Drain Output Option MAX 3000A devices provide an optional open–drain (equivalent to open-collector) output for each I/O pin. This open–drain output enables the device to provide system–level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired–OR plane. Open-drain output pins on MAX 3000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high V IH. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor Slew–Rate Control The output buffer for each MAX 3000A I/O pin has an adjustable output slew rate that can be configured for low–noise or high–speed performance. A faster slew rate provides high–speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low–noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin–by–pin basis. The slew rate control affects both the rising and falling edges of the output signal. Design Security All MAX 3000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. Generic Testing MAX 3000A devices are fully tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 8. Test patterns can be used and then erased during early stages of the production flow.

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Figure 8. MAX 3000A AC Test Conditions capacitance for MAX 3000A devices. observable noise immunity can result. Table 12. MAX 3000A Device Absolute Maximum Ratings Note (1)

Table 13. MAX 3000A Device Recommended Operating Conditions Table 14. MAX 3000A Device DC Operating Conditions Note (4)

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(1) See the Operating Requirements for Altera Devices Data Sheet. 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (4) These values are specified under the reco mmended operating conditions, as shown in Table 13 on page 23. to high–level TTL or CMOS output current. low–level TTL, PCI, or CMOS output current. (8) This pull–up exists while devices are programmed in –system and in unprogrammed devices during power–up. has a maximum capacitance of 20 pF. 3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. and 0° C, contact Altera Applications. Table 15. MAX 3000A Device Capacitance Note (9)

Figure 9. Output Drive Characteristics of MAX 3000A Devices reached, MAX 3000A devices operate as specified by the user.

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analysis for device–wide performance evaluation. Figure 10. MAX 3000A Timing Model between internal and external delay parameters.

Figure 11. MAX 3000A Switching Waveforms

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EPM3256A, and EPM3512A timing information. Table 16. EPM3032A External Timing Parameters Note (1)

Table 17. EPM3032A Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 18. EPM3064A External Timing Parameters Note (1) Table 17. EPM3032A Internal Timing Parameters (Part 2 of 2) Note (1)

Table 19. EPM3064A Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 20. EPM3128A External Timing Parameters Note (1) Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2) Note (1)

Table 21. EPM3128A Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 22. EPM3256A External Timing Parameters Note (1) Table 21. EPM3128A Internal Timing Parameters (Part 2 of 2) Note (1)

Table 23. EPM3256A Internal Timing Parameters (Part 1 of 2) Note (1)

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Table 24. EPM3512A External Timing Parameters Note (1) Table 23. EPM3256A Internal Timing Parameters (Part 2 of 2) Note (1)

Table 25. EPM3512A Internal Timing Parameters (Part 1 of 2) Note (1)

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Figure 11 on page 27 for more information on switching waveforms. devices, add an additional 0.1 ns to the PIA timing value. (4) These parameters are measured with a 16–bit loadable , enabled, up/down counter programmed into each LAB. Table 25. EPM3512A Internal Timing Parameters (Part 2 of 2) Note (1)

Application Note 74 (Evaluating Power for Altera Devices). pattern in the device and the environmental operating conditions. Table 26. MAX 3000A ICC Equation Constants

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Figure 12. ICC vs. Frequency for MAX 3000A Devices

192.3 MHz

108.7 MHz

222.2 MHz

125.0 MHz

144.9 MHz

Figure 13. ICC vs. Frequency for MAX 3000A Devices

172.4 MHz

102.0 MHz

116.3 MHz

76.3 MHz

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Library for pin–out information. Figure 14. 44–Pin PLCC/TQFP Package Pin–Out Diagram Package outlines not drawn to scale.

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Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale.

Figure 18. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. ■ New paragraph added before “Expander Product Terms”.

Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations , and all other words and lo gos that are identified as trademarks and/or se rvice marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected un der numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the la test version of device specifications before relying on any published information and before placing orders for products or services

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San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com MAX 3000A Programmable Logic Device Family Data Sheet

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Version 3.3 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.3: ■ Updated Tables 3, 13, and 26. ■ Added Tables 4 through 6. ■ Updated Figures 12 and 13. ■ Added “Programming Sequence” on page 14 and “Programming Times” on page 14 Version 3.2 The following change were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.2: ■ Updated the EPM3512 ICC versus frequency graph in Figure 13. Version 3.1 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.1: ■ Updated timing information in Table 1 for the EPM3256A device. ■ Updated Note (10) of Table 15. Version 3.0 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.0: ■ Added EPM3512A device. ■ Updated Tables 2 and 3.