MA5332MS INFINEON | Alldatasheet
Document overview
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Technical content
Features
2 channel analog input Class D audio amplifier in a small 7x7mm package Very low RDS(ON) at 24.4 mΩ typical, enabling heatsink-less operation at 2x100W at 4Ω 95% efficiency Class D at 2x200W at 4Ω Split or single power supply capable Differential or single-ended input Multiple configuration options: 2xSE, BTL, PSE (Parallel Single-Ended) Over-current, over-temperature and under-voltage protections with self-reset feature Start/stop click noise reduction Clip and Fault reporting outputs PG- IQFN-42
Applications
Multi-channel home theatre system Studio monitor Active speaker Soundbar subwoofer Marine amplifier Aftermarket car audio system General-purpose audio power amplifier Product validation Qualified for standard applications according to the relevant tests of J-STD-020 and JESD22. Product type Package MA5332MS 7x7mm PG- IQFN-42
Description
The MA5332MS offers the same or higher output power than monolithic alternatives without heatsink and 50% less footprint. This MCM (multi-chip module) solution integrates 2 channel PWM controller, high voltage gate driver, and 4 low RDS(ON) MOSFETs. Like its predecessor, IR43x2M, it includes standard Class D protection features for reliable operation over various environmental conditions. As a powerful upgrade to IR43x2M and other monolithic solutions, MA5332MS’ 7x7 mm PG- IQFN-42 package showcases the benefit of small footprint, high power density, and heatsink-less operation. Topology Half-bridge / Full bridge MA5332MS Output power (Half- bridge,THD+N=10%, typical)
150 W in 2 Ω / 300 W in 4 Ω
200 W in 4 Ω / 400 W in 8 Ω
160 W in 6 Ω
*Residual noise (AES-17, IHF-A, typical) 250 μVrms *THD+N (1kHz, 70W, 4 Ω, typical) 0.01 % * In a typical application Total Harmonic Distortion
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1 Qualification information
Qualification Level (1) Standard (2) Qualified for standard applications according to the relevant tests of J-STD-020 and JESD22 Moisture Sensitivity Level (MSL) (3) MSL3 (per IPC/JEDEC J-STD-020) ESD Charge Device Model Class C2a (per JEDEC standard JS-002) Human Body Model Class 1B (per JEDEC standard JS-001) IC Latch-Up Test Class I, Level A (per JESD78) RoHS Compliant Yes Note: 1. Qualification standards can be found at Infineon’s web site http://www.infineon.com/ 2. Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. 3. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information.
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2 Device Comparison Table
MA5332MS 200W (4 Ω)*2 channel integrated analog input Class D audio Amplifier IR4302M 130W (4 Ω)*2 channel integrated analog input Class D audio Amplifier IR4322M 100W (2 Ω)*2 channel integrated analog input Class D audio Amplifier IR4312M 35W (4 Ω)*2 channel integrated analog input Class D audio Amplifier IR4301M 160W (4 Ω) single-channel integrated analog input Class D audio Amplifier IR4321M 135W (2 Ω) single-channel integrated analog input Class D audio Amplifier IR4311M 35W (4 Ω) single-channel integrated analog input Class D audio Amplifier
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3 Pin Configuration
3.1 Lead assignments
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3.2 Lead definitions
Pin # Symbol Description
1 CLIP Clipping detection output, open drain, referenced to GND
2 COMP2 CH2 PWM comparator input
3 IN-2 CH2 Analog inverting input
4 IN+2 CH2 Analog non-inverting input
5 GND GND for internal shunt zener diodes to VAA and VSS, a reference to FAULT and CLIP
outputs.
6 VSS Floating input negative supply
7 VAA Floating input positive supply
8 IN+1 CH1 Analog non-inverting input
9 IN-1 CH1 Analog inverting input
10 COMP1 CH1 PWM comparator input
11 CSD Shutdown timing capacitor / shutdown input
12 FAULT Fault reporting output, open drain, referenced to GND
13 VCC Low side supply
14 COM Low side supply return, internally connected to pin 27
15 CSH1 CH1 High side over current sensing input, referenced to VS1
16 VB1 CH1 High side floating supply
17 VS1 CH1 PWM output, internally connected to pin 19
18 VP1 CH1 Positive power supply
19 VS1 CH1 PWM output
20 VN1 CH1 Negative power supply, connect to COM externally
21 VN2 CH2 Negative power supply, connect to COM externally
22 VS2 CH2 PWM output, internally connected to pin 24
23 VP2 CH2 Positive power supply
24 VS2 CH2 PWM output
25 VB2 CH2 High side floating supply
26 CSH2 CH2 High side over current sensing input, referenced to VS2
27 COM Low side supply return, internally connected to pin 14
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4 Specifications
4.1 Absolute maximum ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM=VN1=VN2; all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min Max Units VPn Positive power supply rail voltage, n=1-2 - 100 VBn High side floating supply voltage -0.3 115 VSn High side floating supply voltage(2), n=1-2 VBn -15 V Bn +0.3 VCSHn CSH pin input voltage, n=1-2 VSn -0.3 V Bn +0.3 VCC Low side supply voltage(2) -0.3 15 VAA Floating input positive supply voltage(2) -0.3 110 VSS Floating input negative supply voltage(2) -1 (See ISSZ) GND +0.3 VIN+n Floating input supply ground voltage , n=1-2 V SS -0.3 V AA +0.3 IINn Input current between IN- and IN+ pins(1), n=1-2 - ±3 mA VCSD CSD pin input voltage VSS -0.3 V AA +0.3 V VCOMPn COMP pin input voltage, n=1-2 VSS -0.3 V AA +0.3 VCLIP CLIP pin input voltage GND -0.3 V AA +0.3 ICLIP CLIP pin sinking current - 5 mA VFAULT FAULT pin input voltage GND -0.3 V AA +0.3 V IFAULT FAULT pin sinking current - 5 mA IAAZ Floating input supply zener clamp current(2) - 20 ISSZ Floating input negative supply zener clamp current(2) - 20 ICCZ Low side supply zener clamp current(2) - 20 IBSZn Floating supply zener clamp current(2), n=1-2 - 20 dVSn/dt Allowable Vs voltage slew rate, n=1-2 - 50 V/ns dVSS/dt Allowable Vss voltage slew rate(3) - 50 V/ms Id@ 25ºC Continuous output current, from VPn to VSn, VSn to VNn, VCC=10V, VBn-VSn=10V - 16 A Id@ 100ºC Continuous output current, from VPn to VSn, VSn to VNn, VCC=10V, VBn-VSn=10V - 10 IDM Pulsed output current, from VPn to VSn, VSn to VNn, V CC=10V, VBn-VSn=10V(5) - 64 Pd Power dissipation(4)@ TC = 25C - 25 W RthJC Thermal resistance, junction to case(4) - 5 C/W TJIC Control IC junction temperature - 150 TJFET FET junction temperature - 150
Datasheet 9 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents TS Storage Temperature -55 150 TL Lead temperature (Soldering, 10 seconds) - 300 Note: 1. IN- and IN+ contain clamping diodes between the two pins. 2. VAA -VSS, Vcc-COM and VBn-VSn contain internal shunt zener diodes. Note that the voltage ratings of these can be limited by the clamping current. 3. For the rising and falling edges of step signal of 10V. Vss=15V to 100V. 4. Per MOSFET. 5. Repetitive rating, pulse width limited by maximum junction temperature.
4.2 Recommended operating conditions
For proper operation, the device should be used within the recommended conditions below. The Vss and Vsn offset ratings are tested with supplies biased at COM=VN1=VN2, VAA-VSS=9.6V, VCC=12V and VBn-VSn=12V. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. Symbol Definition Min Max Units VPn Positive power supply voltage, n=1-2, without heatsink MA5332MS - 60 Positive power supply voltage, n=1-2, with heatsink MA5332MS - 80 V VBn High side floating supply absolute voltage, n=1-2 VSn +10 VSn +14 VSn High side floating supply offset voltage, n=1-2 MA5332MS (6) 100 VAA Floating input positive supply voltage(7) VSS +9.0 VSS + 9.8 VSS Floating input negative supply voltage(7) MA5332MS 0 100 IAAZ Floating input supply zener clamp current(7) 1 15 mA ISSZ Floating input negative supply zener clamp current(7) 1 15 VCC Low side fixed supply voltage 10 15 V VIC IN- and IN+ pins common mode input voltage VSS + 2 VAA - 2 VIN-n Inverting input voltage, n=1-2 VIN+ -0.5 VIN+ +0.5 VCSD CSD pin input voltage VSS VAA VCOMPn COMP pin input voltage, n=1-2 VSS VAA CCOMPn COMP pin phase compensation capacitor to GND , n=1-2 1 - nF VCSHn CSH pin input voltage, n=1-2 VSn VBn V fSW Switching frequency - 500 kHz TJ_IC Juction temperature of controller IC -40 100 C Note: 6. Logic operational for Vs equal to –5V to +100V. Logic state held for Vs equal to –5V to –V BS. 7. GND input voltage is limited by IAAZ and ISSZ.
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4.3 Electrical characteristics
Unless otherwise specified, the following apply: VCC,VBS= 12 V VSS=VS1=VS2=VN1=VN2=COM=0V VAA=9.6V TA=25C Table 2 Electrical characteristics Symbol Definition Min Typ Max Units Test conditions Low-side supply UVCC+ Vcc supply UVLO positive threshold 8.4 8.9 9.4 V UVCC- Vcc supply UVLO negative threshold 8.2 8.7 9.2 V UVCCHYS UV CC hysteresis - 0.2 - V IQCC Low side quiescent current - - 3 mA ICC Low side supply current - 10 - mA f=400kHz VCLAMPLn Low side zener diode clamp voltage, n=1-2 14.7 15.3 16.2 V I CC=5mA High-side floating supply UVBS+n High side well UVLO positive threshold, n=1-2 8.0 8.5 9.0 V UVBS-n High side well UVLO negative threshold, n=1-2 7.8 8.3 8.8 V UVBSHYSn UV BS hysteresis, n=1-2 - 0.2 - V IQBSn High side quiescent current, n=1-2 - - 2.4 mA IQBSn_OFF-CSH High side quiescent current, with CSH pin open n=1-2 350 500 650 uA VCLAMPHn High side zener diode clamp voltage, n=1-2 14.7 15.3 16.2 V I BS=5mA Floating input supply UVAA+ VA+, VA- floating supply UVLO positive threshold from VSS 8.2 8.7 9.2 V VSS =0V, GND pin floating UVAA- VA+, VA- floating supply UVLO negative threshold from VSS 7.7 8.2 8.7 V VSS =0V, GND pin floating UVAAHYS UV AA hysteresis - 0.5 - V VSS =0V, GND pin floating IQAA0 Floating Input positive quiescent supply current - 1.5 3 mA VAA=9.6V, VSS =0V, VCSD =VSS IQAA1 Floating Input positive quiescent supply current - 4 6 mA VAA=9.6V, VSS =0V, VCSD =VAA
Datasheet 11 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents IQAA2 Floating Input positive quiescent supply current - 5 7.5 mA VAA=9.6V, VSS =0V, VCSD =GND ILKM Floating input side to Low side leakage current - - 50 µA VAA=VSS=VGND= 100V VCLAMPM+ VAA floating supply zener diode clamp voltage, positive, with respect to GND 4.9 5.1 5.4 V IAA=5mA, ISS=5mA, VGND=0V, VCSD =VSS VCLAMPM- VSS floating supply zener diode clamp voltage, negative, with respect to GND -5.4 -5.1 -4.9 V IAA=5mA, ISS=5mA, VGND=0V, VCSD =VSS Audio input (VGND=0, VAA=4.8V, VSS=-4.8V) VOSn Input offset voltage, n=1-2 -18 0 18 mV IBINn Input bias current, n=1-2 - - 40 nA GBWn Small signal bandwidth in OTA, n=1- 2 - 9 - MHz C COMP=1nF, Rf=0 gmn OTA transconductance, n=1-2 - 10 - mS VIN+=0V, VIN- =10mV GVn OTA gain, n=1-2 50 - - dB VNrmsn CHn OTA input noise voltage, n=1-2 - 200 330 mVrms PWM VthPWM PWM comparator threshold in COMP - (VAA - VSS)/2 - V fOTAn COMP pin star-up local oscillation frequency, n=1-2 0.7 1.0 1.5 MHz V CSD =GND Ton_n COMP to VS rising edge propagation delay, n=1-2 - 370 - ns Toff_n COMP to VS trailing edge propagation delay, n=1-2 - 320 - ns DTn Deadtime: Low-side turn-off to High-side turn-on (DTLO-HO) & High- side turn-off to Low-side turn-on (DTHO-LO) , n=1-2 - 50 - ns VP=30V, VN=-30V, Power MOSFET (FET1, FET2, FET3, FET4) At Tj=25°C, unless otherwise specified V(BR)DSS (8) Drain-to-Source breakdown voltage 100 - - V VGS=0V, ID=250uA RDS(ON) FET on resistance - 24.4 30.5 mΩ ID=3.3A, VGS=10V Qg Total gate charge - 12.7 19 nC VGS=10V ILK0 VP leakage current, VS=VN - - 20 µA VP=100V(8), VCSD =VSS Protection
Datasheet 12 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents IOCPn Over current detection Positive threshold, n=1-2(8) - 40 - A IOCNn Over current detection Negative threshold, n=1-2(9) - -40 - A Vth1 CSD pin shutdown release threshold 0.62xVAA 0.70xV AA 0.78xV AA V Vth2 CSD pin self-reset threshold 0.26xV AA 0.30xV AA 0.34xV AA V ICSD+ CSD pin discharge current 70 100 130 µA VCSD = VSS +4.8V ICSD- CSD pin charge current 70 100 130 µA VCSD = VSS +4.8V tSDn Shutdown propagation delay from VS < Vth1 to Shutdown, n=1-2 - - 250 ns COMP = VSS tOCPn CHn propagation delay time from IOn > IOCPn to Shutdown, n=1-2 - - 500 ns COMP = VSS tOCNn CHn propagation delay time from IOn < IOCNn to Shutdown, n=1-2 - - 500 ns COMP = VSS Vth+CLIP Clip detection positive threshold in COMP 0.85xVAA 0.90xV AA 0.95xV AA V Vth-CLIP Clip detection negative threshold in COMP 0.05xVAA 0.10xV AA 0.15xV AA V tCLIP Clipping detection propagation delay - 40 - ns tCLIPmin Clipping detection minimum output duration - 3 - us TSD Over-temperature shutdown threshold in controller IC 100 - - ºC TSDHYS Over-temperature shutdown threshold hysteresis - 7 - ºC
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4.4 Audio characteristics (SE)
Parameter Test conditions Typ Unit Po Power output per channel(10) RL= 6Ω, 10%THD+N, Vbus = ± 40 V 160 W RL= 4Ω, 10%THD+N, Vbus = ± 36.5 V 200 RL= 3Ω, 10%THD+N, Vbus = ± 31.5 V 190 RL= 2Ω, 10%THD+N, Vbus = ± 23 V 150 RL= 6Ω, 1%THD+N, Vbus = ± 40 V 120 RL= 4Ω, 1%THD+N, Vbus = ± 36.5 V 150 RL= 3Ω, 1%THD+N, Vbus = ± 31.5 V 140 RL= 2Ω, 1%THD+N, Vbus = ± 23V 110 Residual noise(AES-17, IHF-A, typical) EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω 250 uV Idling supply current EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω +55 mA -80 Efficiency(11) EVAL_AUDAMP25, Vbus = ± 36.5 V, Pout=200W, RL= 4Ω 95 % Note: 8. Vp changes over temperature at a rate of 50mV/K compared to Tj=25°C. 9. Over-current protection threshold measured under Tj=25°C condition. 10. Tested with heatsink (digikey part number: V8818V) 11. Class D stage only
4.5 Audio characteristics (BTL)
Parameter Test conditions Typ Unit Po Power output per channel(9) RL= 8Ω, 10%THD+N, Vbus = ± 36.5 V 400 W RL= 6Ω, 10%THD+N, Vbus = ± 31.5 V 380 RL= 4Ω, 10%THD+N, Vbus = ± 23 V 300 RL= 8Ω, 1%THD+N, Vbus = ± 36.5 V 300 RL= 6Ω, 1%THD+N, Vbus = ± 31.5 V 280 RL= 4Ω, 1%THD+N, Vbus = ± 23V 220 Residual noise(AES-17, IHF-A, typical) EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω 350 uV Idling supply current EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 8Ω +55 mA -80 Efficiency(10) EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 8Ω 95 %
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4.6 Audio characteristics (PSE)
Parameter Test conditions Typ Unit Po Power output per channel(9) RL= 2Ω, 10%THD+N, Vbus = ± 36.5 V 400 W RL= 2Ω, 1%THD+N, Vbus = ± 36.5V 300 Residual noise(AES-17, IHF-A, typical) EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω 250 uV Idling supply current EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω +55 mA -80 Efficiency(10) EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω 95 %
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4.7 Typical Audio characteristics (SE)
Test conditions: All Measurements taken at Sine wave frequency= 1 kHz, AES17+ AUX-0025 measurement filters. Vbus = ± 40 V, Load impedance = 6 Ω, FPWM = 400 kHz Vbus = ± 36.5 V, Load impedance = 4 Ω, FPWM = 400 kHz Vbus = ± 31.5 V, Load impedance = 3 Ω, FPWM = 400 kHz Vbus = ± 23 V, Load impedance = 2 Ω, FPWM = 400 kHz 4.7.1 Power vs. THD+N Figure 2 Power vs. THD+N 0.001 0.01 0.1 0.01 0.1 1 10 100 1000 THD+N(%) Outpower(W) 2ohm 3ohm 4ohm 6ohm
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4.7.3 Frequency response
Test conditions: Output power = 1 W, LPF = 22uH+0.47uF Figure 4 Frequency response 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) 2ohm 3ohm 4ohm 6ohm -10 20 200 2000 20000 200000dBr A Frequency(Hz) 2ohm 3ohm 4ohm 6ohm
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4.7.4 Noise floor
4.7.5 Efficiency
Figure 6 Efficiency 4 Ω load -150 -130 -110 -90 -70 -50 -30 -10 10 100 1000 10000 dBV Frequency(Hz) 2ohm 3ohm 4ohm 6ohm 0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 70.0% 80.0% 90.0% 100.0% Efficiency Power (W) MA5332 4ohm load MA5332 4ohm load
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4.8 Typical Audio characteristics (BTL)
Test conditions: All Measurements taken at Sine wave frequency= 1 kHz, AES17+ AUX-0025 measurement filters. Vbus = ± 40 V, Load impedance = 8 Ω, FPWM = 400 kHz Vbus = ± 31.5 V, Load impedance = 6 Ω, FPWM = 400 kHz Vbus = ± 23 V, Load impedance = 4 Ω, FPWM = 400 kHz 4.8.1 Power vs. THD+N Figure 7 Power vs. THD+N 0.001 0.01 0.1 0.01 0.1 1 10 100 1000 THD+N(%) Outpower(W) 4ohm 6ohm 8ohm
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4.8.3 Frequency response
Test conditions: Output power = 1 W, fixed LPF 22uH+0.47uF Figure 9 Frequency response 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) 4ohm 6ohm 8ohm -10 20 200 2000 20000 200000dBr A Frequency(Hz) 4ohm 6ohm 8ohm
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4.8.4 Noise floor
Test conditions: No input signal Figure 10 Noise floor -150 -130 -110 -90 -70 -50 -30 -10 10 100 1000 10000 dBV Frequency(Hz) 4ohm 6ohm 8ohm
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4.9 Typical Audio characteristics (PSE)
Test conditions: All Measurements taken at Sine wave frequency= 1 kHz, AES17+ AUX-0025 measurement filters. Vbus = ± 36.5 V, Load impedance = 2 Ω, FPWM = 400 kHz 4.9.1 Power vs. THD+N Figure 11 Power vs. THD+N 0.001 0.01 0.1 0.01 0.1 1 10 100 1000 THD+N(%) Outpower(W) 2ohm
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4.9.3 Frequency response
Test conditions: Output power = 1 W, fixed LPF 22uH+0.47uF Figure 13 Frequency response 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) 2ohm -10 20 200 2000 20000 200000dBr A Frequency(Hz) 2ohm
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4.9.4 Noise floor
Test conditions: No input signal Figure 14 Noise floor -150 -130 -110 -90 -70 -50 -30 -10 10 100 1000 10000 dBV Frequency(Hz) 2ohm
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5 Thermal information
Benefits from unique co-packaging technique and superior MOSFET technology, MA5332MS has the best-in-class thermal performance, Peak power duration. It can deliver 100W*2/4Ω even without a heatsink.
5.1 Peak power duration thermal information
Test conditions: All Measurements are taken at sinewave frequency= 1 kHz, AES17+ AUX-0025 measurement filters. Input signal = 1 kHz, FPWM = 400 kHz. Tests are based on Eval_AUDAMP25 board when both channels are driven. Table 6 Peak power with heatsink Load (Ω) ±Vbus (V) 10 percent THD+N power (W) Duration 6 40 160 More than 1 minute without thermal shutdown 4 36.5 200 3 31.5 190 2 23 150 Figure 15 Peak power Pout = 164 W with 6 Ω load ±40 V Note: Maximum temperature 68.9°C at 1 minute.
Datasheet 27 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents Figure 20 Peak power Pout = 55 W with 2 Ω load ±13.7 V Note: Maximum temperature 142.8°C at 1 minute. Table 8 1/8 power test with heatsink Load (Ω) ±Vbus (V) Max. T-case (°C) 1/8 power (W) Duration (minutes) 6 40 71.6 16.5 30 4 36.5 85.6 19.8 30 3 31.5 87.2 19.7 30 2 23 84.8 15 30 Table 9 1/8 power test without heatsink Load (Ω) ±Vbus (V) Max. T-case (°C) 1/8 power (W) Duration (minutes) 4 22.7 84.6 7.12 30 2 13.7 76.1 4.88 30
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5.2 Heatsink information
Heatsink: V8818V Thermal pad: BER161-ND Figure 21 Heatsink installation
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6 Functional block diagram
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7 Typical Implementation
The MA5332MS can be designed as single-ended, BTL or parallel single ended (PSE) output configuration, using a single or split power supply. Here are examples of typical configurations. A configuration for single-ended input with split power supply sets the base example. The front end section refers to GND which is common to speaker output GND. Speaker CH1 OUTPUT CH2 OUTPUT CH2 INPUT EXT CLK (OPTIONAL) VCC Speaker VAA IN-2 COMP2 CSD FAULT COM VN2 VS2 VCC VS1 VN1 CSH1 VB1 VS1 VP1 CSH2 VB2 VS2 VP2 COM CLIP IN+2 COMP1 IN-1 IN+1 VSS GND CH1 INPUT Figure 23 Inverting amplifier with Split Power Supply Speaker CH1 OUTPUT CH2 OUTPUT EXT CLK (OPTIONAL) VCC Speaker VAA IN-2 COMP2 CSD FAULT COM VN2 VS2 VCC VS1 VN1 CSH1 VB1 VS1 VP1 CSH2 VB2 VS2 VP2 COM CLIP IN+2 COMP1 IN-1 IN+1 VSS GND CH1 IN- CH2 IN+ CH2 IN- CH1 IN+ Figure 24 Differential amplifier with Split Power Supply
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8 Input / Output pin equivalent circuit diagrams
Figure 29 Input/output pin equivalent circuit diagrams
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9 PWM Modulator Design
The open-access front-end configuration of MA5332MS enables many ways to implement a PWM modulator. This section explains how PWM modulation works based on an example of a self-oscillating PWM modulator in a typical application. Figure 30 MA5332MS Typical Control Loop Design
9.1 Input Section
The audio input stage of MA5332MS forms an inverting error amplifier. The voltage gai n of the amplifier, G V, is determined by the ratio between input resistor RIN and feedback resistor RFB. IN FB V R RG Since the feedback resistor R FB is part of an integrator time constant, which determines switching frequency, changing the overall voltage gain by RIN is simpler and therefore recommended. Note that the input impedance of the amplifier is equal to the input resistor RIN. A DC blocking capacitor C3 should be connected in series with RIN to minimize the DC offset voltage on the output. Due to potential distortion, a ceramic capacitor is not recommended. Minimizing the DC offset is essential to minimize the audible noise during power-ON and -OFF. The connection of the non-inverting input IN+ is a reference for the error amplifier, and thu s is crucial for audio performance. Connect IN+ to the signal reference ground in the system, which has the same potential as the negative terminal of the speaker output.
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9.2 Control Loop Design
The MA5332MS allows the user to choose from numerous methods of PWM modulator implementations. In this section, all the explanations are based on a typical application circuit of a self-oscillating
9.3 PWM Frequency
Choosing the switching frequency entails making a trade-off between many aspects. At lower switching frequency, conduction losses in the MOSFET stage increases due to higher inductor ripple current. The output carrier leakage in the speaker output increases. At higher switching frequency, the efficiency degrades due to higher switching losses. Higher switching frequency supports wider audio bandwidth. The inductor ripple decreases yet core loss might increase. For these reasons, 400kHz is chosen for a typical design example. Self-oscillating frequency has little influence from the bus voltage and input resistance RIN. Note that the nature of a self-oscillating PWM is for the switching frequency to decrease as PWM modulation deviates from idling. Table 10 summarizes suggested values of components for a given target self-oscillating frequency. The front- end operational transconductance amplifier (OTA) output has limited voltage and current compliances. This set of component values ensures that OTA operates within its linear region for optimal THD+N performance. In case the target frequency is somewhere in between the frequencies listed in Table 10, simply adjust the frequency by tweaking R1. Table 10 External Component Values vs. Self-Oscillation Frequency Target Self-Oscillation Frequency (kHz) C1=C2 (nF) R1 (ohms) 500 2.2 200 450 2.2 165 400 2.2 141 350 2.2 124 300 2.2 115 250 2.2 102 200 4.7 41.2 150 10 20.0 100 10 14.0 70 22 4.42
Datasheet 36 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents
9.4 Clock Synchronization
In the PWM control loop design example, the self-oscillating frequency can be set and synchronized to an external clock. Through a set of resistors and a capacitor, the external clock inje cts periodic pulsating charges into the integrator, forcing oscillation to lock up to the external clock frequency. A typ ical setup with 5 Vp-p 50% duty clock signal uses R CK=22 kΩ and C CK=100 pF in Figure 31. To maximize audio performance, the self-running frequency without clock injection should be 20 to 30% higher than the external clock frequency. Figure 31 External Clock Synchronization Figure 32 shows how a self-oscillating frequency locks up to an external clock frequency. A design of a 400 kHz self-oscillating frequency synchronizes to an external clock whose frequency is within the red border lines. Figure 32 Typical Lock Range to External Clock (RCK=22 kΩ and CCK=100 pF) 100 200 300 400 500 600 Duty Cycle Operating Frequency (kHz)
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9.5 Click Noise Elimination
The MA5332MS has a unique feature that minimizes power-ON and -OFF audible cli ck noise. When CSD is in between Vth1 and Vth2 during start-up, an internal closed loop around the OTA enables an oscillation that generates voltages at COMP and IN-, bringing them to steady-state values. It runs at around 1 MHz, independent from the switching oscillation. Figure 33 Audible Click Noise Elimination As a result, all capacitive components connected to COMP and IN- pins, such a s C1, C2, C3 and Cc in Figure 33, are pre-charged to their steady-state values during the start-up sequence. This allows instant settling of closed- loop PWM operation. To utilize the click noise reduction function, the following conditions must be met. 1. CSD pin has slow enough ramp up from Vth1 to Vth2 such that the voltages in the capacitors can settle to their target values. 2. High-side bootstrap power supply needs to be charged up prior to starting oscillation. 3. Audio input has to be zero. 4. For internal local loop to override external feedback during the startup period, DC offset at speaker output prior to shutdown release has to satisfy the following condition.
Datasheet 38 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents
9.6 Differential Input
Figure 34 shows an example of a differential input configuration. This desi gn is useful in a single supply configuration. Use RIN1=RIN2, RFB1=RFB2, C3=C4. Voltage gain is given by a ratio between RIN and RFB. IN FB V R RG Figure 34 Differential Input Although component values in the feedback network are balanced between inverting and non-inverting inputs, the integration capacitor path in the non-inverting input creates unbalance at high frequencies, causing slightly higher distortion compared to an unbalanced input configuration. To impro ve the THD degradations, place optional RC network R2=R1 and C5=C1.
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10 Operational Mode
The CSD pin determines the operational mode of the MA5332MS as shown in Figure 35. T he OTA has three operational modes: shutdown, pop-less startup and normal operation; while the gate driver section has two modes: shutdown and normal operation. When VCSD < Vth2, the IC is in shutdown mode and the input OTA is cut off. When Vth2< V CSD < Vth1, the output MOSFETs are still in shutdown mode. The OTA is activated and starts local oscillation for pop-less start-up which pre-biases all the capacitive components in the error amplifier. When V CSD>Vth1, the MA5332MS enters normal operation mode and PWM operation starts. Figure 35 VCSD and Operational Mode
10.1 Self-oscillation Start-up Condition
The MA5332MS requires the following conditions in order for pop-less startup to work properly. - All the control power supplies, VAA, VSS, VCC and VBS are above the under-voltage lockout thresholds. - CSD pin voltage is over Vth1 threshold. FBIN ii Where IN IN IN R Vi , FB B FB R Vi . - The duration CSD voltage transitioning from Vth2 to Vth1 is long enough to pre-charge i nput and integration capacitors around OTA section.
Datasheet 40 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents
11 Protections
Figure 36 Protection Functional Block Diagram The internal protection control block dictates the operational modes, normal or shutdown, using the input of the CSD pin. In shutdown mode, the controller IC turns off internal power MOSFETs. The CSD pin provides five functions. 1. Power up delay timer 2. Self-reset timer 3. Shutdown input 4. Latched protection configuration 5. Shutdown status output (host I/F) The CSD pin cannot be paralleled with another MA5332MS directly. The operating statuses of the protection features are shown in Table 11.
Datasheet 41 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Table of contents Table 11 Events and Actions of CSD and FAULT *CSD recycle: CSD pin voltage discharges down to Vth2 and charges back to VAA, if CSD pin is configured as self reset protection.
11.1.1 Self-Reset Protection
Attaching a capacitor between CSD and VSS configures the MA5332MS self-reset protection mode. Upon an OCP event, the CSD pin discharges the external capacitor voltage V CSD down to the lower threshold V th2 to reset the internal shutdown latch. Then, the CSD pin begins to charge the external capacitor, Ct, in an attempt to resume operation. Once the voltage of the CSD pin rises above the upper threshold, Vth1, the IC resumes normal operation. Figure 37 Self-Reset Protection Configuration Event CSD FAULT UVCC, rising edge Recycle L until CSD>Vth1 UVCC, falling edge n/a n/a UVAA, rising edge n/a L at VAA<UVAA UVAA, falling edge n/a L at VAA<UVAA UVBS, rising edge n/a n/a UVBS, falling edge n/a n/a Over Current Protection Keep recycling until OCP is reset Held L until OCP is reset Clip Detection n/a n/a Over Temperature Protection Keep recycling until OTP is reset Held L until OTP is reset
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11.1.2 Designing Ct
The external timing capacitor, Ct, programs self-reset timings: tRESET and tSU. tRESET is the time that elapses from when the IC enters the shutdown mode to the time wh en the IC resumes operation. tRESET should be long enough to avoid over heating the MOSFETs from the repetitive sequence of shutting down and resuming operation during over-current conditions. In most applications, the minimum recommended time for tRESET is 0.1 seconds. tSU is the time between powering up the IC in shutdown mode to the moment the IC releases shut down to begin normal operation. The Ct determines tRESET and tSU as following equations: CSD AA RESET I VCtt 1 . 1 [s] CSD AA SU I VCtt 7 . 0 [s] where I CSD: the charge/discharge current at the CSD pin VAA: the floating input supply voltage with respect to VSS.
11.1.3 Shutdown Input
During normal operation, pulling the CSD pin below the upper threshold Vth1 forces the IC into shutdown mode. Figure 38 shows how to add an external discharging path to shutdown the PWM. Figure 38 Shutdown Input
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11.1.4 Latched Protection
Connecting CSD to V AA through a 10 kΩ or less resistor configures latched protection mode. Th e internal shutdown latch stays in shutdown mode after the overcurrent is detected. An external reset switc h brings CSD below the lower threshold Vth2 for a minimum of 200 ns and resets the latch. At first p ower-up, a reset signal to the CSD pin is required to release the IC from shutdown mode. Figure 39 Latched Protection with Reset Input
11.1.5 Interfacing with System Controller
The MA5332MS can communicate with an external system controller through a simple interfacing circuit shown in Figure 40. A generic PNP transistor, U1, detects the sink current at the CSD pin during protection event and outputs a shutdown flag signal to an external system controller. Another generic NPN trans istor, U2, can then reset the internal protection logic by pulling the CSD voltage below the lower thresho ld Vth2. After the first power-up sequence, a reset signal to the CSD pin is required to release the IC from shutdown mode. Figure 40 Interfacing CSD with System Controller
Datasheet 44 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Protections
11.2 Over Current Protection (OCP)
The MA5332MS features over current protection to protect the internal power MOSFETs duri ng abnormal load conditions. The control logic diagrams are in Figure 41. As soon as either the high-side or low-side current sensing block detects over current, the following sequence will occur. 1. The shutdown latch flips its logic states from normal operational mode to shutdown mode. 2. Low-side and high-side MOSFETs go into an off state condition. 3. The CSD pin starts discharging the external capacitor Ct. 4. When voltage across Ct falls below the lower threshold Vth2, COMP2 resets the shutdown latch to normal mode. 5. The CSD pin starts charging the external capacitor Ct. 6. When V CSD goes above the upper threshold Vth1, the logic on COMP1 toggles and the IC res umes operation. Figure 41 summarizes the above. As long as the over current condition e xists, the IC will repeat the over current protection sequence at a repetitive rate set by the CSD capacitor. Figure 41 Overcurrent Protection Timing Chart
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11.3 Over Temperature Protection (OTP)
If the junction temperature TJ of the controller IC exceeds the on-chip thermal shutdown threshold, T SD, the on- chip over temperature protection shuts down the PWM.
11.4 Under Voltage Protection (UVP)
In order to prevent a partial on-state of the internal MOSFET, under-voltage protection monitors the low side and high side gate bias supplies, VCC and VB. When VCC is below UVLO, both high and low si de MOSFETs are turned off. When the high side supply V BS is below the UVLO threshold, the high side output is disabled, while the low side works normally.
Datasheet 46 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Status Output
12 Status Output
12.1 Fault Output
FAULT output is an open drain output referenced to GND to report whether the MA5332MS is in shutdown mode or in normal operating mode. If the FAULT pin is open, the MA5332MS is in normal operation mode, i.e. the output MOSFETs are active. The following conditions trigger shutdown internally and pulls the FAULT pin down to GND. Over Current Protection Over Temperature Protection Shutdown mode from CSD pin voltage Figure 42 Fault Output
Datasheet 47 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Status Output
12.2 CLIP Output
When the output of the amplifier loses track of an expected target value, the amplifier enters into clipping condition. The CLIP detection block monitors the COMP pin voltage with a window comparator. The CLIP pin is pulled to GND when a clipping condition is detected. The detection thresholds in the COMP pin are at 10% and 90% of VAA-VSS. The CLIP outputs are disabled in shutdown mode. OTA VAA VSS IN+ IN- CLIP1 COMP PGEN VAA VSS R R R PWM GND SD Figure 43 CLIP Detection
Datasheet 48 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Power Supply Design
13 Power Supply Design
13.1 Supplying VAA and VSS
VAA and VSS are supply voltages to the front-end of the analog section, hence are noise sensitive. For best audio performance, use regulated power supplies for VAA and VSS. 7805 7905 VAA GND VSS MA53xx 2.2µF 2.2µF Figure 44 Supplying VAA and VSS with External Voltage Regulators When switched-mode regulators are used as supply voltages for VAA and VSS, place a two-stage R-C noise filter in the supply lines as shown in Figure 45. 10µF 10µF 2.2µF 2.2µF +5V -5V VAA GND VSS MA53xx Figure 45 Supplying VAA and VSS from Switched Mode Power Supply
13.2 Supplying VCC and VB
Figure 46 shows the recommended power supply configuration for gate driver power supplies. The gate driver stage has three power supply inputs: 1. VCC-COM: low side gate drive supply 2. VB1-VS1: CH1 high side gate drive supply 3. VB2-VS2: CH2 high side gate drive supply The low-side power supply, VCC, feeds the internal gate drive logic and low side gate driver. In order to protect VCC from switching noise generated by the VS node, it is recommended to insert a few ohms of RVBS in the bootstrap charging path. The high-side driver requires a floating supply VBn referenced to the respective switching node VSn where the source of the output MOSFET is connected. A charge pump method (floating bootstrap power supply) eliminates the need for a floating power supply and thus is used in the typical application circuit. The floating bootstrap power supply charges the bootstrap capacitor CBS from the low-side power supply VCC during the low-side MOSFET ON period. When the high-side MOSFET is ON, the diode cuts off and floats the VBS supply. CBS retains its VB supply voltage for the rest of the high-side ON duration.
Datasheet 49 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Power Supply Design PWMGQBSQCCVCC fQIII 2 /per channel Recommend to have minimum 20% design margin for Ivcc. VCC VAA IN-2 COMP2 CSD FAULT COM VN2 VS2 VCC VS1 VN1 CSH1 VB1 VS1 VP1 CSH2 VB2 VS2 VP2 COM CLIP IN+2 COMP1 IN-1 IN+1 VSS GND Vbus CBP 100nF RVP N1 4.7 RVP N2 4.7 CVCC 1uF CVB S1 10uF CVB S2 10uF Figure 46 Recommended Power Supply Configurations for Output Stage
13.2.1 Choosing Bootstrap Capacitance
Often MA5332MS uses hard clipping condition. The continuous high-side ON duration could continue as long as half of the lowest audio frequency, tens of milliseconds. A typical application uses a 22 uF C BS to support low audio frequency clipping. A ceramic capacitor (X7R, X5R or X5S type) or aluminum electrolytic capacitor with 25 V or higher voltage rating is recommended.
13.2.2 Choosing Bootstrap Diode
Use a bootstrap charging diode with voltage rating of 1.5 x the maximum bus voltage. In order to charge the bootstrap capacitor in a very short low-side ON period with a high PWM modulation ratio, a fast recovery diode type (trr<50ns) is recommended.
13.2.3 Charging VBS Prior to Start
For proper start-up, pre-charging the bootstrap supply VBS prior to PWM start-up is necessary for self-oscillating PWM modulator topologies. A charging resistor, RCHARGE, inserted between the positive supply bus and VB, charges CBS prior to switching start as shown in Figure 47. The minimum resistance of RCHARGE is limited by the maximum PWM modulation index of the system. When the high-side MOSFET is on, RCHARGE drains the bootstrap power supply together with the quiescent current, IQBS, so it reduces the holding time, resulting in maximum continuous high-side on time. The maximum resistance of RCHARGE is limited by the current charge capability of the resistor during startup.
Datasheet 50 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Power Supply Design Pre-charging current flows into the speaker load. In order to startup without the load connected, a dummy load Rdummy in parallel with the speaker output provides a pre-charging current path. Figure 47 Bootstrap Supply Pre-Charging
Datasheet 51 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Power Supply Design
13.3 Power Supply Sequence
The protection control block in the MA5332MS monitors the status of V AA and V CC to ensure that both voltage supplies are above their respective UVLO (under voltage lockout) thresholds before starting normal operation. If either VAA or VCC is below the under voltage threshold, the output MOSFETs are disabled in shutdown mode until both VAA and VCC rise above their voltage thresholds. As soon as VAA or VCC falls below its UVLO threshold, protection logic in the MA5332MS turns off high-side and low-side. Figure 48 MA5332MS UVLO Timing Chart
Datasheet 52 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Package details Figure 49 Package details
Datasheet 53 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Package details Figure 50 Package details; Bottom metallization detail view
Datasheet 54 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Package details Figure 51 Dimension table
Datasheet 55 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Board mounting, part marking, and ordering information
15 Board mounting, part marking, and ordering information
Reliability of products in the PQFN package is subject to the board mounting process. The Soldering process is critical. Refer to Application Note AN-1170 Audio IC Board Mounting Application Note for specific footprint design and soldering methods. Device outline Figure 52 shows the outline for these devices. The relative pad positions are controlled to an accuracy of ±0.050mm. For full dimensions and tolerances of each device, and to find out its size and outline, refer to the relevant product data sheet and package outline drawing. Figure 52 42-lead 7x7 device outline
Datasheet 59 of 59 V 2.0 9/24/2021 Integrated Class D Amplifier MA5332MS Board mounting, part marking, and ordering information
Ordering information
Base part number Package type Standard pack Complete part number Form Quantity MA5332MS 7x7mm PG- IQFN-42 Tape and Reel 3000 MA5332MS
100VIntegratedClassDAmplifier MA5332MS Rev.2.0,2021-09-25 RevisionHistory MA5332MS Revision:2021-09-25,Rev.2.0 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2021-09-25 Release of final version Trademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2020InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics (“Beschaffenheitsgarantie”). Withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Inaddition,anyinformationgiveninthisdocumentissubjecttocustomer’scompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomer’sproductsandanyuseofthe productofInfineonTechnologiesincustomer’sapplications. Thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.Itistheresponsibilityofcustomer’s technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered.