MA12040

MA12040 INFINEON | Alldatasheet

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level Switching Technology level and 5 level modulation Low EMI emission Filterless amplification Digital Power Management Algorithm High Power Efficiency (PMP <100 mW I dle p ower d issipation ( 18V PVDD, all chan nels s witching) % Efficiency at 1W power (1kHz sine, 8 Ω % Efficiency at Full Power (1kHz sine , 8 Ω Audio Performance (PMP2) >107dB DNR (A w, rel. to 1% THD+N power level) 55µV output integrated noise (A 0.003% THD+N at high output levels th Order Feedback Error Control High suppression o f supply disturbance HD audio quality Supply Voltages: +4V to +18 V (PVDD) and (A/DVDD) Selectable Gain (20dB/26dB) 2×4 peak output power (18V PVDD, R L = 4Ω 10% THD+N level) 20W continuous output power (RL = 8Ω at 18V, PMP4, 10% THD+N level, without heatsink) 2.0, 2.1, 4.0, 1.0 Output Stage Configurations Protection Under voltage lockout Over temperature warning/error Short circuit/overload protection Power stage pin to pin short circ uit Er ror reporting through serial interface (I2C) DC protec tion I2C control (four selectable addresses) Heatsink free operation with EPAD down package Package pin QFN Package with exposed thermal pad (EPAD) Lead free Soldering

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Ordering Information

Description

, EPAD down (exposed thermal pad on bottom side) Known Issues and Limitations Please refer to the “MA12040 / MA12040P Known Issues and Limitations” document for descriptions of issues and limitations relating to device operation and performance.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Typical Application Block Diagram EPAD PVS S PVDD AVSS AVDD µF PVDD 470 µF µF µF CGD P CGD N µF CMSE C REF VDD µF µF µF CGD P CGD N µF CFDCP CFDCN DVSS DVDD VDD µF µF CDC Analog power and reference voltages Charge pump power supplies VGDC µF CFGDP CFGDN n F OUT A OUT B EMC filter depending on application IN A µF Audio In IN B µF Power amp LP filter Bypass PVDD PVSS CF AN CF AP µF CF BN CF BP µF LP filter Bypass IN A µF IN B µF LP filter Bypass LP filter Bypass OUT A OUT B CF AN CF AP µF CF BN CF BP µF Control and protection MUTE ENABLE MSEL MSEL AD SCL SDA AD CLIP ERROR Clock management Audio In Temp sensor Host system CLKM S CLKIO Power amp PVDD PVS S Power amp PVDD PVSS Power amp PVDD PVS S C in C in C in C in Channel configuration Power management C FGD C GD C GD C FDC C DC C GD C C F A C F B C F A C F B Figure Typical application block diagram

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Pin Description 4.1 Pinout MA12040 QFN A V D D C M S E A V S S C R E F I N A I N B I N A I N B A V S S D V S S S C L A D A D S D A C L K M S C L K N C C F G D N C F G D P C G D N C G D P D V S S C F D C N C F D C P C D C D V D D V G D C C G D P C G D N M S E L M S E L N C Figure Pinout MA12040QFN

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 4.2 Pin Function Table Pin No. Name Type P Power ground for internal power amplifiers PVSS P Power ground for internal power amplifiers CF0AN P Connect to external flying capacitor negative terminal for amplifier channel 0A OUT0A O Audio power output 0A OUT0A O Audio power output 0A CF0AP P Connect to external flying capacitor positive terminal for amplifier channel 0A PVDD P Power supply for internal power amplifiers PVDD P Power supply for internal power amplifiers CF0BP P Connect to external flying capacitor positive terminal for amplifier channel 0B OUT0B O Audio power output 0B OUT0B O Audio power output 0B CF0BN P Connect to external flying capacitor negative terminal for amplifier channel 0B PVSS P Power ground for internal power amplifiers PVSS P Power ground for internal power amplifiers /CLIP O Audio clipping indicator (open drain output), pulled low when clipping occurs /ERROR O Error indicator (open drain output), pulled low when an error occurs AVDD P Power supply for internal analog circuitry CMSE O Decoupling pin for internally generated common mode voltage in SE configuration. Should be externally decoupled to AVSS AVSS P Ground for internal analog circuitry CREF O Decoupling pin for internally generated analog reference voltage. Should be externally decoupled to AVSS. IN0A I Analog audio input 0A IN0B I Analog audio input 0B IN1A I Analog audio input 1A IN1B I Analog audio input 1B AVSS P Ground for internal analog circuitry DVSS P Ground for internal digital circuitry SCL IO I2C bus serial clock AD0 I I2C device address select 0 (see “ MCU/Serial control interface ” section AD1 I I2C devic e address select 1 (see “ MCU/Serial control interface ” section SDA IO I2C bus serial data CLKM/S I Clock master/slave mode select. When pulled low the device is in clock slave mode. When pulled high the device is in master mode. CLKIO IO Clock input when in clock slave mode (CLKM/S is pulled low) or clock output when in master mode (CLKM/S is pulled high) /ENABLE I When pulled high, the device is reset and kept in an inactive state with minimum power consumption. /MUTE I Mute audio output when pulled low PVSS P Power ground for internal power amplifiers PVSS P Power ground for internal power amplifiers CF1BN P Connect to external flying capacitor negative terminal for amplifier channel 1B OUT1B O Audio power output 1B OUT1B O Audio power output 1B

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Pin No. Name Type P Connect to external flying capacitor positive terminal for amplifier channel 1B PVDD P Power supply for power amplifiers PVDD P Power supply for power amplifiers CF1AP P Connect to external flying capacitor positive terminal for amplifier channel 1A OUT1A O Audio power output 1A OUT1A O Audio power output 1A CF1AN P Connect to external flying capacitor negative terminal for amplifier channel 1A PVSS P Power ground for internal power amplifiers PVSS P Power ground for internal power amplifiers NC P Internally connected to DVDD MSEL1 I SE/BTL/PBTL configuration select 1 MSEL0 I SE/BTL/PBTL configuration select 0 CGD1N P Connect to external decoupling capacitor negative terminal for internal gate driver power supply 1 CGD1P P Connect to external decoupling capacitor positive terminal for internal gate driver power supply 1 VGDC P Internally generated virtual ground voltage for digital core. Should be decoupled to DVDD. DVDD P Power supply for internal digital circuitry and charge pumps CDC P Connect to external decoupling capacitor for digital core internal power supply CFDCP P Connect to external flying capacitor positive terminal for internal digital core power supply CFDCN P Connect to external flying capacitor negative terminal for internal digital core power supply DVSS P Power ground for internal digital circuitry CGD0P P Connect to external decoupling capacitor positive terminal for internal gate driver power supply 0 CGD0N P Connect to external decoupling capacitor negative terminal for internal gate driver power supply 0 CFGDP P Connect to external flying capacitor negative terminal for internal gate driver power supplies CFGDN P Connect to external flying capacitor positive terminal for internal gate driver power supplies NC P Internally connected to DVDD Type P = Power; I = Input; O = Output; IO = Input/Output

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Absolute Maximum Ratings Table Parameter Value Unit Power Supplies Power stage supply voltage, PVDD 0.5 to V System supply voltage, DVDD, AVDD 0.5 to 6.0 V Input / Output Analog: IN0A, IN0B, IN1A, IN1B 0.5 to 6.0 V Logic: /ENABLE, /MUTE, /ERROR, /CLIP, MSEL0, MSEL1 0.5 to 6.0 V Clock: CLKIO, CLKM/S 0.5 to 6.0 V Interface: SCL, SDA, AD0, AD1 0.5 to 6.0 V Output current, Logic and Interface mA Thermal Conditions A mbient temperature range, T A 40 to C Junction temperature range, T J to C Storage temperature range to C Thermal resistance, Junction to Ambient C/W Thermal resistance, Junction to EPAD C/W Lead soldering temperature, 10s 300 C Electrostatic Discharge (ESD) Human body model (HBM) V Charged device model (CDM) 1000 V PLEASE NOTE Device u s age beyond the above stated ratings may cause permanent damage to the device Permanent us age at the above stated ratings may limit device lifetime and result in reduced reliability This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. See “Recommended Operation Conditions” for continuous functional ratin gs

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Recommended Operating Conditions Table Symbol Parameter Min Typ Max Unit PVDD Power Stage Power Supply V DVDD Digital Power Supply V AVDD Analog Power Supply V V IH High Level for Logic, Clock, Interface V V IL Low Level for Logic, Clock, Interface 0.8 V V IN_dc DC Offset Level for Analog Inputs 1.2 2.5 3.8 V V IN_ac Audio Signal Level for Analog Inputs 1.8 Vpp R L (BTL) Minimum Load in Bridge Tied Load Mode 3.2 Ω R L (PBTL) Minimum Load in Parallel Bridge Tied Load Mode 1.6 Ω R L (SE) Minimum Load in Single Ended Mode 2.4 Ω L Leq Minimum required equivalent load inductance per output pin for short circuit protection 0.5 µH T A Ambient temperature range +85 C Note: Minimum Load resistance was measured in Filterless output condition.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Electrical and Audio Characteristics Table Power Mode Profile = 0; VDD (Analog & Digital) = +5V; PVDD = +18V; T A = 0°C to +85°C. Typical values are at T A = +25° C Symbol Parameter Conditions Min Typ Max Unit P OUT (BTL) Output Power per channel peak Without Heatsink, see Note 1 THD+N = 10%, RL = 8 Ω, f = 1kHz W THD+N = 10%, RL = 4 Ω, f = 1kHz W THD+N = 1%, RL = 8 Ω, f = 1kHz W THD+N = 1%, RL = 4 Ω, f = 1kHz W Output Power per channel continuous ) Without Heatsink, see Note RL = 8 Ω, f = 1kHz , PVDD = +18V W RL = 4 Ω, f = 1kHz , PVDD = +13V W P OUT (PBTL) Output Power ( peak see Note 1 THD+N = 10%, RL = 2 Ω, f = 1kHz W THD+N = 1%, RL = 2 Ω, f= 1kHz W P OUT (SE) Output Power per channel peak see Note 1 THD+N = 10%, RL = 4 Ω, f = 1kHz W THD+N = 10%, RL = 3 f = 1kHz W THD+N = 1%, RL = 4 Ω, f = 1kHz W THD+N = 1%, RL = 3 Ω, f = 1kHz W T ENABLE Shutdown/Full Operation Timing NENABLE = 1 ms T MUTE Mute/Unmute Timing NMUTE = 1 0 and 0 0.3 ms R IN Input Impedance per output channel High gain mode k Ω Low gain mode k Ω V OS Output Offset Voltage Low gain ±60 mV PSRR Power Supply Rejection Ratio ± 100mVpp ripple voltage dB CMRR Common Mode Rejection Ratio 1kHz common mode input dB R on Resistance, switch on 0.10 0.1 0.20 Ω f SW Power MOSFET Switching Frequency see Note Power Mode A 618 672 726 kHz Power Mode B & C 316 336 356 kHz Power Mode D 158 168 178 kHz f CLK_IO Clock Output Frequency 2.7151 2.822 2.9296 MHz A V Gain Low gain 19.6 dB High gain 25.3 dB I OUT Maximum Output Current A X Talk Crosstalk BTL, POUT = 1 f=1kHz, Ch1 & 2 110 dB

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Note 1: The thermal design of the target application will significantly impact the ability to achieve the peak output power levels for extended time. See “Thermal Characteristics and Test Signals” section for thermal optimization recommendations. Note C ontinuo us power measurements were performed on the MA12040/MA12040P proprietary Amplifier EVK without heatsinking at 25 C ambient temperature in Power Mode Profile 4 Note Power MOSFET switching frequency depends on which properties are assigned to the individual power modes of the device. Detail ed information on this can be found in “Power Mode Management” section Table VDD (Analog & Digital) = +5V ; PVDD = +18V; Typical values are at T A = +25° C ; Output Configuration: BTL Symbol Parameter Conditions Min Typ Max Unit η Efficiency POUT 20W, 8 Ω , PMP = 0 POUT 20W , 8 Ω , PMP = 1 POUT 20W , 8 Ω , PMP = 2 POUT 20W , 8 Ω , PMP = 4 POUT , 4 Ω , PMP = 0 POUT , 4 Ω , PMP = 1 POUT , 4 Ω , PMP = 2 POUT , 4 Ω , PMP = 4

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Table Power Mode Profile = 0; VDD (Analog & Digital) = +5V; PVDD = +18V; T A = 0°C to +85°C. Typical values are at T A = +25°C Symbol Parameter Conditions Min Typ Max Unit I shutdown Current Consumption, PVDD Shutdown µA I idle,mute Current Consumption, PVDD Idle, mute 5.5 mA I idle,unmute Current Consumption, PVDD Idle, unmute, inputs grounded mA I AVDD+D VDD Current Consumption, A VDD+ D VDD Idle, unmute, inputs grounded mA THD+N Total Harmonic Distortion + Noise 1kHz, POUT = 1W, RL = 4 Ω 0.008 1kHz, POUT = 20W, RL = 4 Ω 0.010 DNR Dynamic Range 20kHz, A weighted, Gain = low 105 dB 20kHz, A weighted, Gain = high 102 dB V noise Output integrated noise level 20kHz, A weighted, Gain = low 110 µVrms 20kHz, A weighted, Gain = high 120 µV rms Table Power Mode Profile = 2; VDD (Analog & Digital) = +5V; PVDD = +18V; T A = 0°C to +85°C. Typical values are at T A = +25°C Symbol Parameter Conditions Min Typ Max Unit I shutdown Current Consumption, PVDD Shutdown µA I idle,mute Current Consumption, PVDD Idle, mute 5.5 mA I idle,unmute Current Consumption, PVDD Idle, unmute, inputs grounded mA I AVDD+D VDD Current Consumption, AVDD+D VDD Idle, unmute, inputs grounded mA THD+N Total Harmonic Distortion + Noise kHz, POUT = 1W, RL = 4 Ω 0.004 kHz, POUT = 2 W, RL = 4 Ω 0.003 DNR Dynamic Range 20kHz, A weighted, Gain = low 107 dB 20kHz, A weighted, Gain = high 103 dB V noise Output integrated n oise l evel 20kHz, A weighted, Gain = low µV rms 20kHz, A weighted, Gain = high 105 µV rms Dynamic Range Output power at THD+N < 1% reference to noise floor at 60dBFS signal NOTE : M A12040 gives user s the freedom to choose P ower M ode Profiles (PM P independently As noted in the specifications table, t he cho ice in power mode profiles gives a trade of f between power efficiency and audio p erformance as an individual set of performance characteristics See “Power Mode Profiles” section for more details.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Functional description Multi level modulation The power stage of the MA12040 is a true multi level switching topology . Each half bridge is capable of delivering a PWM output with three voltage levels, rather than the conventional two. The three level half bridges are each driven with a two phase PWM signal, so that the switching frequency seen at the PWM output is twice that of the individual power MOSFET switching frequency. For very low EMI in BTL configuration, the two half bridges are operated in a complementary fashion i.e with 180 phase shift) , which removes common mode PWM output content. This configuration is ideal for dr iving long speaker cables with out an output filter. Differentially, this modulation method drives the filter/load assembly with three PWM levels. For reduced power loss in the BTL configuration, the half bridges can also be driven in a quadrature phase shi fted fashion i.e with ⁰ phase shift It provides five PWM levels at the load , along with a quadrupling of MOSFET switching frequency with respect to the differential PWM switching frequency. With this modulation scheme, the MOSFET switching frequency can therefore be lowered, in order to decrease switching losses. The five level modulation scheme produce s a common mode voltage on the load wires, but with less high frequency content compared to conventional two level BD modulation The multi level switc hing topology of the MA12040 make s filterless operation viable, since the modulation scheme s ensure little or no idle losses i n the speaker mag netic system. For applications with stringent EMC requirements or long speaker cables, the MA12040 can operate wi th a very small and inexpensive EMI/EMC output filter. This can be enabled by multiple PWM output levels and the frequency multiplication seen on the PWM switching nodes. Notably, with the multi level modulation of the MA12040 , there is no tradeoff between idle power loss and inductor cost/size, which is due to the absence of inductor ripple current under idle conditions in all configuration s . Due to the high filter cutoff frequency, non linearities of LC components have less impact on audio performance tha n with a conventional amplifier Therefore, the MA12040 can operate with inexpensive iron powder cored inductors and ceramic (X7R) filter capacitors with no signifi cant audio performance penalty Very low power consumption The MA12040 achieve s very low power loss under idle and near idle operating conditions . This is due to the zero idle ripple property of the multi level PWM scheme, in combination with the programmable automatic reduction of switching frequency at low modulation index levels result ing in a state of the art power efficiency at low and medium output power levels. For high output power levels, power efficiency is determined primarily by the on resistance (Rds on of the output power MOSFETs. With music and music like (e.g. pink noise) output signals with high c re st factor, the reduced near idle losses of the MA12040 contribute to reducing power losses compared to a conve n tional amplifier with the same Rds on . In most applications, this allows the MA12040 to run at high power level s with out a heatsink. Power Mode M anagement T he MA12040 is equipped with an intelligent power management algorithm which applies automatic power mode selection during audio playback. In this state, the amplifier will seamlessly transition between three dif ferent power modes depending on the audio level in order to achieve optimal performance in terms of power l oss, audio performance and EMI These transitions will not give rise to any audible artifacts. Figure shows an illustration of the basic power mode management. Alternatively, it is possible to manually select the desired power mode for the MA12040 via the serial interface. In both manual and automatic power mode selection , the power mode can be configured and set on the fly during audio playback, with no audible artifacts. This makes it possible to optimize the target application to achieve the best possible operating performance at all audio power levels. During automatic power mode selection , the MA12040 can transition between power modes at programmable audio level thresholds. The thresholds can be set via the serial control interface, by addressing the associate d register s

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Low to moderate Medium High Max Power mode change Audio level Power mode change Power mode Figure Illustration of automa tic power mode selection ranges To allow easy use of the power mode management, “Power Mode Profiles” have been defined. The “Power Mode Profiles” address the appropriate power modes for a varie ty of applications. Power Modes Profiles The MA12040 provides different power mode profiles for operating t he internal power amplifiers. The power mode profiles give the user freedom to choose optimal settings of the amplifier for the intended application. The available power modes profiles are referred to as 1, 2, 3 and and can be set by programming the according register (see Register Map . The power mode profi le selection affect s various parameters such as switching frequency modulation scheme and loop gain thus providing flexibility in design tradeoffs such as audio performance, power loss and EMI. The details of each power mode profiles are described in Tab le 8 Table Power Mode Profile characteristics Property Profile 0 Profile 1 Profile 2 Profile 3 Profile 4 PM switch seq. D ↔D↔C B ↔B↔B B ↔B↔A D ↔B↔A D ↔D↔D Idle loss Very low Low Low Very low Very low Full scale efficiency Good Good Good Normal Best THD+N Good Best Best Good/Best Good Common mode content, idle Only DC Only DC Only DC Only DC Only DC Common mode content, full scale audio Only DC DC + Sidebands around 660kHz, 1.98MHz, 3.3MHz Only DC Only DC DC + sidebands around 330kHz, 990kHz, 1.65MHz Differential content low to mid power Audio + sidebands around multiples of 1.2MHz Audio + sidebands around multiples of 1.32MHz Audio + sidebands around multiples of 1.32MHz Audio + sidebands around multiples of 660kHz Audio + sidebands around multiples of 660kHz Differential content mid to high power Audio + sidebands around multiples of 600kHz Audio + sidebands around multiples of 1.32MHz Audio + sidebands around multiples of 1.32MHz Audio + sideba nds around multiples of 1.32MHz Audio + sidebands around multiples of 660kHz Application Filterfree: optimized efficiency, default

applications

Filterfree: optimized audio performance, active speaker Filterfree: optimized audio performance, default LC filter: high efficiency, high audio performance, good EMI, low ripple loss Filterfree: optimized efficiency, active speaker Note: There is a programmable “Profile ” which allows the user to set up a custom profile. The first row of Table shows that each Power Mode Profile follows a certain Power Mode transition sequence. This means that each Power Mode within every Power Mod e Profile will have its specific set of properties (A,B,C or D). The exact details of each assigned set of properties is reflected in Table

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Table Set of properties assigned to Power Modes in the selectable Power Mode Profiles Property A B C D FET switching frequency, f FET 660kHz 330kHz 330kHz 165kHz Modulation scheme level level level level Switching frequency seen at load, f SW 1.32MHz (2 x f FET 1.32MHz (4 x f FET 660kHz (2 x f FET 660kHz (4 x f FET Idle loss Reduced Low Low Very low Full scale efficiency Normal Good Good Best Open loop gain High High Low Low THD+N Best Best Good Good Common mode content, idle Only DC Only DC Only DC Only DC Common mode content, full scale audio Only DC DC + sidebands around 660kHz, 1.98MHz, 3.3MHz Only DC DC + sidebands around 330kHz, 990kHz, 1.65MHz Differential content Audio + sidebands around multiples of 1.32MHz Audio + sidebands around multiples of 1.32MHz Audio + sidebands around multiples of 660kHz Audio + sidebands around multiples of 660kHz Next to the pre defined Power Mode Profiles it is also possible to define a custom profile which will be avail able under Power Mode Profile This profile can be configured using the “custom power mode profile” register (address 30) See “Register Map” section for more details. The MA12040 employs feedback of the output PWM signals in order to compensate for noi se and other non idealities in the power processing path. A fourth order analog feedback loop is used, which t ypically provides a loop gain of 6 0dB to suppress errors in the audio band. For the typical high efficiency application t his results in low THD (Total Harmonic Distortion) at all audio frequencies, as well as exc ellent immunity (in excess of 80 dB) to power supply borne interferences. See also PSRR in Table Maximum achievable loop gain is typically set by the PWM frequency stability criteria. Inherent frequency multiplication of the multilevel topology therefore allows for a much more aggressive loop filter (and therefore better THD and noi se properties) because of a higher effective PWM switching frequency seen at the output. See “Pro file 1 and Profile 2 ” in Table for high fidelity P ower Mode Profiles. For the lowest switching frequencies, the proprietary loop filter architecture seamlessly reduces feedback bandwidth to ensure loop stability. In most applications (e.g. filterless applications), no further special attention is requi red to ensure loop stability. In applications with very stringent EMI requirements, an LC filter can be used. In these cases attention to loop stability is required since an un damped LC filter effectively represents a short circuit to ground at the resonance frequency. In extreme cases, this can cause instability of the analog feedback loops. In order to avoid this, an LC filter should use an inductor with more than 10m Ω DC resistance, and a series R C circuit should be use d to limit the Q of the LC circuit to around 5. Power supplies The MA12040 generates internal supply voltages and uses external capacitors for this purpose and for decoupling.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Gate driver supplies The MA12040 utilizes a floating supply voltage for the gate driver circuitry generated internally by a charge pump. The gate driver on power supply voltage is approximately V to 9V higher than PVDD. Table 8 shows the required external charge pump and decoupling capacitors. Table Gate driver supply capacitors Name Purpose Connection Type Value C GD0 Decoupling of gate driver supply voltage CGD0P, CGD0N 16V, high capacity, low precision 1uF C GD1 Decoupling of gate driver supply voltage 1 CGD1P, CGD1N 16V, high capacity, low precision 1uF C FGD Charge pump f lying capacitor CFGDP, CFGDN V, high capacity, low precision 00n F Digital core supply The digital control unit in the MA12040 uses a supply voltage generated internally by a charge pump and a voltage regulator for highest efficiency. Table 8 lists the e xte rnal capacitors required and describes their function and connection. Table Digital supply capacitors Name Purpose Connection Type Value C DC C harge pump output voltage decoupling to GND CDC , GND >=6.3V, high capacity, low precision 1uF C FDC Charge pump flying capacitor CFDCP, CFDCN >=6.3V, high capacity, low precision u F C GDC Decoupling of digital core virtual ground voltage on the VGDC pin The voltage on the VGDC pin is approximately 1.8V below DVDD, i.e. about 3.2V VGDC, DVDD >=6.3V, high capacity, low precision 1uF Flying capacitors The MA12040 power stage uses flying capacitor s to generate a ½PVDD supply voltage to enable multi level operation Each output switch node OUTXX ha s a corresponding flying capacitor with a positive and a negative terminal, CFXX P and CFXX The two flying capacitor terminals are to be considered high power switch ing nodes carrying voltage s and current s similar to that on the OUTXX nodes. Care must be taken in the PCB design to reduce both the inductance and the resistance of these nodes Table lists the flying capacitors, incl. connection, type and value. Table Flying capacitors Name Purpose Connection Type Value C F0A Half bridge 0A flying capacitor CF0AP CF0AN V, high capacity, low precision 10uF C F0B Half bridge 0B flying capacitor CF0BP CF0BN >=25 V, high capacity, low precision 10uF C F1A Half bridge 1A flying capacitor CF1AP CF1AN >=25 V, high capacity, low precision 10uF C F1B Half bridge 1B flying capacitor CF1BP CF1BN >=25 V, high capacity, low precision 10uF Care must be taken when choosing flying capacitors in applications where maximum output power is needed. The effective capacitance of poor ceramic capacitors can be greatly reduced when a DC bias voltage is applied. A recommended part is the GRM21BZ71E106K E15L capacitor from Murata . Other parts may also be used as long as the effective capacitance is minimum 3.0 µF at 0.5*PVDD voltage.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Protection The MA12040 integrates a range of protection Protection features include Current protection on OUTXX nodes during operation Pin to pin low impedance detect ion on OUTXX CFXX P and CFXXN switching nodes . Prevents the device from starting to switch into a shorted output. On chip temperature sensor for protection against device over heating. Undervoltage supply monitors on AVDD, DVDD, VGDC and PVDD DC protection, preventing DC to be present on the amplifier outputs. Over c urrent protection on OUTXX nodes During switching operation the output stage monitor s the forward current flow in all output switches that are turned on. This is done to limit the maximum power dissipated in the switches and prevent damage to the device and the speaker load. The current in the output stage can exceed unwanted levels if: The speaker load impedance drops to a low value while the device is powered from a high PVDD supply A failure occurs on the speaker terminals causing a low impedance short. The speaker is damaged and thereby exhibiting a low impedance Over cur rent protection and short circuit protection use a latching mechanism. If an over current or a short circuit condition occurs, it will shut down the power stage and report the error on the ERR OR pin. By default the device will restart. Current limiting wi ll not occur for currents below the OCE THR level, see Table 7 Current protection against speaker terminal shorts requires an equivalent load inductance L Le q on each of the output OUTXX pins (see Table 6 L oad inductance from loudspeaker cables and if used, ferrite beads (EMC filter) will typically be sufficient T emperature protection An on chip temperature sensor effectively safeguards the device against a thermally induced failure due to overloading and/or insufficient cooling. A high junction tem perature initially causes a temperature warning, TW. This can be detected by reading the error register (address 124 , bit 4) via I2C. If the temperature continues to rise the device will reach the temperature error (TE) level and set the TE bit in the e rror register (address 12 4, bit 5). This will cause the device to stop all switching activity. T he device will restart after sufficient cooling down of the system. Both TW and TE will report the error on the /ERR OR pin Table High Temperature Warning and Error Signaling Levels Name Parameter Test Conditions Typ ical Value Unit TE THR,SET High Temperature Error (TE) Set Threshold Temperature rising 150 TE THR,CLR High Temperature Error (TE) Clear Threshold Temperature falling 135 TW THR,SET High Temperature Warning (TW) Set Threshold Temperature rising 125 TW THR,CLR High Temperature Warning (TW) Clear Threshold Temperature falling 105

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Power supply monitors The MA12040 features integrated PVDD, DVDD and AVDD under voltage lockout. Table shows typical limits for the supply monitors. Table Under volt age lockout levels Name Parameter Test Conditions Typ ical Value Unit UVP DVDD DVDD under voltage error threshold DVDD Rising 4.2 V DVDD Falling 4.0 V UVP AVDD AVDD under voltage error threshold AVDD Rising 4.2 V AVDD Falling 4.0 V UVP PVDD PVDD under voltage error threshold PVDD Rising 4.3 V PVDD Falling 4.1 V DC protection The MA12040 incorporates a circuit, detecting whether a DC is present on the amplifier output terminals driving the loudspeaker. In case of an unexpected DC being present on any of the amplifier outputs, the power stage will be shut down to protect the lou dspeaker from harmful DC content. Furthermore, a failure is reported on the /ERROR pin and in the error register readable by the device serial interface. The power stage can be restarted by resetting the device by cycling the /ENABLE pin or toggle the eh_c lear bit ( bit 2, address 45) to clear the error register DC protection is default on. It can be disabled by clearing bit 2 of Eh_dcShdn (address 0x26). For the DC protection circuit to trigger, the DC value of an output pin must be staying above 0.63*PVDD or below 0.37*PVDD for more than 700ms. Clock system The MA12040 incorporates a clock system consisting of an input clock divider and PLL, a low jitter low TC oscillator (2.8224 MHz) and control logic. The input clock frequency is a uto detected by the input clock divider and the corresponding divider ratio is selected as a function of the input frequency and the internal oscillator frequency The correct PLL reference clock is generated from this T he internal PLL divider ratio is also selected as a function of the master clock base frequency (2.8224 or 3.072 MHz). The MA12040 accepts input master clock frequencies that are 1, 2, 4 or 8 times the base frequency. This clock system automatically handles clock errors and master clock frequency changes without requiring an external system controller, thereby significantly reducing the overall system complexity. The MA12040 can operate in two clock modes: Master mode ( CLKM/S =1) In this mode the MA12040 uses the internal oscillator as a reference for the internal PLL. The internal master clock is accessible via the CLKIO pin and can be distributed to other MA12040 ICs operating in slave mode. Slave mode ( CLKM/S =0) In this clock mode, the input master clock (via the CLKIO pin) provides th e reference for the internal PLL through the input clock divider circuit. In slave mode the MA12040 accepts input master clock frequencies in the range specified above.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Clock synchronization In the situation where multiple MA12040 devices are going to be used in one system it is advisable to use one MA12040 in master mode and the other MA12040 devices in slave mode. This way the mutual PWM switching frequencies are synchronized which minimizes cross coupling between devices that could ca u se inter modulated audio in band tones. MCU/Serial control interface The I2C serial control interface of the MA12040 allows an I2C master to read and/or modify a wide range of device parameters. The I2C interf ace consists of four physical pins SDA, SCL, AD0 and AD1 I2C decoder logic handles transaction protocol and read/write access to the device regist er bank. SDA and SCL are standard bidirectional I2C slave pins for data and clock respectively. Both SDA an d SCL must be pulled up to a digital I/O (3.3V 5V) with a 5k resistor on each pin and operated in standard I2C mode up to 100 kbps transmission rate P ins AD0 and AD1 are used to configure the bit I2C address of the device . The I2C address is decoded according to Table Table I2C address decoding I2C device address AD1 pin AD0 pin bit I2C address 0x20 0b0100000 0x21 0b0100001 0x22 0b0100010 0x23 0b0100011 The I2C interface enables read/write operation s to the device register bank. The register bank is organized as a 128 entry, byte wide memory, holding device configuration and status registers. The address space from 0 to 80 holds read/write registe rs and the address space from 96 to 127 are read only . The complete address map and description of each register is presented in “Register Map” section Figure shows the block schematic of the I2C interface between: I2C bus and MA12040 ( serial interface controller and the register bank SDA SCL AD AD Digital I O DVDD I C bus MA 12040 Read Write Read only Serial interface controller Register bank Figure . I2C bus interface and register bank

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 I2C write operation Each I2C transaction is initiated from a master by sending an I2C start condition followed by the 7 bit I2C device address and cleared read/write bit. The device address and read/write bit is signaled on the SDA bus by pulling the bus to g round indicating a ‘0’ or releasing the bus to indicate a ‘1’ . The I2C SDA input is sampled by the device on the rising edge of the SCL bus. If the transmitted I2C address matches the configured address of the device, the device will acknowledge the reque st by pulling the SDA bus to ground. The master samples the acknowledged bit from the device on the next rising edge of SCL. The I2C initialization as described is show n in the waveform in Figure Figure . I2C init addressing sequence T o complete the device register write operation, the master must continue transmitting the address and at least one data byte. The device continue s to acknowledge each byte received on the 9 th SCL rising edge. Each additional data written to the device is written to the next address in the register bank. The write transaction is terminated when the master sends a stop signal to the device. The stop signal consists of a rising edge on SDA during SCL kept high. Figure shows a single write operation. Figure I2C write operation I2C read operation To read data from the device register bank the read tran saction is started by sending a write command to the I2C address with the R/W bit cleared followed by the device address to read from. Se e Figure Figure I2C read transaction, register bank to be rea d from is written to the device The device will acknowledge the two bytes . Then dat a can be fetch ed from the devi c e by sending a repeated start follow ed by a n I2C read command consisting of a byte with the device I2C address and the R/W bit set. The device will acknowledge the read request and start to drive the SDA bus with the bits f rom the requested register bank address. See Figure

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Figure I2C read transaction last part The read transaction continues until the master does not acknowledge the 9 th bit of the data read byte transaction and sends a stop signal. The stop condition is defined as a rising edge of SDA while SCL is high. Table I2C timing requirements Parameter Min Typ Max Unit C lock frequency 100 kHz SDA and SCL rise time µs SDA and SCL fall time µs SCL clock high µs SCL clock low µs Data, setup 300 ns Data, hold ns Min stop to start condition µs NOTE : Pull up resistance is equal to 2.2k Ω for 400kHz. C LIP pin and soft clipping The CLIP pin changes from a HIGH state to LOW state when audio output is close to clipping. A sy stem microcontroller can at this instance decrease volume level or, if possible, increase power st age voltage in order to avoid clipping The associated modulation ind ex for both channel 0 and channel 1 can be read out by reading address 98 and address 1 respectively. Note that /CLIP pin is an open drain output which means that it should be pulled up through a pull up resistor to the digital I/O DVDD of the system. To minimize possible audible artifacts from sticky clipping or ringing around the clippi ng region, it is possible to enable a soft clipping scheme. This clipping scheme prevents the amplifier to sticky clip and minimizes ringing which subsequently minimizes possible audible artifacts apart from normal clipping audibility. The soft clipping sc heme can be enabled by setting bit 7 of address 10. /ERROR pin and error handling The /ERROR pin changes from a HIGH state to a LOW state when one of the associated error sources is triggered. A system microcontroller can at this instance read out the erro r registers (address 45 and 109) . According to the type of error or warning the right measures can be taken. The errors will be shown in the error register (address 124) which shows the live status of the error sources. Another register error_acc (address 109) will contain all the errors accumulated over time. The error_acc register can be cleared by toggling the eh_clear bit (bit 2, address 45). Table shows the content of the error vector which is mapped to both the error register and the accumulated error register. A more detailed explanation can be found in “Register Map” section Table Error vector B it 7 Bit 6 Bit 5 Bit 4 Bit Bit 2 Bit 1 Bit 0 dc_ prot pps ote otw uvp pll ocp fcov Note that t he /ERROR pin has an open drain output and should be pulled up to the interface I/O rail.

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Application Information

Input/Output Configurations The MA12040 is highly flexible regarding configuration of the four power amplifier channels. MA12040 can be set to four different output configurations. By setting the configuration pins MSEL0 and MSEL1 according to Table , the device is configured to one of the four different configurations Each configuration is individually described in the following sections Table Signal configuration MSEL0 pin MSEL1 pin Configuration 1 channel parallel bridge tied load (PBTL) 2 channels single ended load (SE) and 1 channel bridge tied load (BTL) 2 channels bridge tied load (BTL) 4 channels s ingle ended load (SE) Bridge Tied Load (BTL) Configuration In BTL configuration, two input and output terminals a re used per channel as shown in Figure and Figure This configuration will enable the full potential of multi level technology where the speaker load will experience up to 5 levels. This enables low near idle power consumption and beneficial noise properties. Figure shows a Bridge Tied Load (BTL) c onfiguration (2 audio channels) with symmetrical audio sources having a differential output signal In default recommended configuration external AC coupling capacitors are used to allow the MA12040 to self bias the DC voltage o n the input terminals. Alternative ly, the input can be driv en without the AC coupling capacitors. In this case t he common mode offset voltage should be selected to ensure that the voltage on the input terminals at full scale audio levels are within the recommended range (see Table EMC filter depending on application t t Audio sources R s R s t t R s R s V OUT A OUT B OUT A OUT B IN A IN B IN A IN B MSEL MSEL C in C in C in C in Figure Bridge tied load (BTL) configuration, with symmetrical audio sources Figure shows a Bridge Tied L oad (BTL) configuration (2 audio channels) with single ended audio sources. Note that the drive impedance of the two input terminals a re match ed to achieve optimum audio performance.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 EMC filter depending on application Audio sources V t C in R s C in R s V t C in R s C in R s V OUT A OUT B OUT A OUT B IN A IN B IN A IN B MSEL MSEL Figure Bridge tied load (BTL) configuration, with single ended audio sources Single Ended (SE) Configuration In single ended (SE) configuration, the MA12040 is able to drive one loudspeaker per output power stage, i.e. up to four loudspeakers. The output is biased to half the power supply voltage, ½ PVDD One of the solutions to drive a speaker in this configuration is to use AC coupling capacitors C out in series with the load, as shown in Figure . The value of the capacitors depends on the load resistance and t he desired audio bandwidth. Table shows examples of AC coupling capacitor values. The DC voltage across the capacitors a t the output is approximately ½ PVDD. Howeve r, significant AC voltage swing might occur at low frequencies, which must be accounted for in the voltage rating of the capacitors. V A t Audio sources C in R s C out OUT A OUT B OUT A OUT B C out C out C out IN A IN B IN A IN B V B t C in R s V A t C in R s V B t C in R s EMC filter depending on application MSEL MSEL V V Figure Four channel, single ended (SE) configuration

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Table Typical values for the output AC coupling capacitor, C out Load Resistance Output AC coupling capacitor, C out 3dB frequency Ω 220µF 90Hz Ω 1000µF 20Hz Ω 2200µF 18Hz Combined SE and BTL Configuration A combination of SE and BTL configuration can be used as shown in Figure . In this configuration two half bridges are combined to run in BTL configuration and the two remaining half bridges are configured to run in SE configuration. EMC filter depending on application Audio sources V A t C in R s C in V t C in R s C in R s V B t R s C out C out OUT A OUT B OUT A OUT B IN A IN B IN A IN B MSEL MSEL V Figure Combined Bridge tied load (BTL) and single ended (SE) configuration with SE audio sources Parallel Bridge Tied Load (PBTL) For providing additional power the MA12040 can be configured for mono operation using a parallel BTL mode (PBTL), as shown in Figure In this fashion the two BTL output stages are combined to be able to deliver twice the current. This makes high output power sub woofer application possible. Note: Input pins IN1A and IN1B are unused and can be left floating.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Figure Parallel Bridge Tied Load (PBTL) configuration Regardless the application, it is recommended to use AC coupling capacitors, C in , at the analog audio input terminals INX X to allow the internal biasing circuitry to set a suitable DC bias operating voltage on the input terminals. The value of the capacitors depends on the configuration, see Table . Ceramic capacitors are recommended, e g. of type X5R. Table Recommended values for input ac coupling capacitors, C in Input Impedance MA12040 Configuration Recommended minimum AC coupling capacitor, C in Gain drop at 20Hz k Ω High gain mode 2.2µF 0.6dB k Ω Low gain mode 1µF 1dB EMC output filter Considerations The proprietary level modulation significantly reduces EMC emissions, and the amplifiers can pass the Radiated Emission test with speaker cables lengths up to 80 cm with just a small ferrite filter. For cables longer than 80 cm it is recommended to use a LC filter. For more information regarding filter type, components and measurements, see the document “Applications note EMC Output Filter Recomm e ndations” at the Infineon homepage. Audio Performance Measurements In a typical audio application the outputs of the MA12040 will be connected directly to the speaker loads. However, for audio performance evaluation it can be beneficial to configure the circuit board with an LC filter. This is due to the fact that many audio analyzers do not handle PWM signals at their inputs well. When using an audio anal yzer configured with an external and/or internal measurement filter the u se of an LC filter is not necessary. However, be sure to verify the audio analyzer’s input limits before connecting it to a filterless amplifier output. When using an LC filter the design depends on the specific load. L and C values should therefore be op timized for this.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Thermal Characteristics and Test Signals Performing audio measurements by use of an audio analyzer is typically very helpful during the evaluation of an amplifier. However, using an audio analyzer can be misleading when evaluating thermal performance. Audio analyzers typically generate full tone, continuous sine wave signals as the input signal for the amplifier. While this is required to perform many audio measurements, it is also the worst case thermal scenario for the device. Using full scale continuous sine waves for thermal evaluation or testing will lead to an overly conservative and more costly thermal design which will be unnecessary in almost all real audio applications. Actual audio content, such as music, has much lower RMS value s compared to its maximum peak output power than a full scale continuous sine wave. This results in significantly less heat dissipation from the device when amplifying actual audio. For thermal evaluation it is therefore recommended to use actual music sig nals during tests. Alternatively, a pink noise signal can be used to emulate a music signal. It is not uncommon for an amplifier solution to have limited thermal performance, potentially resulting in thermal protection shutdown, when amplifying full scale continuous sine wave signal s Start up procedure It is recommended to follow the start up procedure as described below: Make sure the all hardware pins are configured correctly: e.g. BTL, Slave Clock mode Keep the device in disable and mute: /ENABLE = 1; /MUTE = 0 Bring up 5V VDD supply and PVDD supply (it does not matter if VDD or PVDD comes up first, provided that the device is held in disable) Wait for VDD and PVDD to be stable Enable device: /ENABLE = 0 Program applicable initialization to register s Unmute device: /MUTE = 1 The device is now in normal operation state Shut down / power down procedure It is recommended to follow the start up procedure as described below: The device is in n ormal operation state Mute device: /MUTE = 0 Disable devic /ENABLE = 1 The device is now power down state. Bring down 5V VDD supply and PVDD supply The device is now in shut down state Recommended PCB Design for MA12040 QFN E PAD down package The QFN package with exposed thermal pad at the bottom side is thermally sufficient for most applications. However, in order to remove heat from the package care should be taken in designing the PCB. The PCB footprint for the device should include a the r mal relief pad underneath the device with a size of 6 x 6 mm. This thermal relief pad must be centered so the device can be solder ed easily. It is recommended to use a PCB design with two or more layer s of copper for good thermal performance. Using multiple layers enables a design with a large area o f copper conn ected to the EPAD. To achieve best thermal performance i t is also important to design the surrounding connections in such a way that avoids cut ting up the copper area in to many sections

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Figure shows a PCB design using 26 via connections directly underneath the chip between the top and bottom layers. These should be placed on a grid each with a 0.65 mm plated through hole. The se con nections ensure good thermal transfer from the top side EPAD to a large section of ground connected copper area on the bottom side of the PCB Figure Example of 2 layer PCB layout, top and bottom layers It is recommended to use a PCB made from glass/ epoxy laminate e.g. FR material. This type of material works well with PCB designs that require thermal relief as it can endure high temperature s for a long duration of time. PCB copper thickness i s recommended to be a minimum of 35μ (1 oz) and the PCB must be made to the IPC 6012C, Class standard.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz Typical Characteristics PVDD = 18V , Load = 4Ω + 22µH BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Output Power for PMP2 Figure THD+N vs Output Power for PMP4 Figure

1 THD+N vs

PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Frequency for PMP2 Figure THD+N vs Frequency for PMP4 Figure THD+N vs Frequency for PMP0 Figure THD+N vs Frequency for PMP1 PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PMP2 Efficiency (VDD+PVDD) vs Output Power Figure PMP4 Efficiency (VDD+PVDD) vs Output Power Figure PMP0 Efficiency (VDD+PVDD) vs Output Power Figure PMP1 Efficiency (VDD+PVDD) vs Output Power PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Input Power vs Output Power for PMP2 F igure Input Power vs Output Power for PMP4 Figure Input Power vs Output Power for PMP0 Figure Input Power vs Output Power for PMP1 PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP0 PMP1 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP2 PMP4 PVDD Idle Current (mA) PVDD (V) PMP0 PMP1 PVDD Idle Current (mA) PVDD (V) PMP2 PMP4 BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PVDD Idle Current vs PVDD for PMP0 & PMP1 Figure PVDD Current vs Output Power for PMP0 & PMP1 PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H Figure PVDD Current vs Output Power for PMP2 & PMP4 PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H Gain = 20dB Load = 4 Ω + 22 µ H Gain = 20dB Load = 4 Ω + 22 µ H Figure PVDD Idle Current vs PVDD for PMP2 & PMP4

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Output Power (W) PVDD (V) 1% THD+N 10% THD+N Output Power (W) PVDD (V) 1% THD+N 10% THD+N Output Power (W) PVDD (V) 1% THD+N 10% THD+N Output Power (W) PVDD (V) 1% THD+N 10% THD+N BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure

23 Output Power vs PVDD Voltage for PMP2

24 Output Power vs PVDD Voltage for PMP4

Output Power vs PVDD Voltage for PMP0 Figure

22 Output Power vs PVDD Voltage for PMP1

Gain = 20dB Load = 4 Ω + 22 µ H Gain = 20dB Load = 4 Ω + 22 µ H Gain = 20dB Load = 4 Ω + 22 µ H Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Low Gain vs Frequency for PMP2 Figure Low Gain vs Frequency for PMP4 Figure Low Gain vs Frequency for PMP0 Figure Low Gain vs Frequency for PMP1 PVDD = +18V Load = 4 Ω + 22 µ H PVDD = +18V Load = 4 Ω + 22 µ H PVDD = +18V Load = 4 Ω + 22 µ H PVDD = +18V Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure High Gain vs Frequency for PMP2 Figure High Gain vs Frequency for PMP4 Figure High Gain vs Fre quency for PMP0 Figure High Gain vs Frequency for PMP1 PVDD = +18V Load = 4 Ω + 22 µ H PVDD = +18V Load = 4 Ω + 22 µ H PVDD = +18V Load = 4 Ω + 22 µ H PVDD = +18V Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Crosstalk vs Frequency for PMP2 Figure

36 Crosstalk vs

Crosstalk vs Frequency for PMP0 Figure

34 Crosstalk vs Frequency for PMP1

PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz Typical Characteristics (PVDD = 18V, Load = 8Ω + 22µH) BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs. Output Power for PMP2 Figure THD+N vs. Output Power for PMP4 Figure THD+N vs. Output Power for PMP0 Figure THD+N vs. Output Power for PMP1 PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Frequency for PMP2 Figure THD+N vs Frequency for PMP4 Figure THD+N vs Frequency for PMP0 Figure THD+N vs Frequency for PMP1 PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 8 Ω + 22 µ H PVDD = +18V Gain = 20dB Load = 8 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PMP2 Efficiency (VDD+PVDD) vs Output Power Figure PMP0 Efficiency (VDD+PVDD) vs Output Power PVDD = +18V Gain = 20dB Load = Ω + 22 µ H Figure PMP1 Efficiency (VDD+PVDD) vs Output Power PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H Figure PMP4 Efficiency (VDD+PVDD) vs Output Power

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Input Power vs Output Power for PMP2 Figure Input Power vs Output Power for PMP4 Figure Input Power vs Output Power for PMP0 Figure Input Power vs Output Power for PMP1 PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP0 PMP1 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP2 PMP4 PVDD Idle Current (mA) PVDD (V) PMP0 PMP1 PVDD Idle Current (mA) PVDD (V) PMP2 PMP4 BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PVDD Idle Current vs PVDD for PMP0 & PMP1 Figure PVDD Current vs Output Power for PMP0 & PMP1 Figure PVDD Current vs Output Power for PMP2 & PMP4 PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H Gain = 20dB Load = Ω + 22 µ H Gain = 20dB Load = Ω + 22 µ H Figure PVDD Idle Current vs PVDD for PMP2 & PMP4

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Output Power (W) PVDD (V) 1% THD+N 10% THD+N Output Power (W) PVDD (V) 1% THD+N 10% THD+N Output Power (W) PVDD (V) 1% THD+N 10% THD+N Output Power (W) PVDD (V) 1% THD+N 10% THD+N BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Output Power vs PVDD Voltage for PMP0 Figure Gain = 20dB Load = Ω + 22 µ H Gain = 20dB Load = Ω + 22 µ H Gain = 20dB Load = Ω + 22 µ H Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Low Gain vs Frequency for PMP2 Figure Low Gain vs Frequency for PMP4 Figure Low Gain vs Frequency for PMP0 Figure Low Gain vs Frequency for PMP1 PVDD = +18V Load = Ω + 22 µ H PVDD = +18V Load = Ω + 22 µ H PVDD = +18V Load = Ω + 22 µ H PVDD = +18V Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure High Gain vs Frequency for PMP2 Figure High Gain vs Frequency for PMP4 Figure High Gain vs Frequency for PMP0 Figure High Gain vs Frequency for PMP1 PVDD = +18V Load = Ω + 22 µ H PVDD = +18V Load = Ω + 22 µ H PVDD = +18V Load = Ω + 22 µ H PVDD = +18V Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Crosstalk vs Frequency for PMP2 Figure

36 Crosstalk vs Frequency for

Crosstalk vs Frequency for PMP0 Figure PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H PVDD = +18V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz Typ ical Characteristics (PVDD = +15 V, Load = 4Ω + 22µH) BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Output Power for PMP2 Figure THD+N vs Output Power for P MP4 Figure THD+N vs Output Power for PMP0 Figure THD+N vs Output Power for PMP1 PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Frequency for PMP2 Figure THD+N vs Frequency for PMP4 Figure THD+N vs Frequency for PMP0 Figure THD+N vs Frequency for PMP1 PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PMP2 Efficiency (VDD+PVDD) vs Output Power Figure PMP4 Efficiency (VDD+PVDD) vs Output Power Figure PMP0 Efficiency (VDD+PVDD) vs Output Power Figure PMP1 Efficiency (VDD+PVDD) vs Output Power PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Input Power vs Output Power for PMP2 Figure Input Power vs Output Power for PMP4 Figure Input Power vs Output Power for PMP0 Figure Input Power vs Output Power for PMP1 PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PV DD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP0 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP1 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP2 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP4 BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PVDD Current vs Output Power for PMP2 Figure PVDD Current vs Output Power for PMP4 Figure PVDD Current vs Output Power for PMP0 Figure PVDD Current vs Output Power for PMP1 PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kH z). Figure Low Gain vs Frequency for PMP2 Figure Low Gain vs Frequency for PMP4 Figure Low Gain vs Frequency for PMP0 Figure Low Gain vs Frequency for PMP1 PVDD = +15V Load = 4 Ω + 22 µ H PVDD = +15V Load = 4 Ω + 22 µ H PVDD = +15V Load = 4 Ω + 22 µ H PVDD = +15V Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure High Gain vs Frequency for PMP2 Figure High Gain vs Frequency for PMP4 Figure High Gain vs Frequency for PMP0 Figure High Gain vs Frequency for PMP1 PVDD = +15V Load = 4 Ω + 22 µ H PVDD = +15V Load = 4 Ω + 22 µ H PVDD = +15V Load = 4 Ω + 22 µ H PVDD = +15V Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Crosstalk vs Frequency for PMP2 Figure

32 Crosstalk vs Frequency for PMP4

Crosstalk vs Frequency for PMP0 Figure

30 Crosstalk vs Frequency for PMP1

PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz Typical Characteristics (PVDD = +15V, Load = 8Ω + 22µH) BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs. Output Power for PMP2 Figure THD+N vs. Output Power for PMP4 Figure THD+N vs. Output Power for PMP0 Figure THD+N vs. Output Power for PMP1 PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Frequency for PMP2 Figure THD+N vs Frequency for PMP4 Figure THD+N vs Frequency for PMP0 Figure THD+N vs Frequency for PMP1 PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 8 Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = 8 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PMP2 Efficiency (VDD+PVDD) vs Output Power Figure PMP4 Efficiency (VDD+PVDD) vs Output Power Figure PMP0 Efficiency (VDD+PVDD) vs Output Power Figure PMP1 Efficiency (VDD+PVDD) vs Output Power PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Input Power vs Output Power for PMP2 Figure Input Power vs Output Power for PMP4 Figure Input Power vs Output Power for PMP0 Figure Input Power vs Output Power for PMP1 PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP0 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP1 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP2 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP4 BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PVDD Current vs Output Power for PMP2 Figure PVDD Current vs Output Power for PMP4 Figure PVDD Current vs Output Power for PMP0 Figure PVDD Current vs Output Power for PMP1 PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Low Gain vs Frequency for PMP2 Figure Low Gain vs Frequency for PMP4 Figure Low Gain vs Frequency for PMP0 Figure Low Gain vs Frequency for PMP1 PVDD = +15V Load = Ω + 22 µ H PVDD = +15V Load = Ω + 22 µ H PVDD = +15V Load = Ω + 22 µ H PVDD = +15V Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure High Gain vs Frequency for PMP2 Figure High Gain vs Frequency for PMP4 Figure High Gain vs Frequency for PMP0 Figure High Gain vs Frequency for PMP1 PVDD = +15V Load = Ω + 22 µ H PVDD = +15V Load = Ω + 22 µ H PVDD = +15V Load = Ω + 22 µ H PVDD = +15V Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Crosstalk vs Frequency for PMP2 Figure

36 Crosstalk vs Frequency

Crosstalk vs Frequency for PMP0 Figure PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +15 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVD D = +15 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz Typical Characteristics (PVDD = +12V, Load = 4Ω + 22µH) BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs. Output Power for PMP2 Figure THD+N vs. Output Power for P MP4 Figure THD+N vs. Output Power for PMP0 Figure THD+N vs. Output Power for PMP1 PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Frequency for PMP2 Figure THD+N vs Frequency for PMP4 Figure THD+N vs Frequency for PMP0 Figure THD+N vs Frequency for PMP1 PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PMP2 Efficiency (VDD+PVDD) vs Output Power Figure PMP0 Efficiency (VDD+PVDD) vs Output Power PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H Figure PMP1 Efficiency (VDD+PVDD) vs Output Power PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H Figure PMP4 Efficiency (VDD+PVDD) vs Output Power

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Input Power vs Output Power for PMP2 Figure Input Power vs Output Power for PMP4 Figure Input Power vs Output Power for PMP0 Figure Input Power vs Output Power for PMP1 PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP0 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP1 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP2 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP4 BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PVDD Current vs Output Power for PMP2 Figure PVDD Current vs Output Power for PMP4 Figure PVDD Current vs Output Power for PMP0 Figure PVDD Current vs Output Power for PMP1 PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = + V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Low Gain vs Frequency for PMP2 Figure Low Gain vs Frequency for PMP4 Figure Low Gain vs Frequency for PMP0 Figure Low Gain vs Frequency for PMP1 PVDD = +12V Load = 4 Ω + 22 µ H PVDD = +12V Load = 4 Ω + 22 µ H PVDD = +12V Load = 4 Ω + 22 µ H PVDD = +12V Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 10W BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure High Gain vs Frequency for PMP2 Figure High Gain vs Frequency for PMP4 Figure High Gain vs Frequency for PMP0 Figure High Gain vs Frequency for PMP1 PVDD = +12V Load = 4 Ω + 22 µ H PVDD = +12V Load = 4 Ω + 22 µ H PVDD = +12V Load = 4 Ω + 22 µ H PVDD = +12V Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 BTL configuration; Load = 4 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Crosstalk vs Frequency for PMP2 Figure Crosstalk vs Frequency for PMP0 Figure PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = 4 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 4 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz 0.001 0.01 0.1 100 0.001 0.01 0.1 100 THD+N (%) Output Power (W) 100Hz 1kHz 6kHz Typical Characteristics (PVDD = +12V, Load = µH) BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs. Output Power for PMP2 Figure THD+N vs. Output Power for PMP4 Figure THD+N vs. Output Power for PMP0 Figure THD+N vs. Output Power for PMP1 PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W 0.001 0.01 0.1 100 200 2000 20000 THD+N (%) Frequency (Hz) 0.5W 2.5W BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure THD+N vs Frequency for PMP2 Figure THD+N vs Frequency for PMP4 Figure THD+N vs Frequency for PMP0 Figure THD+N vs Frequency for PMP1 PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 8 Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = 8 Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel 100 Efficiency (%) Output Power (W) Output Power Per Channel BTL configuration; Load = Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PMP2 Efficiency (VDD+PVDD) vs Output Power Figure PMP4 Efficiency (VDD+PVDD) vs Output Power Figure PMP0 Efficiency (VDD+PVDD) vs Output Power Figure PMP1 Efficiency (VDD+PVDD) vs Output Power PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel 0.1 100 0.0001 0.001 0.01 0.1 100 Input Power (W) Output Power (W) Output Power Per Channel BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Input Power vs Output Power for PMP2 Figure Input Power vs Output Power for PMP4 Figure Input Power vs Output Power for PMP0 Figure Input Power vs Output Power for PMP1 PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP0 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP1 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP2 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 100 PVDD Current (A) Output Power (W) PMP4 BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure PVDD Current vs Output Power for PMP2 Figure PVDD Current vs Output Power for PMP4 Figure PVDD Current vs Output Power for PMP0 Figure PVDD Current vs Output Power for PMP1 PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Low Gain vs Frequency for PMP2 Figure Low Gain vs Frequency for PMP4 F igure Low Gain vs Frequency for PMP0 Figure Low Gain vs Frequency for PMP1 PVDD = +12V Load = Ω + 22 µ H PVDD = +12V Load = Ω + 22 µ H PVDD = +12V Load = Ω + 22 µ H PVDD = +12V Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W 24.2 24.4 24.6 24.8 25.2 25.4 25.6 25.8 200 2000 20000 Gain (dB) Frequency (Hz) 0.5W 2.5W BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure High Gain vs Frequency for PMP2 Figure High Gain vs Frequency for PMP4 Figure High Gain vs Frequency for PMP0 Figure High Gain vs Frequency for PMP1 PVDD = +12V Load = Ω + 22 µ H PVDD = +12V Load = Ω + 22 µ H PVDD = +12V Load = Ω + 22 µ H PVDD = +12V Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 200 2,000 20,000 Crosstalk (dB) Frequency (Hz) Ch0 to Ch1 Ch1 to Ch0 BTL configuration; Load = 8 Ω + 22µH ; Measurements carried out with APx 515 + AUX 0025 input filter; APx uses AES17 brick wall filter (20kHz). Figure Crosstalk vs Frequency for PMP2 Figure Crosstalk vs Frequency for PMP0 Figure PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVDD = +12 V Gain = 20dB Load = Ω + 22 µ H PVDD = +1 V Gain = 20dB Load = Ω + 22 µ H PVD D = +12 V Gain = 20dB Load = Ω + 22 µ H

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Register map For all register map: f “ : Don’t Care condition “ : Reserved bits configured during factory settings. Read / Write Access (Power Mode Settings) Address Default Address Value Bit(s) Value Function 0x00 0x3D Power Mode Control manualPM 1 1 Select manual Power Mode control. Default the device will operate in automatic Power Mode control. This bit can be set to 1 if manual Power Mode control is required. PM_man 5:4 1 1 Manual selected power mode. These two bits can be used selecting the Power Mode of the device when it is in manual Power Mode control. 0 0 Reserved 0 1 Power Mode 1 1 0 Power Mode 2 1 1 Power Mode 3 0x01 0x3C Threshold for Power Mode change PM1=>PM2 Mthr_1to2 7:0 0 0 1 1 1 1 0 0 Threshold value for PM1=>PM2 change. This value will set the threshold for when automatic Power Mode changes from PM1 to PM2. It can be programmed from 0 255; this maps to 0 output power max output power. 0x02 0x32 Threshold for Power Mode change PM2=>PM1 Mthr_2to1 7:0 0 0 1 1 0 0 1 0 Threshold value for PM2=>PM1 change. This value will set the threshold for when automatic Power Mode changes from PM2 to PM1. It can be programmed from 0 255; this maps to 0 output power max output power. 0x03 0x5A Threshold for Power Mode change PM2=>PM3 Mthr_2to3 7:0 0 1 0 1 1 0 1 0 Threshold value for PM2=>PM3 change. This value will set the threshold for when automatic Power Mode changes from PM2 to PM3. It can be programmed from 0 255; this maps to 0 output power max output power. 0x04 0x50 Threshold for Power Mode change PM3=>PM2 Mthr_3to2 7:0 0 1 0 1 0 0 0 0 Threshold value for PM3=>PM2 change. This value will set the threshold for when automatic Power Mode changes from PM3 to PM2. It can be programmed from 0 255; this maps to 0 output power max output power. 0x0A 0xC Soft clipping and over current protection latching lf_clamp_en Enables soft clipping. High to enable. Low to disable. ocp_latch_en High to use permanently latching OCP.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Read / Write Access (Power Mode Profile Settings): Address Default Address Value Bit(s) Value Function 0x1D 0x00 Select Power Mode Profile setting PM profile 2:0 f f f f f 0 0 0 Power Mode Profile select. With this register the user can selects the appropriate Power Mode Profile. 0 0 0 Power Mode Profile 0 0 0 1 Power Mode Profile 1 0 1 0 Power Mode Profile 2 0 1 1 Power Mode Profile 3 1 0 0 Power Mode Profile 4 0x1E 0x2F Power Mode Profile configuration PM3_man 5:4 f f 1 0 Custom profile PM3 content 0 0 Assign scheme A to PM3 0 1 Assign scheme B to PM3 1 0 Assign scheme C to PM3 1 1 Assign scheme D to PM3 PM2_man 3:2 f f 1 1 Custom profile PM2 content 0 0 Assign scheme A to PM2 0 1 Assign scheme B to PM2 1 0 Assign scheme C to PM2 1 1 Assign scheme D to PM2 PM1_man 1:0 f f 1 1 Custom profile PM1 content 0 0 Assign scheme A to PM1 0 1 Assign scheme B to PM1 1 0 Assign scheme C to PM1 1 1 Assign scheme D to PM1 0x20 0x1F Over current protection latch clear ocp_latch_cle ar Clears over current protection latch. A low to high toggle clears the current OCP latched condition. 0x25 0x10 Audio in mode audio_in_mo de 6:5 0 0 Audio input mode. Sets the input mode of the amplifier. This means the amplifier overall gain setting. 0 0 Audio in mode 0: 20dB gain 0 1 Audio in mode 1: 26dB gain 0x26 0x05 DC protection Eh_dcShdn f f f f Enables or disables DC protection. High to enable. Low to disable. 0x27 0x08 Audio in mode overwrite audio_in_mo de_ext 0 0 Enables audio in mode default overwrite. High to enable. Low to disable. Should enabled for address 0x25 to have effect. 0x2D 0x30 Error handler clear eh_clear Clears error handler. A low to high to low toggle clears the error handler.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Read Only Access Monitor Channel 0 and Channel 1 Address Default Address Value Bit(s) Value Function 0x60 0x00 Monitor register channel 0 (Frequency and Power Mode) dcu_mon0.fr eqMode 6:4 0 0 0 f f 0 0 Frequency mode monitor channel 0. Register to read out in which frequency mode channel 0 of the device is currently operating in. dcu_mon0.P M_mon 1:0 f f 0 0 Power mode monitor channel 0. Monitor to read out in which Power Mode channel 0 of the device is currently operating in. 0x61 0x00 Monitor register channel 0 dcu_mon0.m ute f f 0 0 0 0 0 Channel 0 mute monitor. Monitor to read out if channel 0 is in mute or in unmute. dcu_mon0.vd d_ok f f 0 0 0 0 0 Channel 0 VDD monitor. Monitor to read out if VDD for channel 0 is ok. dcu_mon0.pv dd_ok f f 0 0 0 0 0 Channel 0 PVDD monitor. Monitor to read out if PVDD for channel 0 is ok. dcu_mon0.Vc fly2_ok f f 0 0 0 0 0 Channel 0 Cfly2 protection monitor. Monitor to read out if Cfly2 for channel 0 is ok. dcu_mon0.Vc fly1_ok f f 0 0 0 0 Channel 0 Cfly1 protection monitor. Monitor to read out if Cfly1 for channel 0 is ok. OCP Monitor channel 0 f f 0 0 0 0 0 Channel 0 over current protection monitor. Monitor to read out if an over current protection event has occurred. 0x62 0x00 Monitor register channel 0 (Modulation Index) dcu_mon0.M _mon 7:0 0 0 0 0 0 0 0 0 Channel 0 modulation index monitor. Monitor to read out live modulation index. Modulation index from 0 to 1 maps on the 8 bits register from 0 to 255. 0x64 0x00 Monitor register channel 1 (Frequency and Power Mode) dcu_mon1.fr eqMode 6:4 0 0 0 f f 0 0 Frequency mode monitor channel 1. Register to read out in which frequency mode channel 1 of the device is currently operating in. dcu_mon1.P M_mon 1:0 f f 0 0 Power mode monitor channel 1. Monitor to read out in which Power Mode channel 1 of the device is currently operating in. 0x65 0x00 Monitor register channel 1 dcu_mon1.m ute f f 0 0 0 0 0 Channel 1 mute monitor. Monitor to read out if channel 1 is in mute or in unmute. dcu_mon1.vd d_ok f f 0 0 0 0 0 Channel 1 VDD monitor. Monitor to read out if VDD for channel 1 is ok. dcu_mon1.pv dd_ok f f 0 0 0 0 0 Channel 1 PVDD monitor. Monitor to read out if PVDD for channel 1 is ok. dcu_mon1.Vc fly2_ok f f 0 0 0 0 0 Channel 1 Cfly2 protection monitor. Monitor to read out if Cfly2 for channel 1 is ok. dcu_mon1.Vc fly1_ok f f 0 0 0 0 Channel 1 Cfly1 protection monitor. Monitor to read out if Cfly1 for channel 1 is ok. OCP Monitor channel 1 f f 0 0 0 0 0 Channel 1 over current protection monitor. Monitor to read out if an over current protection event has occurred. 0x66 0x00 Monitor register channel 1 (Modulation Index) dcu_mon1.M _mon 7:0 0 0 0 0 0 0 0 0 Channel 1 modulation index monitor. Monitor to read out live modulation index. Modulation index from 0 to 1 maps on the 8 bits register from 0 to 255.

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 Read Only Access (Error Register Monitoring): Address Default Address Value Bit(s) Value 0x6D 0x00 Error accumulated register error_acc 7:0 0 0 0 0 0 0 0 0 Error monitor register. Gives the accumulated status of every potential error source. This register should be cleared by using the error handler clear register. All bits will be 0 in default/normal operation and 1 when triggered Bit 0: flying capacitor over voltage error Bit 1: over current protection Bit 2: pll error Bit 3: PVDD under voltage protection Bit 4: over temperature warning Bit 5: over temperature error Bit 6: pin to pin low impedance protection Bit 7: DC protection 0x75 0x00 Monitor MSEL register msel_mon 2:0 f f f f f 0 0 0 MSEL[2:0] monitor register. Monitor to read out which output configuration the device is in: BTL, SE, BTL/SE or PBTL 0x7C 0x00 Error register error 7:0 0 0 0 0 0 0 0 0 Error monitor register. Gives the live status of every potential error source. All bits will be 0 in default/normal operation and 1 when triggered Bit 0: flying capacitor over voltage error Bit 1: over current protection Bit 2: pll error Bit 3: PVDD under voltage protection Bit 4: over temperature warning Bit 5: over temperature error Bit 6: pin to pin low impedance protection Bit 7: DC protection

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Revision History

Doc. Rev. Date Comments V 1.0 July 2018 Initial release in Infineon format

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Contents

Known Issues and Limitations Typical Application Block Diagram Pin Description 4.1 Pinout MA12040QFN 4.2 Pin Function Absolute Maximum Ratings Recommended Operating Conditions Electrical and Audio Characteristics Functional description Multi level modulation Very low power consumption Po wer Mode Management Power Modes Profiles Power supplies Gate driver supplies Digital core supply Flying capacitors Protection Over current protection on OUTXX nodes Temperature protection Power supply monit ors DC protection Clock system Clock synchroniz ation MCU/Serial control interface I2C write operation I2C read operation /CLIP pin and soft clipping /ERROR pin and error handling Input/Output Configurations Bridge Tied Load (BTL) Configuration Single Ended (SE) Configuration Combined SE and BTL Configuration Parallel Bridge Tied Load (PBTL)

Please read the Important Notice and Warnings at the end of this document V 1.0 www.infineon.com page of 2018 EMC output filter Considerations Audio Performance Measurements Thermal Characteristics and Test Signals Start up procedure Shut down / power down procedure Recommended PCB Design for MA12040QFN (EPAD down package) Typical Characteristics (PVDD = +18V, Load = 4 Ω + 22µH) Typical Characteristics (PVDD = +18V, Load = 8 Ω + 22µH) Typical Characteristics (PVDD = +15V, Load = 4 Ω + 22µH) Typical Characteristics (PVDD = +15V, Load = 8 Ω + 22µH) Typical Characteristics (PVDD = +12 V, Load = 4 Ω + 22µH) Typical Characteristics (PVDD = +12V, Load = 8 Ω + 22µH) Register map Read / Write Access (Power Mode Settings): Read / Write Access (Power Mode Profile Settings): Read Only Access (Monitor Channel 0 and Channel 1) Read Only Access (Error Register Monitoring):

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