M8880

M8880 CLARE | Alldatasheet

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ment.Ina single-ended configuration,the inputpins should be connected as shown in Figure 3.Figure4 shows the necessary connections fora differentialinputconfiguration. Receiver Section The low and high group tones are separated by applying the DTM F signalto the inputs oftwo sixth-orderswitched capacitor bandpassfilterswith bandwidthsthatcorrespond to the low and high group frequencies listed in Table 2. The low group filterin- corporates notches at350 and 440 Hz,providing excellentdial tone rejection.Each filteroutputis followed bya single-order switched capacitorfilterthatsmoothsthe signalspriorto limiting. Limiting is performed by high-gain comparators with hysteresis to preventdetection ofunwanted low-levelsignals.The com- parator outputs provide full-raillogic swings at the incoming DTM F signalfrequencies. A decoderemploysdigitalcounting techniquesto determine the frequencies ofthe incoming tones,and to verify thatthey corre- spond to standard DTM F frequencies.A complex averaging al- gorithm protects againsttone simulation by extraneous signals (such as voice),while tolerating smalldeviations in frequency. The algorithm provides an optimum combination ofimmunity to talkoffwith tolerance to interfering frequencies (third tones)and noise.Whe n the detectorrecognizes the presence oftwo valid tones (referred to as “signalcondition”),the early steering (ESt) outputgoes to an active state.Any subsequentloss ofsignal condition willcause ES tto assume an inactive state. Steering Circuit:Beforea decoded tone pairis registered,the receiverchecks fora valid signalduration (referred to as “char- acterrecognition condition”).This check is performed by an ex- ternalR C time constant driven by ESt. A logic high on ESt Page 2 M-8880 40-406-00012, Rev. G www.clare.com Figure 3 Single-Ended Input Configuration Figure 4 Differential Input Configuration Name Description IN+ Noninverting op-amp input. IN- Inverting op-amp input. GS Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. VREF Reference voltage output. Nominally VDD /2 is used to bias inputs at mid-rail. VSS Negative power supply input. OSC1 DTMF clock/oscillator input. OSC2 Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. TONE Dual tone multifrequency (DTMF) output. R/W Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter.TTL compatible. CS Chip select.TTL input (CS= 0 to select the chip). RS0 Register select input. See Table 6.TTL compatible. f2 System clock input. May be continuous orstrobed only during read or write.TTL compatible. IRQ/CP Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and inter- rupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11 D0 - D3 Microprocessor data bus.TTL compatible. ESt Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ES tto return to a logic low. St/GT Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The G T output acts to reset the external steering time-constant; its state is a funciton ofES tand the voltage on St. VDD Positive power supply input. Table 1 Pin Functions

VL and VH correspond to the low-group and high-group ampli- tude,respectively,and V IMD isthe sum ofallthe intermodulation components.The internalswitched capacitorfilterfollowing the D/A converter keeps distortion products down toa very low level. DTMF Clock Circuit The internalclockcircuitiscompleted with the addition ofastan- dard 3.579545 MH z television colorburstcrystal.A numbe rof M-8880 devices can be connected as shown in Figure8 using only one crystal. Microprocessor Interface The M-8880 usesa microprocessorinterface thatallows pre- cise controloftransmitterand receiverfunctions.Five internal registers are associated with the microprocessor interface, which can be subdivided into three categories:data transfer, transceivercontrol,and transceiverstatus.Tw o registers are associated with data transfer operations. The receive data, read-only,contains the outputcode ofthe lastvalid DTM F tone pairto be decoded.The data entered in the transmitdata regis- terdetermineswhich tone pairisto be generated (see Table 2). Data can only be written to the transmitdata register.Trans- ceivercontrolis accomplished with two controlregisters (CRA and CRB) ,occupying the sam e address space.A write opera- tion to CR B can be executed by setting the appropriate bitin CRA .The following write operation to the sam e address will then be directed to CRB ,and subsequentwrite cycles willthen be redirected to CRA .Internalresetcircuitry clears the control Page 5 M-8880 40-406-00012, Rev. G www.clare.com Bit Name Function Description b0 TOUT Tone output A logic 1 enables the tone output. This function can be implemented in either the burst mode or nonburstmode. b1 CP/DTMF Mode control In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow call progress tones to be detected. Call progress tones within the specified bandwidth will be pre- sented at the IRQ /CP pin in rectangular wave format if the IRQ bit has been enabled (b2 =1). Also, when the CP mode and burst mode have both been selected, the transmitter will issue DTMF sig- nals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be decoded when the CP mode has been selected. b2 IRQ Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been se- lected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal has been received and has been present for the guard time or (2) the transmitter is ready for more data (burst mode only). b3 RSET Register select A logic 1 selects control register B on the next write cycle to the control register address. Subse- quent write cycles to the control register are directed back to control register A. Table 4 Control Register A Description Bit Name Function Description b0 BURST Burst mode A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific duration (see Table 12). Subsequently, a pause of the same duration is induced. Immediately fol- lowing the pause, the status register is updated indicating that the transmit data register is ready for further instructions, and an interrupt will be generated if the interrupt mode has been enabled. Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increed by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired dura- tion may be generated. b1 TEST Test mode By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted) signal from the DTMF receiver. Refer to Figure 11 (b3 waveform) for details concerning the output waveform. DTMF mode must be selected (CRA b1 = 0) before test mode can be implemented. b2 S/D Single/dual tone generation A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled (logic 1), ei- ther now or column tones (low or high group) can be generated depending on the state of b3 in control register B. b3 C/R Column/row tones When used in conjunction with b2 (above), the transmitter can be made to generate single-row or single-column frequencies. A logic0 will select row frequencies and a logic 1 will select column fre- quencies. Table 5 Control Register B Description Figure 8 Common Crystal Connection

40-406-00012, Rev. G www.clare.com Parameter Symbol Min Typ* Max Units Operating supply voltage VDD 4.75 5.0 5.25 V Operating supply current IDD — 10 15 m A Power consumption PO — 50 78.75 mW Inputs High-level input voltage, OSC1 V IHO 3.5 — — V Low-level input voltage, OSC1 VILO — — 1.5 V Input impedance (@ 1 kHz), IN+, IN- R IN — 10 — M W Steering threshold voltage VTSt 2.2 2.3 2.5 V Outputs High-level output voltage (no load), OSC2 V OHO VDD - 0.1V — — V Low-level output voltage (no load), OSC2 VOLO — — 0.1 V Output leakage current (VOH = 2.4V),IRQ IOZ — 1.0 10.0 mA VREF output voltage (no load) VREF 2.4 — 2.7 V VREF output resistance R OR — 1.0 kW Data Bus Low-level input voltage V IL — — 0.8 V High-level input voltage VIH 2.0 — — V Low-level output voltage (IOL = 1.6 mA) VOL — — 0.4 V High-level output voltage (IOH = 400 mA) VOH 2.4 — — V Input leakage current (VIN = 0.4 to 2.4 V) IIZ — — 10.0 mA All voltages referenced to VSS unless otherwise noted.VDD = 5.0 V – 5% ;fC = 3.579545 MHz ;TA = -40°C to +85°C, unless otherwise noted. *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. Table 11 DC Characteristics BIT Name Status Flag Set Status Flag Cleared b0 IRQ Interrupt has occurred. Bi tone (b1) and/or bit 2 (b2) is set. Interrupt is inactive. Cleared after status register is read. b1 Transmit data register empty (burst mode only) Pause duration has terminated and transmitter is ready for new data. Cleared after status register is read or when not in burst mode. b2 Receive data register full Valid data is in the receive data register. Cleared after status register is read. b3 Delayed steering Set on valid detection of the absence of a DTMF sig- nal. Cleared on detection of a valid DTMF signal. Table 9 Status Register Description Parameter Symbol Value Power supply voltage (VDD -V SS ) VDD + 6.0 V max Voltage on any pin Vdc VSS -0.3 V to VDD + 0.3 V Current on any pin IDD 10 mA max Operating temperature TA -40°C to +85°C Storage temperature TS -65°C to +150°C Note:Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. Table 10 Absolute Maximum Ratings

40-406-00012, Rev. G www.clare.com Page 8 PARAMETER SYMBOL MIN TYP* MAX UNITS Receive signal conditions Valid input signal levels (each tone of composite signal; Notes 1, 2, 3, 5, 6, 9) -29 27.5 869 dBm mV RMS Positive twist accept (Notes 2, 3, 6, 9) — 6 dB Negative twist accept (Notes 2, 3, 6, 9) — 6 dB Frequency deviation accept (Notes 2, 3, 5, 9) ± 1.5% ± 2 Hz — — Nom. Frequency deviation reject (Notes 2, 3, 5) – 3.5% — — Nom. Third tone tolerance (Notes 2, 3, 4, 5, 9, 10) — -16 — dB Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10) — -12 — dB Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11) — +22 — dB Call progress Lower frequency (@ -25 dBm) accept f LA — 320 — Hz Upper frequency (@ -25 dBm) accept fHA — 510 — Hz Lower frequency (@ -25 dBm) reject fLR — 290 — Hz Upper frequency (@ -25 dBm) reject fHR — 540 — Hz Receive timing Tone present detect time t DP 5 11 14 m s Tone absent detect time tDA 0.5 4 8.5 ms Tone duration accept (ref. Figure 12) tREC — — 40 ms Tone duration reject (ref. Figure 12) tREC 20 — — ms Interdigitpause accept (ref. Figure 12) tID — — 40 ms Interdigitpause reject (ref. Figure 12) tDO 20 — — ms Delay St to b3 tPStb3 — 13 — ms Delay St to RX O —RX 3 tPStRX — 8 — ms Transmit timing Tone burst duration (DTMF mode) t BST 50 — 52 ms Tone pause duration (DTMF mode) tPS 50 — 52 ms Tone burst duration (extended, call progress mode) tBSTE 100 — 104 ms Tone pause duration (extended, call progress mode) tPSE 100 — 104 ms Tone output High group output level (R L = 10 kW ) VHOUT -6.1 — -2.1 dBm Low group output level (RL = 10 kW) VLOUT -8.1 — -4.1 dBm Pre-emphasis (RL = 10 kW) dBP 0 2 3 dB Output distortion (RL = 10 kW , 3.4 kHz bandwidth) THD — -25 — dB Frequency deviation (f = 3.5795 MHz) fD — ± 0.7 ± 1.5 % Output load resistance R LT 10 — 50 kW Microprocessor interface f 2 cycle period t CYC 0.5 — — ms f2 high pulse width tCH 200 — — ns f2 low pulse width tCL 180 — ns f2 rise and fall time tR ,tF — — 25 ns Address, R/Whold time tAH ,tRWH 10 — — ns Address, R/Wsetup time (prior to f2) tAS ,tRWS 23 — — ns Table 12 AC Characteristics

40-406-00012, Rev. G www.clare.com Parameter Symbol Min Typ* Max Units Microprocessor interface (continued) Data hold time (read) tDHR 22 — — ns f2 to valid data delay (read) (200 pF load) tDDR — — 150 ns Data setup time (write) tDSW 45 — — ns Data hold time (write) tDHW 10 — — ns Input capacitance, D0—D3 C IN — 5 — pF Output capacitance,IRQ/CP C/OUT — 5 — pF DTMF clock Crystal clock frequency fC 3.5759 3.5795 3.5831 MHz Clock input rise time (external clock) tLHCL — — 110 ns Clock input fall time (external clock) tHLCL — — 110 ns Clock input duty cycle (external clock) DC CL 40 50 60 % Capacitive load, OSC2 C LO — — 30 pF All voltages referenced to unless otherwise noted.VDD = 5.0 V – 5% ;VSS = 0 V;fC = 3.579545 MHz; TA = -40°C to +85°C *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. Notes: 1. dBm = decibels above or below a reference power of 1 m W into a 600 W load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40 ms. Tone pause = 40 ms. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. The tone pair is deviated by – 1.5% – 2 Hz. 7. Bandwidth limited (3 kHz)Gaussian noise. 8. The precise dial tone frequencies are 350 and 440 Hz (– 2%). 9. For an error rate of less than 1 in 10,000. 10. Referenced to the lowest amplitude tone in the DTMF signal. 11. Referenced to the minimum valid accept level. Table 12 AC Characteristics (continued) Parameter Symbol Min Typ* Max Units Input leakage current (VSS £ VIN £ VDD ) IIN — 100 — nA Input resistance R IN — 10 — M W Input offset voltage VOS — 25 — m V Power supply rejection (1 KHz) PSRR — 60 — dB Common mode rejection (-3.0 V £ VIN £ 3.0 V) CMRR — 60 — dB DC open-loop voltage gain AVOL — 65 — dB Unity gain bandwidth BW — 1.5 — MHz Output voltage swing (RL ‡ 100 KW to VSS ) VO — 4.5 — VPP Maximum capacitive load, GS C L — 100 — pF Maximum resistive load, GS R L — 50 — KW Common mode range (no load) VCM — 3.0 — VPP All voltages referenced to unless otherwise noted.VDD = 5.0 V;VSS = 0 V; TA = 25°C *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. Table 13 Electrical Characteristics - Gain Setting Amplifier

40-406-00012, Rev. G www.clare.com Explanation of Events (A) Tone bursts detected, tone duration invalid,R X Data Register not updated. (B) Tone #n detected, tone duration valid, tone decoded and latched in R X Data Register. (C) End of tone #n detected, tone absent duration valid,R X Data Register remain latched until next valid tone. (D) Tone #n + 1 detected, tone duration valid, tone decoded and latched in R X Data Register. (E) Acceptable dropout of tone #n + 1, tone absent duration invalid,R X Data Register remain latched. (F) End of tone #n + 1 detected, tone absent duration valid,R X Data Register remain latched until next valid tone. Explanation of Symbols V IN DTMF composite input signal. ESt Early steering output. Indicates detection of valid tone frequencies. St/GT Steering input/guard time output. Drives external RC timing circuit. RX 0-RX3 4-bit decoded data in receive data register. b3 Delayed steering output. Indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid DTMF signal. b2 Output enable (input). A low level shifts Q1 - Q4 to its high impedance state. IRQ /CP Interrupt is active indicating that new data is in the R X data register. The interrupt is cleared after the status register is ready. tREC Maximum DTMF signal duration not detected as valid. tREC Minimum DTMF signal duration required for valid recognition. tID Minimum time between valid DTMF signals. tDO Maximum allowable dropout during valid DTMF signal. tDP Time to detect the presence of valid DTMF signals. tDA Time to detect the absence of valid DTMF signals. TGTP Guard time, tone present. tGTA Guard time, tone absent. Figure 13 Timing Diagrams

40-406-00012, Rev. G www.clare.com Figure 14 Package Dimensions Tolerances Inches Metric (mm) Min Max Min Max A .093 .104 2.35 2.65 A1 .004 .012 .10 .30 b .013 .020 .33 .51 D .496 .512 12.60 13.00 E .291 .299 7.39 7.59 e .050 BSC 1.27 BSC H .394 .419 10.00 10.65 L .016 .050 .40 1.27 Tolerances Inches Metric (mm) Min Max Min Max A .210 5.33 A1 .015 .38 b .014 .022 .36 .56 b2 .045 .070 1.14 1.78 C .008 .014 .20 .36 D .980 1.060 24.89 26.92 E .300 .325 7.62 8.26 E1 .240 .280 6.10 7.11 e .100 BSC 2.54 BSC ec 0° 15° 0° 15° L .115 .150 2.92 3.81

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Tel: 49 8459 3214 10 Fax: 49 8459 3214 29 Italy Via C. Colombo 10/A I-20066 Melzo (Milano) Tel: 39-02-95737160 Fax: 39-02-95738829 Sweden Clare Sales Comptronic AB Box 167 S-16329 Spånga Tel: 46-862-10370 Fax: 46-862-10371 United Kingdom Clare UK Sales Marco Polo House Cook Way Bindon Road Taunton UK-Somerset TA2 6BG Tel: 44-1-823 352541 Fax: 44-1-823 352797 Specification: 40-406-00012, Rev. G © Copyright 2000, CP Cla re Corporation d/b/a Cla re All rights reserved. Printed in USA. 07/28/00 Clare cannot assume responsibility for use of any circuitry other then cir- cuitry entirely embodied in this Clare product. No circuit patent licenses nor indemnity are expressed or implied. Clare reserves the right to change the specification and circuitry, without notice at an y time. The products de- scribed in this document are not intended for use in medical implantation or other direct life support a pplications where malfunction may result in direct physical harm, injury or death to a person. ASIA PACIFIC Asian Headquarters Clare Room N1016, Chia-Hsin, Bldg II, 10F, No. 96, Sec. 2 Chung Shan North Road Taipei, Taiwan R.O.C. Tel: 886-2-2523-6368 Fax: 886-2-2523-6369 http://www.clare.com