M6M80011

M6M80011 MITSUBISHI | Alldatasheet

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M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM

DESCRIPTION

: The M6MBO011AP, L, FP are 1024-bit (64-word x 16- | PIN CONFIGURATION (TOP VIEW) bit) electrically erasable CMOS EEPROMs, and all have a cue sevect ain his oe input CS=T] [8] Voo(sv) built-in high voltage generator to enable operation in all clock Pur ScR—=[] 2 ye mower BUSY modes by a single 5V power supply. cata wrur pie] 2 ijeaeoer one” \\ The difference between M6M80011AP, M6M80011AL cam ourtor bo : Bu" and M6M80011AFP is only outline of package, and the a Vaal0v: following explanations are for M6M80011AP unless spe- Outline 8P4 cifically indicated otherwise. oof Do =| FEATURES (OVIVs5 3 © Single 5V power supply se- & © Clock synchronous serial I/O wee & © Three ports control (CS and RESET, DI and DO can be own AS interconnected.) aon © Built-in sequential controller nest oH © 100000 erase/write cycles @ 10 years data retention Outline 8P5K APPLICATION s-W Voo(5¥) M6M800114 is especially suitable for use as a nonvolatile Sck—[2} =~ [8] roveusy channel memory for electronic tuner and as the read only” ne =s Bf xe memory system that must be frequently reprogrammed in o~ Gal > — RESET ° the field. co~(5] a {8} vastow) Outline 10P2N-A NC: NO CONNECTION BLOCK DIAGRAM DATA CLOCK CHIP DATA OUTPUT INPUT INPUT SELECT INPUT bo Dl SCK tS |HAMMING CODE] DATA INPUT [| | circuit 8 TEMORY CELL ARRAY | ouTeur DATA SENSE 64x 16 BIT "ADDRESS. MODE CLOCK secrcrenpJoORRECTI Sie caxber PO] uate tO | area | JOsciitaring ‘ (HAMMAN CODE) ice a5 WRONTROL Foo] oscit GENERATOR conenoe LATOR ! MODE CONTROL cincurt Vse(0V) Voo(5V) RDY/BUSY RESET BUSY OUTPUT RESET INPUT ' M™ 6249825 0026103 SbT

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M6MS80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM FUNCTIONS M6M80011AP is a clocked serial port compatible EEPROM, Any of five modes (write, read, write enable, write and data is input from the rising edge of clock signal and disable, status output) may be specified. The write time is output by synchronizing to the falling edge of clock signal. set by an internal timer, and determination of whether Data is grouped by 8 bits. The beginning 8 bits specify write operation is in progress or not can be made from the mode, next 8 bits specify the address, and subsequent status of the RDY/BUSY pin or the DO pin status after 16 bits specify the I/O data. the status mode has been set. PIN DESCRIPTION a Name Z Functions : © @ Chip selection is made by setting this pia to “L”. When this port is “H, the internal sequential controller | isreset, Therefore, this pin must be set to "H" betore executing each mode @® During the write operation (when BUSY output is “L."), write operation is continued regardless of the input az ip select inpu to thispin cs Chip select input @ Alter write operation is finished, tis pin must be set to “"H" to make mode reading possible. Inthe case of “status output” mode only, reading is possible even if this pin is “L” after the sequential controller has boon reset and tsra has elapsed since the time when the write operation was started. SOK clock D Input data is read at the rising edge of clock ° lock input ® ata is output by synchronizing to the falling edge of clock. Data input Data is input from this pin. _ Data output Data is autput from this pin. Di and DO ean be interconnected @ Must be set to "H” at the time of power ON or OFF. @® When this pin is set to "H”, the sequential controller and the write circuit are reset for memory protection, If this pin becomes“ during write operation, the operation is halted RESET ® This pin and CS can be interconnected. When this is done, CS (RESET) must be held to “L" during write operation nov/suey| a D this" auingwiieopeation SSS BUSY | Busy output ® This is “L” at the time of power ON or OFF. In this condition, all inputs ere disabled. MODE FUNCTIONS [fore ode fairs aT | fea | 10101000 AoA Aza AdAs00 Do~DrDy~Dis 10100100 ‘AoA AcAaaAs00 Do~DrDe~Dis [—writeenabie | too00n1 | xxx PT Write operation is enabled.

10100000 XXX = Write operation is disabled

OOXXXXXX 0 usy! Busy flag _ 1 (Ready) . I 0 (Enable) tat itput 10101001 i VOXXXXXX_ TiDiabie) Write enable flag 0 (Correct) OTXXXXXX ECC tag 1 (incorrect) M@™ 6249825 0028104 4Tb

M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM OO LT OCR AMMABLE ROM STATUS OUTPUT MODE (1) Busy flag (3) ECC flag The busy flag serves the same function as the BUSY output An ECC circuit, which corrects data errors, is built-in to pin. insure high degree of memory cell reliability. The ECC When this flag is specified, “1 is output when ready circuit corrects data errors and outputs the corrected error from the 16 clock falling edge and “0” is output if busy __if there is only one error each in the high-order 8 bits and (write operation in progress). the low-order 8 bits of 1 word (16 bits). When an error is : corrected in at least one of the high-order or low-order . (2) Write enable flag byte, this flag is set to “1” to indicate that error correction M6M0011AP has a write enable flag, and write operation is has been made. The data is corrected in this case. When executed only when this flag is “0”. The contents of this this flag is “0”, it indicates that the correct data value was flag can be updated only in the write enable (WEN) mode —_ output without having to active the ECC circuit. By setting and the write disable (WDS) mode, The contents of this the ECC mode after the read mode, ECC information on flag is underfined at the power on time, so that the WEN the address that was specified immediately before can be mode must be set before setting the write mode for write —_varified. operation. Once the WEN mode is set and this flag is set to the enable state, latch is in effect until the WDS mode is set. ‘ EEPROM can be read regardless of the status of this flag. ABSOLUTE MAXIMUM RATINGS Parameter Suppty votrage po 036.0 | vi Input voltage p03 ~vo0t03 [| a ee | Flow |_| Hisevel output current a (7 ee a ae eS RECOMMENDED OPERATING CONDITIONS ( Ta=—10~706, Voo=5V+10%, unless otherwise noted) Voo Supply voltage - pees feet Vin Highevel input voltage Di 0.7Vo0| Voo_| Voo High lve input voltae RESET, CS, SOK mel ve Te Vv Low level input vottoge BT x) eee Lowlevel input voltage RESET, CS, SCK [0 | 0 |0.2ven) Vv DC ELECTRICAL CHARACTERISTICS Veo Supply voltage - ra 5.5 v Vin High-level input voltage DI Voo Vv High-level input voltage RESET, CS, SCK v Cow-level input voltage RESET, C5, SCK _ —— 0.2Ve0] Vv Vou Highiewlouiputwolteae «dg 00 A a 7 Vou | Lovie! output vottage lo=zimA bet v eee ; @™ 6249825 0028105 332 MITSUBISHI ate TBS 3-5

M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM OO AC ELECTRICAL CHARACTERISTICS p “Tea conait Carts 7 Symbat ameter 7 fest conditions : tee [ome] tone Positive data shitt clock pulse width _ 450 [ns tre Negative clock pulsewidth 450 ns te Clock Poa tne every @ clocks pl a tevrca-scx | CMD lect setup tie before te a of he clock | (fe | tnecaccs) | CMPS#ECC Rod time afer the seo he clack L «| Dba up tine beore the ise ofthe cork jw | tnsox-on | Date old time after ters of the clock [= | teucece.cs) | Clock set up time before the fall of the chip select ys ‘eo Daa delay time attr the fal ofthe clock ae 1s fe | Data valid ie after thei ofthe chip sae | fs | [cm | Sittinewiie sameness [tcsn | Posivechipswiet with as Chip select, clock hold time after the start of the write sequence us ‘At setting status mode, clock hold time start of Note 1. ts7a indicates the maximum value of the sequential controller reset pulse that is generated after the write operation is sterted When the sequential controller is reset, only the status output can be rea. NONVOLATILE CHARACTERISTICS 3H Parameter est conditions ni one Tetons one Erase/Wiie cycle por word ws |_| | evores Ee WM 6249825 0028106 279 a ¢ MITSUBISHI 3-6 ELECTRIC

M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM TIMING DIAGRAMS (1) Synchronizing data 1/0 timing tes = =| “ se " XK] | a a aa, Fig. 1 Synchronizing timing (2) SCK “H" hold time at every 8 clocks The timing pattern shown above is maintained during transfer of 8-bit data, but the clock “H” hold time twwn is necessary at every 8th clock for SCK input in all modes. M@ 6249825 0028107 105 ¢ MITSUBISHI ELECTRIC 3-7

M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM TIMING CHART for VARIOUS MODES (1) When controlling CS and RESET pins © Write enable and write disable mode H RESET |< oy twwn cs SE so OC" 16 L y 8 H oo of Loo of Tx]xTx]x Px fx PT) Hi-Z Do oH RDY/BUSY L . Ve WRITE ENABLE Fig. 2 Sequence at write enable and write disable modes © Status output mode H 4 town twwh cs — u SOK i l 8 l 16 l H mt Lo Loft Leo Ty PP Px PT x] H Hi-Z (00. BUSY FLAG O-- BUSY STATUS Js READY STATUS 1O-WRITE ENABLE — Q--- ENABLE STATUS. FLAG VDISABLE STATUS Ole ECC FLAG Q+-CORRECT DATA TesINCORRECT DATA Fig. 3 Sequence at status output mode The status of each status flag specified from the DO pin is output starting at the rising edge of the 16th clock. Output is not dependent on clock but continues until CS becomes M@@ 6249825 0028108 041

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M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM @ Read mode H RESET tc_~=reee— OO : = Hl twwh twwh tanh — H SOK, 1 8 16 24 32 Heewee ol L TLof Loft ]_o oo [al Jojo H co | RDY/BUSYK{—— — L Fig. 4 Sequence at read mode © Write mode : H RESET — _ 4 twwh twwh twwh es - L — H SCK L a J 8 16 J 24 He---- oT TloPleofi Loo [al To] o fol, To Jor Tod Hi-Z oo HE RDY/BUSY H ee as | a L Fig. 5 Sequence at write mode Execution of the write operation starts at the rising edge of write operation, GS should be set to “H” as shown in the 32nd clock. _ Figure 6 (even is CS is held to “L", SCK can be used by During the write operation, the CS input value may be other tasks if a dummy bit input is performed as shown in either “H” or “L". If the CS pin is held to “L during the Figure 10). _ write’ operation, the read operation is possible only in the To read next mode after te»w, CS must be set to “H’ status mode. first. Thus, the SCK is to be used for other tasks during the ' M@™ 6249825 0028109 Tah MITSUBISHI ees 3-9

M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM RESET os = H twwh twwh, twwh, tree Lt — H 5K f 8 16 24 32 BOY Honwn-- SKS oF elo oo Lal H Hi-Z DO L OS lew RDY/BUSY ee a Fig. 6 Sequence at write mode To use SCK and DI for other tasks during the write ope- ration, CS must be set to “H” after thy has elapsed from the rising edge of the 32nd clock as shown in Figure 6. H RESET [es i i h tsra SCK t l J 32 l 1 16 1 16 l H ween eee, we enna -- ee =e 2+ weeenee ae eee eee ee ee DL L Grats ourru] Gratis oureuq] Cc bo H Hi-Z Hi-Z Hi-Z a on rr: a J — terw —— _ ~ RDY/BUSY | t Fig. 7 Sequence of status output (busy flag) during the write operation After write operation has started, the sequential con- troller is reset automatically, so read operation in the status mode become possible only after tsa has elapsed from the time the write operation started without having to set CS to "H”, Before the status mode is set again, CS must be set to “Has in the ordinary mode setting procedure. Wi 6249625 0028110 7TT MITSUBISHI 3-10 wales

| M6M80011AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM 000 (2) When connecting between CS and RESET pins @ Write mode (ESET x Rl L _— H cs L — H: SOK L 1 mua 8 we L a L 32 He---- earerncas oI i oft Lo ofiLoo [al To] o fol Pi PSBRBSOowrore H Hi-Z bo .—— ter RDY/BUSY H L LJ Fig. 8 Sequence of write operation During the write operation, the CS=RESET pin must be set to “L”. Because the read operation is possible only in the status mode once the write operation starts as described above, SCK must be held to “H” when not setting the status mode. For using SCK and DI for other tasks during the write operation, see Figure. 10. H RESET L _ H i oe cs L H SCK L 1 32 J 8 16 l l | He---=4 a Dr L WRITE iLofilofifoo] 1 loo x H do Pr fr t teww _ H RDY/BUSY | L Fig. 9 Sequence of status output during write operation The read operation in the status mode becomes possible after tea has elapsed from the time the write operation started. Attention is called to the fact, when the status mode is set, the DO pin is in the output state until CS is set to “H”. WM 4249825 0028111 b3b

M6MS800114AP,L,FP 1024-BIT(64-WORD BY 16-BIT) ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM H RESET L = H cs L : 4 ira — COCCCCCCOCCOCOOOO OS BK, 2 LEESON Henne eit SILI LIK a waite OCMC OO H DO iw ™m—_— TST eee tei —— 4H RDY/BUSY a Ca Fig. 10 Sequence of write operation ‘As shown in Figure 9, the read operation in the status mode becomes possible after tera has elapsed from the time the write operation started, and the DO pin is set to the output state when the status mode is set. When using the DO pin is addition to the SCK and DI pins for other tasks, a dummy bit input must be made after tsrq has elapsed from the time the write operation started to avoid the status mode before executing the other tasks. Other (than dummy bit) data input is equally effective for this purpose as long as it does not generate the status mode instruction code (10101001). @™ 6249825 O0edlle 572 MITSUBISHI 3-12 we Mes