M69897VP MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The M69897VP multiplexer chip is an integrated serialization SONET OC-48 (2.488 Gbps) interface device. The chip performs parallel-to-serial functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based ATM applications. The merits of SOI (Silicon-On-Insulator) technology, such as low voltage operation, low substrate noise and good compatibility with standard CMOS technology, are fully utilized in the chip design to achieve low jitter and low power operation and small package outline of 64-pin PQFP.

FEATURES

  • Single 1.8 V power supply - Supports 2.488 Gbps (OC-48, STM-16) - 16-bit single-ended PECL interface - On-chip high-frequency PLL for clock generation - 155.52 MHz reference frequency - Low power consumption - Available in 64 PQFP - Parity check function

APPLICATIONS

  • SONET/SDH systems - Fiber optic systems - High-speed back plane interconnect and point-to-point data links MITSUBISHI SEMICONDUCTOR <SOI/CMOS> M69897VP 16:1 2.488 Gbps Multiplexer Preliminary MITSUBISHI ELECTRIC December 20001 Figure 1 Functional Block Diagram 16:1 PARALLEL TO SERIAL TIMING GENERATOR D-FF PARITY CHECK SDOP/SDON SCLKOP/ SCLKONPCLKOP/ PCLKON PDI[15:0] PARITYI PARIERRO

2.488 Gbps

2.488 GHz

155.52 MHz

155.52 Mbps

SCLKIN 2.488 GHz PCLKIP/ PCLKIN SELPLL

155.52 MHz PLL

2 LPF_EXT1/

LPF_EXT2

MITSUBISHI ELECTRIC December 20002 Table 1 Absolute Maximum Ratings PARAMETER MIN TYP MAX UNITS Storage Temperature Voltage on VDD with Respect to GND Voltage on any PECL Pin ESD Rating (HBM model) -65 -0.5 1000 150 2.2 2.2 ûC V V V Table 3 Differential PECL Input DC Characteristics SYMBOL MIN TYP MAX UNITS VIL Input Low Voltage GND 0.2 VDD -1.4 VDD -0.8 1.1 V ÆVINDIFF Input High Voltage Differential Input Voltage Swing VDD -1.2 CONDITIONS V V Table 5 CMOS Input DC Characteristics Table 6 Differential PECL Output DC Characteristics SYMBOL MIN TYP MAX UNITS VOL Output Low Voltage GND 0.7 0.1 VDD -0.8 1.1 V ÆVOUTDIFF Output High Voltage Differential Output Voltage Swing VDD -0.9 CONDITIONS V V SYMBOL MIN TYP MAX UNITS VIL Input Low Voltage GND VDD VIH Input High Voltage VDD -0.5 CONDITIONS V V VDD -1.3 Table 7 Single-Ended PECL Output DC Characteristics SYMBOL MIN TYP MAX UNITS VOL Output Low Voltage GND 0.7 0.1 VDD -0.8 1.1 V ÆVOUT Output High Voltage Output Voltage Swing VDD -0.9 CONDITIONS V V Table 4 Single-Ended PECL Input DC Characteristics SYMBOL MIN TYP MAX UNITS VIL Input Low Voltage GND 0.4 VDD -1.5 VDD -0.8 1.1 V ÆVIN Input High Voltage Input Voltage Swing VDD -1.1 CONDITIONS V V See Figure 12. See Figure 12. See Figure 12. See Figure 12. Table 2 Recommended Operating Conditions PARAMETER MIN TYP MAX UNITS Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on VDD with Respect to GND Power Consumption 1.71 110 1.89 ûC V mW 1.8 ûC 310260 mW420320 CONDITIONS All Outputs Unterminated. All Outputs Terminated.

MITSUBISHI ELECTRIC December 20007 VH VL Differential Swing = VH - VL VH VL Single-Ended Swing = VH - VL Figure 12 Voltage Swing Table 9 AC Characteristics PCLKIP PDI[15:0] TDH TDS Figure 13 Input Timing (SELPLL = "H") SYMBOL MIN MAX UNITS Serial Clock Rate Parallel Data Setup Time wrt PCLKIP Parallel Data Hold Time wrt PCLKIP Parallel Data Setup Time wrt PCLKOP Parallel Data Hold Time wrt PCLKOP Serial Clock Output Rise and Fall Time 1 TDS TDH TDS2 1.0 ns ns ns 1. 20% - 80% TYP TDH2 Parallel Clock Input Duty Cycle Parallel Clock Output Duty Cycle Serial Clock Output to Serial Data Output Delay Serial Data Output Rise and Fall Time 1 Parallel Clock Input Rise and Fall Time 1 Parallel Data Input Rise and Fall Time 1 Parallel Data Input and Parity Input Skew 1.0 1.0 1.0 -50 100 120 1.0 2.0 1.5 ns ps ps ps ns ns ns

MITSUBISHI ELECTRIC December 20009 Table 13 Common Pin Assignment Table 11 Parity Check Condition PARITYI # of "High"s in PDI[15:0] High High Low Low Even Odd Even Odd PARIERRO High Low Low High Table 12 PDI Pin Assignment PIN NAME PDI0 PDI1 PDI2 PDI3 PDI4 PDI5 PDI6 PDI7 PIN # PIN NAME PDI8 PDI9 PDI10 PDI11 PDI12 PDI13 PDI14 PDI15 PIN # 0.02 µF LPF_EXT1 LPF_EXT2 Figure 16 External Loop Filte PIN NAME DESCRIPTIONLEVEL VDD 1 PIN # VDD 2 GND 1.8 V 1.8 V GND 1, 14, 15, 17, 63 28, 31, 33, 36, 42, 44, 46, 50 35, 39, 43, 45, 48, 49, 64 Core power supply. I/O power supply. Ground. ANAGND GND ANAVDD 1.8 V 25 23, 24 Analog power supply. Analog ground.