M67130

M67130 TEMIC | Alldatasheet

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© Fast access time © BUSY input flag on slave 35 ns to 55 ns © INT flag for port to port communication 30 ns preliminary for commercial only © Fully asynchronous operation from either port © 67130L/671401 low power © Battery backup operation : 67130V/67 40V very low power 2-V data retention © Expandable data bus to 16 bits or more using master/slave ‘TTL compatible devices when using more than one device. © Single SV + 10 % Power Supply (1) © On chip arbitration logic © BUSY output flag on master 33 V versions are also available, Please consult sales. MATRA MHS 1 Rev. F (11 April. 97)

M67130/M67140 Semiconductors Interface Block Diagram a, mi Hi, ni. Et i CS “ on CF — oe, As r vay y i esto FE ees wa [Ta me Ox : je Tio cont] coe T| 7 wo, set 0 0 st 2 om ive A z Row, MEWORY TOW ee “oe ee ar) ARBITRATION 7 Ag Aa AND An os. INTERRUPT Se ain Loaic RW Wis Tite Notes +1. M67130 (MASTER) : BUSY is open drain output and requires pullup resistor M 67140 (SLAVE) : BUSY in input 2. Open drain output requires pull up resistor Pin Configuration

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2 MATRA MHS

Rev. F (11 April. 97)

Semiconductors M67130/M67140 Pin Names The BUSY flags are required when both ports attempt to access the same location simultaneously.Should this conflict arise, on-chip arbitration logic will determine which port has access and set the BUSY flag for the =i <3 inhibited port. BUSY is set at speeds that allow the ‘and data, It should be noted that the operation is invalid for the port for which BUSY is set LOW. The inhibited port will be given access when BUSY goes inactive. A conflict will occur when both left and right ports are TST Nik Tnterrupt Flag active and the two addresses coincide. The ‘on-chip Vee Power arbitration determines access in these circumstances. — Two modes of arbitration are provided : (1) if the addresses match and are valid before CS on-chip control logic arbitrates between CS;, and CSp for access ; or (2) 7 . eas if the TSs are low before an address match, on-chip Functional Description control logic arbitrates between the left and right . addresses for access (refer to table 2). The inhibited port’s ue Sn a ad ri indent BUSY flag is set and will reset when the port granted r sree ty a . sath «: Sa access completes its operation in both arbitration modes. read/write access to any memory location. These devices have an automatic power-down feature controlled by CS. TS controls on-chip power-down circuitry which causes Data Bus Width Expansion the port concerned to go into stand-by mode when not as selected (CS high). When a port is sclected access to the Master/Slave Description full memory array is permitted. Each port has its own Expanding the data bus width to 16 or more bits in a Output Enable control (OE). In read mode, the port’s OE dual-port RAM system means that several chips may be turns the Output drivers on when set LOW. active simultancously. If every chip has a hardware Non-conflicting READ/WRITE conditions are arbitrator, and the addresses for each chip arrive at the illustrated in table 1. same time one chip may activate its L BUSY signal while another activates its R BUSY signal. Both sides are now Interrupt Logic busy and the CPUs will wait indefinitely for their port to ‘The interrupt flag (INT) allows communication between become Iree. ports or systems, If the user chooses to use the interrupt To overcome this “Busy Lock-Out” problem, MHS has function, a memory location (mail box or message center) developed a MASTER/SLAVE system which uses a is assigned to cach port, The left port interrupt flag (INT) _ single hardware arbitrator located on the MASTER. The is set when the right port writes to memory location 3FE — SLAVE has BUSY inputs which allow direct interface to the (HEX). The left port clears the interrupt by reading MASTER with no extemal components, giving a speed address location 3FE. Similarly, the right port interrupt advantage over other systems. flag (NTR) is set when the left port writes to memory When dual-port RAMs are expanded in width, the location 3FF (hex), and the right port must read memory SLAVE RAMs must be prevented from writing until the location 3FF in order to clear the interrupt flag (INTR). | BUSY input has been settled. Otherwise, the SLAVE chip The 8 bit message at 3FE or 3FF is user-defined. If the — may begin a write cycle during a conflict situation, On the interrupt function is not used, address locations 3FE and —_ opposite, the write pulse must extend a hold time beyond 3FF are not reserved for mail boxes but become part of the — BUSY to ensure that a write cycle occurs once the conflict RAM. See table 3 for the interrupt function. is resolved. This timing is inherent in all dual-port memory systems where more than one chip is active at the Arbitration Logic same time. The arbitration logic will resolve an address match or a ‘The write pulse to the SLAVE must be inhibited by the chip select match down to a minimum of 5 ns and MASTER’s maximum arbitration time. If a conflict then determine which port has access, In all cases, an active — occurs, the write to the SLAVE will be inhibited because BUSY flag will be set for the inhibited port. of the MASTER’s BUSY signal. MATRA MHS 3 Rev. F (11 April. 97)

M67130/M67140 Semiconductors Truth Table Table 1: Non Contention Read/Write Control LEFT OR RIGHT PORT? TONGIiON ae a Port Disabled and in Power Down Mode. ICCSB or ICCSB1 a a ET [ites spe] Notes: 1. Aoi Agi # Aor Aog:

2 IF BUSY = L, data is not written

1. IF BTISY = 1, data may not he valid, see two and topo timing 4. 1= HIGH, L= LOW, X = DON’T CARE, Z = HIGH IMPEDANCE ‘Table 2: Arbitration LEFT PORT RIGHT PORT FLAGS (5) ae ot ee ee FUNCTION WY, [ate H x H x No Contention L Any H x No Contention a ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH ‘CS ARBITRATION WITH ADDRESS MATCH BEFORE CS Rist | Aon Ao [RLSL [ =Ao An [ [KTR Ponwins LWSR bwsr [AoA [oH [| Arbitration Resolved [wate] ag An wa antag aia Red Notes: 5. INT Flags Don't Care. 6. X ~ DON'T CARE, L~ LOW, H ~ HIGH LVSR = Left Address Valid > 5 ns before right address RVSL.~ Right Address Valid 2 5 ns before let address. Same = Left and Right Addresses match within 5 ns of each other. LLSR = Left CS = LOW 2 5 ns before Right CS. RLSL = Right CS = LOW > 5 ns before lefi CS. LWSR = Left and Right CS ~ LOWwithin 5 ns of each other. Table 3: Interrupt Flag 7-19 LEFT PORT RIGHT PORT UincHod Aor-As, [INTL [RW | CSe | OFe | Aon Ave Set Right TNTe Fag Lx [Te Pe [we Pwe Px [ox [x [xT x [Reser tet IT Hae Notes: 7, Assumes BUSY), - BUSY, — H. 8. If BUSY, = L, then NC 9. If BUSY = L, then NC. 10. Hl = HIGH, L.= LOW, X = DON’T CARE, NC = NO CHANGE.

4 MATRA MHS

Rev. F (11 April. 97)

Semiconductors M67130/M67140

Electrical Characteristics

Absolute Maximum Ratings * Notice Stresses greater than those listed under ABSOLUTE MAXIMUM Supply voltage (VCC-GND) : 03Vto7.0V RATINGS may cause permanent damage to the device.This is a stress Input or output voll lied: ... (GND 03 V)to(VCC 40.3 Vy Mlitig only and functional operation of the device at these or any other “ipa or ouput veliage PP “ rom «conditions above those indicated in the operational sections of this conditions for extented periods may affect reliability. OPERATING RANGE OPERATING SUPPLY VOLTAGE OPERATING TEMPERATURE DC Parameters 67130/140-30 | 67130/140-3s | 67130/140-45 | 67130/140-5s Versio IND IND IND | Uni mina: ‘Unit |Value| i ons "Y | com | MIL MIL | COM) MIL AUTO AUTO AUTO Tcespaiy | Standby supply current Vv 5 s {5s [5s [5 | 5 | 5 |ma|Max (Both ports TTL level inputs) L 40 40 | so | 40 | 50 | 40 | $0 | mA | Max eespi (12) | Standby supply current Vv 100 100 | 200 | 100 | 200 | 100 | 200 | wa [Max (Both ports CMOS level inputs) L 19000 1000 | 2000 | 1000 | 2000 | 1000 | 2000 | wA_| Max lecop (13) | Operating supply current v 160 145 180 135 150 130 140 | mA | Max (Both ports active) L 175. 155 200 150 170 M0 170_| mA | Max Tecopt (14) | Operating supply current Vv 100 35 | 100 | 75 | 35 | 70 | 75 | ma [Max (One port active ~ One port standby) L 105 95 | uo | 85 | 90 | 80 80 | mA | Max Notes: 11. CS, = TSR 22.2 V. 12. Sy, =CSp2 VCC -02V. 13. Both ports active - Maximum frequency — Outputs open — OE = VIH. 14, One port active (f = (MAX) ~ Outpat open — One port stand-by TTL or CMOS Level inputs ~CS,, = CSg 22.2 V. 67130-30/35/45/55 PARAMETER DESCRIPTION db abedeee VALUE VOL Open drain output low voltage 0s Vv Max (BUSY, INT) lox = 16 mA Notes: 15. Voc = 5.5 V, Vin = Gnd to Veg, CS = VIH, Vout = 0 t0 Veg. 16, VIH max = Vec + 0.3 V, VIL min — 0.3 V or 1 ¥ pulse width 50 ns. 17. Voc min, IOL = 4 mA, IOH =-4 mA. MATRA MHS 3 Rev. F (11 April. 97)

mind. Data retention voltage and supply current are — during the power up and power down transitions. data retention: reaches the minimum operating voltage (4.5 volts). retention ; within Vec to VCCpr. Notes: 18. CS = Vee, Vin = Gnd to Vee. Figure 1. Output Load. Figure 2. Output load.

775 Spr

6 MATRA MHS

Semiconductors M67130/M67140 AC Parameters PARAMETER UNIT 23) 4 PRELIMINARY [ravev [ins | atiowasontie sf wo | | ww | | [rey ns [orsianenimen [| |- «| #[m| [rae [ne | Oaracnticacenine fis | | ws f= | ae Law [ww | insiaaionmermiman [of |e» | w| [mp [wm | cripaisnicroroveraowntinean | — 0 | | | | | Notes: 20. ‘Transition is measured + 500 mV from low or high impedance voltage with load (figures 1 and 2). 21. ‘This parameter is guaranteed but not tested. 22. To access RAM CS = VIL. 23. STD symbol. 24. ALT symbol. ). Commercial only, not available in DIP (**). DIP package available for commercial only. Timing Waveform of Read Cycle n° 1, Either Side (25:26 28) ‘Re’ AoDRESS tA on tow OnTMour “PREVCUS DATA VALOR KKK TAA OM XX Timing Waveform of Read Cycle n° 2, Either Side (25, 27, 29) taco DATA sr Se Se CE v tro, leo ~ CURRENT 7 P cs Dm oe Notes: 25. R/W is high for read cycles. 26. Device is continuously enabled, CS = VIL. 27. Addresses valid prior to or coincident with CS transition low. 28. OF - Vil. 29. To access RAM, CS ~ VIL. MATRA MHS 7 Rev. F (11 April. 97)

M67130/M67140 demtaonduaters AC Parameters POOLE M67130-30(+) | M67130-35(**) | M67130-45 | M67130-55 caliente itis MOT140-30¢#) | M67L40-35(+*) | M67140-45 | M67140-55 PARAMETER a a . UNI (G4) (35) PRELIMINARY TAVWL | tas Address Set up Time 0 0 0 0 ns “TWLWH twe Write Pulse Width 25 - 30, - 3s - 40 - ns [wie [orotate fe -[«-* |e |e! ‘Output active from end of write ; mes low | 30,31, 33) pe fe fe fo fe] Notes: 30. ‘Transition is measured + 500 mV from low or high impedance voltage with load (figures 1 and 2), 31, This parameter is guaranteed but not tested. 32. To aecess RAM CS = VIL. ‘This condition must be valid for entire tgw time. 33. The specification for tj}; must be met by the device supplying write data to the RAM under all operating conditions. Although tpx and tow values vary over voltage and temperature, the actual tpg; will always be smaller than the actual tow. 34, STD symbol. 35. ALT symbol (*). Commercial only. Not available in DIP. (©), DIP package available for commercial only,

8 MATRA MHS

Rev. F (II April. 97)

somiconaueters M67130/M67140 Timing Waveform of Write Cycle n° 1, R/W Controlled Timing 3° 37, 38, 42) we jyzi44 OE ‘aw “ aa ray a twa) PATRout {ey Ks > tow tow barra ae Timing Waveform of Write Cycle n° 2, CS Controlled Timing (36-37, 38, 40) we ae — twa RAV tow ton DATAW a Notes: 36. R/W must be high during all address transitions. 37. Awrite occurs during the overlap (tgw or twp) of a low CS and a low RAW. 38. twa is measured from the earlier of CS or R/W going high to the end of write cycle. 39. During this period, the /O pins are in the output state, and input signals must not be applied. 40. Ifthe CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state, 41, ‘Transition is measured + 500 mV from steady state with a5 pF load (including scope and jig) This parameter is sampled and not 100 % tested. 42, If OBis low during a RAW controlled write cycle, the write pulse widdh must be the larger of twp oF (wz. + Dw) ‘wallow the /O drivers to turn off and data to be placed on the bus forthe required tw. If OE is high during an RAW controlled write eyele, this requirement does not apply and the write pulse ean be as short as the specified twp. 43, ‘Toaccess RAM, CS ~ VIL. MATRA MHS 9 Rev. F (11 April. 97)

M67130/M67140 bemiconductors AC Parameters i ‘Mo7130-30%) | Mo7130-35 | Mo7130-45. | _M67130-55 | sma aati Mo7i40-30(%) | -M67140-35 | Mo7i40-45 | M67140-55 BUSY TIMING (For M7130 only) poet teoc BUSY Disable time to Chip Select 25 23 25 twop | Write Pulse to data delay (44) - 55 - w - 10 Notes: 44, Port-to-port delay through RAM cells from writing port to reading por, refer to “Timing Waveform of Read with BUSY (For M67130 only)”. 45, To ensure that the earlier ofthe two ports wins. 46. tgpp is 4 calculated parameter and is the greater of 0, twpp — twp (actual) oF tppp — tpw (actual). 47. ‘Io ensure that the write eycle is inhibited during contention. 48. To ensure that a write cycle is completed after contention. 49. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port to port delay (For M67140 only)”. (*). Commercial only. Not available in DIP. (°*). DIP package available for commercial only.

10 MATRA MHS

Rev. F (11 April. 97)

somiconaueters M67130/M67140 Timing Waveform of Read with BUSY “51, 52) (For M67130) wo m = tDDD(53) Notes: 50. To ensure that the earlier of the two port wins. 51, Waite cycle parameters should be adhered to, to ensure proper writing 52. Device is continuously enabled for both ports. 53. OE at L for the reading port. Timing Waveform of Write with Port-to-port ‘$4 55:5 (For M67140 only) two RWa iwe wn Coe | | ‘woo ‘ODD Notes: 54. Assume BUSY ~ H for the writing port, and OF ~ L. for the reading port. 55, Write oycle parameters should be adhered tn, to ensure proper writing 56. Devive is continuously enabled for both ports. MATRA MHS ll Rev. F (11 April. 97)

M67130/M67140 Semiconductors Timing Waveform of Write with BUSY (For M67140) twe RW wa ‘WH BUSY Timing Waveform of Contention Cycle n° 1, CS Arbitration (For M67130 only) LAND R oS taPS Sr, 'BAC ‘spo BUSYn 128 L AND R Br 'APS fost “BAC ‘spc BUSY.

12 MATRA MHS

Rev. F (11 April. 97)

Semiconductors M67130/M67140 Timing Waveform of Contention Cycle n° 2, Address Valid Abritration (For M67130 only) $7) Left Address Valid First : ‘RC OR two: tas| IBAA IBD A BUSYr Right Address Valid First : tac OR two taps [| ADEA, Se BAA, ‘BCA BUSY. Note: 57, CS_=CSa= Vi

16 Bit Master/Slave Dual-port Memory Systems

SLAVE®) BUSY BUSY Note: 58. No arbitration in M67140 (SLAVE). BUSY.IN inhibits write in M67140 (SLAVE), MATRA MHS 13 Rev. F (11 April. 97)

M67130/M67140 Semiconductors Waveform of Interrupt Timing ©) two: a XXXXXX ADDR "& INTERRUPT SET ADDRESS KXXXXXX ty ae RAV" sd ling? INT 'B* tre roo XXXXXX INTERRUPT CLEAR ADDAESS OXXXKKX tas 1) cs" OE"B" tin Notes: 59. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite fom “A” 60. See interrupt thruth table. 61, Timing depends on which enable signal is asserted last. 62. Timing depends on which enable signal is de-asserted first. Range INTERRUPT 67130/140-30 | 67130/140-35 oe ae ae [ svamon [fn [a [a [nan [mn | lus _faseensccrome | o | - fo | -[o|-[o]-|=| (*). Commercial only, Not available in DIP. (©). DIP package available for commercial only:

14 MATRA MHS

Rev. F (11 April. 97)

Semiconductors M67130/M67140

Ordering Information

TEMPERATURE RANGE PACKAGE DEVICE SPEED FLOW c M S3_ — 67130 — 35 1K = 48 pin DIL ceramic 600 mils 30 CK = 48 pin DIL side-brazed 600 mils 35 ns AK =48 pin LCC 5 ns $3 = 52 pin PLCC 5 ns 3K = 48 pin DIL plastic 600 mils ns RD — 6 pin VQTP- KK = Flat pack 48 pins 400 mils¢7139 — gk (IK x8) Master Q3 = CQPI 52 67140 =8K (IK x8) Slave 0 = Dice form L = Low power v = Very low power blank = MHS standards 1883 = MIL STD 883 Class B or S C= Commercial 0° to 470°C P83 = MIL STD 883 + PIND test 1= Industrial AO® to 485°C SB/SC = SCC 9000 level B/C A = Automotive A0® to +125°C SHXXX = Special customer request M=Military 55° to +125°C VHXXX == light models (space) S = Space 55° to +125°C UHXXX = Lingineering models (space) MIIXXX = Mechanical parts (space) LHXXX = Life test parts (space) :R = Tape and reel :RD = Tapeand reel dry pack :D = Dry pack MATRA MHS 15 Rev. F (II April. 97)

M67130/M67140 bemiconductors Military and Space Versions The following tables give package/consumption/access time/process flow available combinations ‘Temp. Packages | Consumption Access ‘Time (ns) Std process RI process range 67130 671308, v L 35 45 55 Mil flows Mil flows. Space flows (including SMD5962-86875) cK . P Ps . Py ° KK x x x x x x i x e x x e e s aK . . . . ° cK . . . . ° KK x x x xX x 0 x x e e . Temp. Packages | Consumption Access Time (ns) Std process RT process range 67140 671405 v L 35 45 55 Mil flows ‘Space flows (including SMD5962-86875) M IK . . . ° . ° aK ° . ° . . ° KK x x x x x x @ . . ° . ° ° 0 x . x x e ° aK . . ° ° ° ck . . . . ° KK x x x x x 0 x x . ° . @ = product in production X = call sales office for availibility The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.

16 MATRA MHS

Rev. F (11 April. 97)