M67025E

M67025E ATMEL | Alldatasheet

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Features

 Fast Access Time: 30/45 ns  Wide Temperature Range: -55°C to +125°C  Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility  Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using More Than One Device  On-chip Arbitration Logic  Versatile Pin Select for Master or Slave: –M / S = H for Busy Output Flag On Master –M / S = L for Busy Input Flag On Slave  INT Flag for Port to Port Communication  Full Hardware Support of Semaphore Signaling Between Ports  Fully Asynchronous Operation From Either Port  Battery Back-up Operation: 2V Data Retention  TTL Compatible  Single 5V + 10% Power Supply  QML Q and V with SMD 5962-91617 Introduction The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit × 16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need of an additional discrete logic. Master and slave devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in the memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port in order to enter a very low stand by power mode. Using an array of eight transistors (8T) memory cell, the M67025E combines an extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns over the full temperature range. All versions offer battery backup data retention capa- bility with a typical power consumption at less than 5 µW. For military/space applications that demand superior levels of performance and reli- ability the M67025E is processed according to the methods of the latest revision of the MIL PRF 38635 (Q and V) and/or ESA SCC 9000. Rad. Tolerant High Speed

8 Kb x 16

4146J–AERO–06/03 Block Diagram Notes: 1. (MASTER): BUSY is output. (SLAVE): BUSY is input. 2. LB = Lower Byte UB = Upper Byte

3 M67025E

4146J–AERO–06/03 Pin Configuration Pin Description Left Port Right Port Names CS L CS R Chip select R/W L R/W R Read/Write Enable OE L OE R Output Enable A0L – 12L A0R – 12R Address I/O0L – 15L I/O0R – 15R Data Input/Output SEM L SEM R Semaphore Enable UB L UB R Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSY L BUSY R Busy Flag M/S Master or Slave Select Vcc Power GND Ground

4146J–AERO–06/03 Functional Description The M67025E has two ports with separate control, address and I/O pins that permit independent read/write access to any memory location. These devices have an auto- matic power-down feature controlled by CS . CS controls on-chip power-down circuitry which causes the port concerned to go into stand-by mode when not selected (CS high). When a port is selected access to the full memory array is permitted. Each port has its own Output Enable control (OE ). In read mode, the port’s OE turns the Output drivers on when set LOW. Non-conflicting READ/WRITE conditions are illustrated in Table 1. The interrupt flag (INT) allows communication between ports or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INT L) is set when the right port writes to memory location 1FFE (HEX). The left port clears the interrupt by reading address location 1FFE. Similarly, the right port interrupt flag (INT R ) is set when the left port writes to memory location 1FFF (HEX), and the right port must read memory location 1FFF in order to clear the interrupt flag (INT R ). The 16-bit message at 1FFE or 1FFF is user- defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not reserved for mail boxes but become part of the RAM. See Table 3 for the interrupt function. Arbitration Logic The arbitration logic will resolve an address match or a chip select match down to a min- imum of 5 ns determine which port has access. In all cases, an active BUSY flag will be set for the inhibited port. The BUSY flags are required when both ports attempt to access the same location simultaneously. Should this conflict arise, on-chip arbitration logic will determine which port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that allow the processor to hold the operation with its associated address and data. It should be noted that the operation is invalid for the port for which BUSY is set LOW. The inhib- ited port will be given access when BUSY goes inactive. A conflict will occur when both left and right ports are active and the two addresses coin- cide. The on-chip arbitration determines access in these circumstances. Two modes of arbitration are provided: (1) if the addresses match and are valid before CS on-chip con- trol logic arbitrates between CSL and CSR for access; or (2) if the CS are low before an address match, on-chip control logic arbitrates between the left and right addresses for access (refer to Table 4). The inhibited port’s BUSY flag is set and will reset when the port granted access completes its operation in both arbitration modes. Data Bus Width Expansion Expanding the data bus width to 32 or more bits in a dual-port RAM system means that several chips may be active simultaneously. If every chips has a hardware arbitrator, and the addresses for each arrive at the same time one chip may activate in L BUSY signal while another activates its R BUSY signal. Both sides are now busy and the CPUs will wait indefinitely for their port to become free. To overcome this “Busy Lock-Out’ problem, Atmel has developed a MASTER/SLAVE system which uses a single hardware arbitrator located on the MASTER. The SLAVE has BUSY inputs which allow direct interface to the MASTER with no external components, giving a speed advantage over other systems. When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a conflict situation. Conversely, the write pulse must extend a hold time beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is inherent in all dual-port memory systems where more than one chip is active at the same time.

5 M67025E

4146J–AERO–06/03 The write pulse to the SLAVE must be inhibited by the MASTER’s maximum arbitration time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the MASTER’s BUSY signal. Semaphore Logic The M67025E is an extremely fast dual-port 4 Kb × 16 CMOS static RAM with an additional locations dedicated to binary semaphore flags. These flags allow either of the processors on the left or right side of the dual-port RAM to claim priority over the other for functions defined by the system software. For example, the semaphore flag can be used by one processor to inhibit the other from accessing a portion of the dual-port RAM or any other shared resource. The dual-port RAM has a fast access time, and the two ports are completely indepen- dent of each another. This means that the activity on the left port cannot slow the access time of the right port. The ports are identical in function to standard CMOS static RAMs and can be read from, or written to, at the same time with the only possible conflict aris- ing from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non- semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to prevent conflicts in the non-semaphore segment of the dual-port RAM. The devices have an automatic power-down feature controlled by CS , the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when not selected. This conditions is shown in Table 1 where CS and SEM are both high. Systems best able to exploit the M67025E are based around multiple processors or con- trollers and are typically very high-speed, software controlled or software-intensive systems. These systems can benefit from the performance enhancement offered by the M67025 hardware semaphores, which provide a lock-out mechanism without the need for complex programming. Software handshaking between processors offers the maximum level of system flexibil- ity by permitting shared resources to be allocated in varying configurations. The M67025E does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more usual methods of hardware arbitration is that neither processor ever incurs wait states. This can prove to be a con- siderable advantage in very high speed systems. How The Semaphore Flags Work The semaphore logic is a set of eight latches independent of the dual-port RAM. These latches can be used to pass a flag or token, from one port to the other to indicate that a shared resource is in use. The semaphore provides the hardware context for the “Token Passing Allocation’ method of use assignment. This method uses the state of a sema- phore latch as a token indicating that a shared resource is in use. If the left processor needs to use a resource, it requests the token by setting the latch. The processor then verifies that the latch has been set by reading it. If the latch has been set the processor assumes control over the shared resource. If the latch has not been set, the left proces- sor has established that the right processor had set the latch first, has the token and is using the shared resource. The left processor may then either repeatedly query the sta- tus of the semaphore, or abandon its request for the token and perform another operation whilst occasionally attempting to gain control of the token through a set and test operation. Once the right side has relinquished the token the left side will be able to take control of the shared resource. The semaphore flags are active low. A token is requested by writing a zero to a sema- phore latch, and is relinquished again when the same side writes a one to the latch.

4146J–AERO–06/03 The eight semaphore flags are located in a separate memory space from the dual-port RAM in the M67025E. The address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, OE and R/W) as normally used in accessing a standard static RAM. Each of the flags has a unique address accessed by either side through address pins A0-A2. None of the other address pins has any effect when accessing the semaphores. Only data pin D 0 is used when writing to a semaphore. If a low level is written to an unused semaphore location, the flag will be set to zero on that side and to one on the other side (see Table 5). The semaphore can now only be modified by the side showing the zero. Once a one is written to this location from the same side, the flag will be set to one for both sides (unless a request is pending from the other side) and the semaphore can then be written to by either side. The effect the side writing a zero to a semaphore location has of locking out the other side is the reason for the use of semaphore logic in interprocessor communication. (A thorough discussion of the use of this feature follows below). A zero written to the sema- phore location from the locked-out side will be stored in the semaphore request latch for that side until the semaphore is relinquished by the side having control. When a sema- phore flag is read its value is distributed to all data bits so that a flag set at one reads as one in all data bits and a flag set at zero reads as all zeros. The read value is latched into the output register of one side when its semaphore select (SEM ) and output enable (OE) signals go active. This prevents the semaphore changing state in the middle of a read cycle as a result of a write issued by the other side. Because of this latch, a repeated read of a semaphore flag in a test loop must cause either signal (SEM or OE) to go inactive, otherwise the output will never change. The semaphore must use a WRITE/READ sequence in order to ensure that no system level conflict will occur. A processor requests access to shared resources by attempting to write a zero to a semaphore location. If the semaphore is already in use, the sema- phore request latch will contain a zero, yet the semaphore flag will appear as a one, and the processor will detect this status in the subsequent read (see Table 5). For example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource concerned. If a processor on the right side then attempts to write a zero to the same semaphore flag it will fail, as will be verified by a subsequent read returning a one from the semaphore location on the right side has a READ/WRITE sequence been used instead, system conflict problems could have occurred during the interval between the read and write cycles. It must be noted that a failed semaphore request needs to be followed by either repeated reads or by writing a one to the same location. The simple logic diagram for the semaphore flag in Figure 2 illustrates the reason for this quite clearly. Two sema- phore request latches feed into a semaphore flag. The first latch to send a zero to the semaphore flag will force its side of the semaphore flag low and other side high. This status will be maintained until a one is written to the same semaphore request latch. Should a zero be written to the other side’s semaphore request latch in the meantime, the semaphore flag will flip over to this second side as soon as a one is written to the first side’s request latch. The second side’s flag will now stay low until its semaphore request latch is changed to a one. Thus, clearly, if a semaphore flag is requested and the processor requesting it no longer requires access to the resource, the entire system can hang up until a one is written to the semaphore request latch concerned. Semaphore timing becomes critical when both sides request the same token by attempting to write a zero to it at the same time. Semaphore logic is specially conceived to resolve this problem. The logic ensures that only one side will receive the token if simultaneous requests are made. The first side to make a request will receive the token where request do not arrive at the same time. Where they do arrive at the same time,

7 M67025E

4146J–AERO–06/03 the logic will assign the token arbitrarily to one of the ports. It should be noted, however, that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, errors can be introduced if semaphores are mis- used or misinterpreted. Code integrity is of the utmost performance when semaphores are being used instead of slower, more restrictive hardware-intensive systems. Semaphore initialization is not automatic and must therefore be incorporated in the power up initialization procedures. Since any semaphore flag containing a zero must be reset to one, initialization should write a one to all request flags from both sides to ensure that they will be available when required. Using Semaphores – Some Examples Perhaps the simplest application of semaphores is their use as resource markers for the M67025E’s dual-port RAM. If it is necessary to split the 8 Kb × 16 RAM into two 4 Kb × 16 blocks which are to be dedicated to serving either the left or right port at any one time. Sema- phore 0 can be used to indicate which side is controlling the lower segment of memory and semaphore 1 can be defined as indicating the upper segment of memory. To take control of a resource, in this case the lower 4 Kb of a dual-port RAM, the left port processor would then write a zero into semaphore flag 0 and then read it back. If suc- cessful in taking the token (reading back a zero rather than a one), the left processor could then take control of the lower 4 Kb of RAM. If the right processor attempts to per- form the same function to take control of the resource after the left processor has already done so, it will read back a one in response to the attempted write of a zero into semaphore 0. At this point the software may choose to attempt to gain control of the second 4 Kb segment of RAM by writing and then reading a zero in semaphore 1. If suc- cessful, it will lock out the left processor. Once the left side has completed its task it will write a one to semaphore 0 and may then attempt to access semaphore 1. If semaphore 1 is still occupied by the right side, the left side may abandon its semaphore request and perform other operations until it is able to write and then read a zero in semaphore 1. If the right processor performs the same operation with semaphore 0, this protocol would then allow the two processes to swap 4 Kb blocks of dual-port RAM between one another. The blocks do not have to be any particular size, and may even be of variable size depending on the complexity of the software using the semaphore flags. All eight sema- phores could be used to divide the dual-port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on each side, rather than having a common meaning as is described in the above example. Semaphores are a useful form of arbitration in systems such as disk interfaces where the CPU must be locked out of a segment of memory during a data transfer operation, and the I/0 device cannot tolerate any wait states. If semaphores are used, both the CPU and the I/0 device can access assigned memory segments, without the need for wait states, once the two devices have determined which memory area is barred to the CPU. Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. On a semaphore handshake has been performed, both proces- sors can access their assigned RAM segments at full speed. Another application is in complex data structures. Block arbitration is very important in this case, since one processor may be responsible for building and updating a data structure whilst the other processor reads and interprets it. A major error condition may be created if the interpreting processor reads an incomplete data structure. Some sort of arbitration between the two different processors is therefore necessary. The building processor requests access to the block, locks it and is then able to enter the block to

ensuring a consistent data structure. Note: 1. Inputs Signals are for Semaphore Flags set and test (Write and Read) operations. Table 1. Non Contention Read/Write Control Table 2. Arbitration Options

9 M67025E

Notes: 1. Assumes BUSY L = BUSYR = H.

1. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.

Notes: 1. INT Flags Don’t Care.

1. X = DON’T CARE, L = LOW, H = HIGH.

LV5R = Left Address Valid ≥ 5 ns before right address. Same = Left and Right Addresses match within 5 ns of each other. = LOW ≥ 5 ns before Right CS. RL5L = Right CS = LOW ≥ 5 ns before left CS. LW5R = Left and Right CS = LOW within 5 ns of each other. Table 3. Interrupt Flag(1) (4) Table 4. Arbitration(2)

Note: 1. This table denotes a sequence of events for only one of the 8 semaphores on the M67025E. Figure 1. Semaphore Logic Table 5. Example Semaphore Procurement Sequence

11 M67025E

4146J–AERO–06/03

Electrical Characteristics

Notes: 1. CS L = CSR > 2.2V. 2. CS L = CSR > VCC - 0.2V. 3. Both ports active - Maximum frequency - Outputs open - OE = VIH. 4. One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level Inputs - CSL = CSR > 2.2V Input or output voltage applied: (GND - 0.5V) to (VCC + 0.5V) *NOTE: Stresses greater than those listed under Absolute Max- imum Ratings may cause permanent damage to the device.This is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 6. DC Test Conditions

1. Vcc = 5.5V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
2. VIH max = Vcc + 0.5V, VIL min = -0.5V or -1V pulse width 50 ns.

VIH(2) Input high voltage 2.2 V Min. VOH (3) Output high voltage 2.4 V Min.

4146J–AERO–06/03 Data-retention Mode Atmel CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip select (CS L, CSR ) must be held high during data retention; within VCC to VCC - 0.2V. 2. CS L, CSR must be kept between VCC - 0.2V and 70% of VCC during the power up and power down transitions. 3. The RAM can begin operation > tRC after VCC reaches the minimum operating voltage (4.5 volts). Timing Parameter Description Minimum Maximum Unit VDR Data Retention Voltage 2.0 – V TCDR Chip deselect to data retention time 0– n s T R Operation recovery time TAVAV (1) 1. TAVAV = Read cycle time. –n s ICCDR1 (2) 2. V IN (CSL/R) = Vcc Vcc = 2V V IL = 0V VIH = Vcc Data retention current – 400 µA

13 M67025E

Note: 1. Including scope and jig. Notes: 1. Transition is measured +500 mV from low or high impedance voltage with load (Figure 2 and Figure 3).

1. This parameter is guaranteed but not tested.
2. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. Refer to Table 1.

Figure 2. Output Load Figure 3. Output Load (for tHZ , tLZ, tWZ , and tOW ) Table 7. Over the Full Operating Temperature and Supply Voltage Range UnitSymbol (4) Symbol (5) Min. Max. Min. Max.

4146J–AERO–06/03 Timing Waveform of Read Cycle number 1, Either Side (1) (2)(4) Timing Waveform of Read Cycle number 2, Either Side (1) (3) (4) (5) Timing Waveform of Read Cycle number 3, Either Side (1)(3)(4)(5) 1. R/W is high for read cycles. 2. Device is continuously enabled, CS=V IL, UB or LB VIL. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition low. 4. OE = VIL 5. T o access RAM, CS =V IL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL. Refer to Table 1. O

15 M67025E

Table 8. AC Electrical Characteristics Symbol (1) Symbol (2) Min. Max. Min. Max.

1. T o access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. This condition must be valid
2. Transition is measured ± 500 mV from low or high impedance voltage with load (Figure 2 and Figure 3).
3. The parameters is guaranteed but not tested.

and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW .

4146J–AERO–06/03 Timing Waveform of Write Cycle number 1, R/W Controlled Timing (1) (2) (3) (7) Timing Waveform of Write Cycle number 2, CS Controlled Timing (1) (2) (3) (5) Notes: 1. R/WC or CS must be high during all address transitions. 2. A write occurs during the overlap (tSW or tWP ) of a low CS or SEM and a low R/W. 3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Transition is measured ± 500 mV from steady state with a 5 pF load (including scope and jig).This parameter is sampled and not 100% tested. 7. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 8. To access RAM, CS = VIL. SEM = VIH. 9. To access upper byte CS = VIL, UB = VIL, SEM = VIH. To access lower byte CS = VIL, LB = VIL, SEM = VIH.

17 M67025E

Table 9. AC Electrical Characteristics

1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For Mas-
2. T o ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) to tDDD - tDW (actual).

1. T o ensure that the write cycle is inhibited during contention.
2. T o ensure that a write cycle is completed after contention.
3. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port

delay (For Slave, 67025 only)’.

4146J–AERO–06/03 Timing Waveform of Read with BUSY (2) (3) (4) (For Master 67025) Notes: 1. To ensure that the earlier of the two port wins. 2. Write cycle parameters should be adhered to, to ensure proper writing. 3. Device is continuously enabled for both ports. 4. OE = L for the reading port. Timing Waveform of Write with Port-to-Port (1) (2) (3) (For Slave 67025 Only) Notes: 1. Assume BUSY = H for the writing port, and OE = L for the reading port. 2. Write cycle parameters should be adhered to, to ensure proper writing. 3. Device is continuously enabled for both ports.

19 M67025E

4146J–AERO–06/03 Timing Waveform of Write with BUSY (For Slave 67025) Timing Waveform of Contention Cycle number 1, CS Arbitration (For Master 67025 only)

4146J–AERO–06/03 Timing Waveform of Contention Cycle number 2, Address Valid Arbitration (For Master 67025 only) (1) Left Address Valid First: Right Address Valid First: Note: 1. CS L = CSR = VIL

21 M67025E

4146J–AERO–06/03 AC Interrupt Characteristics Waveform of Interrupt Timing (1) Notes: 1. All timing is the same for left and right ports. Port “A’ may be either the left or right port. Port “B’ is the port opposite from “A’. 2. See interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first. Interrupt Timing Parameter 67025-30 67025-45 UnitSymbol Min. Max. Min. Max. t AS A d d r e s s s e t - u p t i m e 0–0– n s tWR W r i t e r e c o v e r y t i m e 0–0– n s tINS Interrupt set time – 25 – 35 ns tINR Interrupt reset time – 25 – 35 ns

4146J–AERO–06/03 32-bit Master/Slave Dual-port Memory Systems Note: 1. No arbitration in M67025E (SLAVE). BUSY-IN inhibits write in M67025E SLAVE. Timing Waveform of Semaphore Read after Write Timing, Either Side (1) Note: 1. CS = VIH for the duration of the above timing (both write and read cycle).

23 M67025E

4146J–AERO–06/03 Timing Waveform of Semaphore Contention (1) (3) (4) Notes: 1. D OR = DOL VIL, CSR = CSL = VIH, semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. Either side “A’ = left and side “B’ = right, or side “A’ = right and side “B’ = left. 3. This parameter is measured from the point where R/W A or SEMA goes high until R/WB or SEMB goes high. 4. IF tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

4146J–AERO–06/03

Ordering Information

Note: 1. Contact Atmel for availability. Part Number Temperature Range Speed Package Quality Flow MMK2-67025EV-30-E (1) 25°C 30 ns MQFPF84 Engineering Samples MMK2-67025EV-30 -55 to +125 °C 30 ns MQFPF84 Standard Mil. MMK2-67025EV-45 -55 to +125 °C 45 ns MQFPF84 Standard Mil. SMK2-67025EV-30SB -55 to +125 °C 30 ns MQFPF84 SCC B SMK2-67025EV-45SB -55 to +125 °C 45 ns MQFPF84 SCC B 5962-9161709QZC -55 to +125 °C 30 ns MQFPF84 QML Q 5962-9161706QZC -55 to +125 °C 45 ns MQFPF84 QML Q 5962-9161709VZC -55 to +125 °C 30 ns MQFPF84 QML V 5962-9161706VZC -55 to +125 °C 45 ns MQFPF84 QML V MM0-67025EV-30-E (1) 25°C 30 ns Die Engineering Samples 5962-9161709Q9A (1) -55 to +125°C 30 ns Die QML Q 5962-9161709V9A(1) -55 to +125°C 30 ns Die QML V

25 M67025E

4146J–AERO–06/03 Package Drawings 84 lead MQFPF (1.15 inch square)

4146J–AERO–06/03

Printed on recycled paper. Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations

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