M66271FP

M66271FP MITSUBISHI | Alldatasheet

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OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP>

DESCRIPTION

The M66271FP is a graphic display-only controller for displaying a high duty dot matrix type LCD which is used widely for PPC,FAX and multi-function telephones. It is capable of controlling a monochrome STN LCD system of up to 320 x 240 dots. The IC has a built-in 9600-byte VRAM as a display data memory. All of the VRAM addresses are externally opened. Address mapping in the MPU memory space allows direct addressing of all display data from the MPU,thus providing efficient display data processing such as drawing. The built-in arbiter circuit (cycle steal system) which gives priority to display access allows timing-free access from MPU to VRAM, preventing display screen distortion. The IC provides interface with a 8-bit/16-bit MPU with a READY(WAIT) pin. And this IC has a function for LCD module built-in system by lessening connect pins between MPU.

FEATURES

• Monochrome STN dot matrix type LCD of up to 76800 dots (equivalent to 320 · 240 dots)
• Maximum display duty : 1/240 (set to 240 Line) : 1/255 (Max) l Display memory
• Built-in 9600-byte(76800-bit)VRAM (equivalent to one screen of 320 · 240 dots LCD)
• All addresses of built-in VRAM are externally opened. Outline 80P6N-A PIN CONFIGURATION(TOP VIEW) N.C : No Connection l Interface with MPU
• Capability of switching 8-bit type MPU/16-bit type MPU
• With WAIT output pin (Accessing register from MPU without WAIT output. Accessing VRAM from MPU with WAIT output.)
• Capability of controlling BHE or LWR/ HWR at the interface with a 16-bit MPU. l Interface with LCD
• LCD display data are 4-bit parallel output
• 4 kinds of control signals: CP,LP,FLM and M l Display functions
• Graphic display only (characters drawn graphically)
• Binary display only (without tone display function)
• Vertical scrolling is allowed within memory range (small size LCD only) l Additional function for LCD module built-in system
• 15 kinds of interface with MPU : A<4:1>,D<7:0>,IOCS,LWR ,RD
• Accessing VRAM from MPU through I/O register
• Capability of interfacing with 8-bit type MPU only l 5V single power supply l 80-pin QFP APPLICATION
• PPC/FAX operation panel,display/operation panel of other OA equipment
• Multi-function/public telephones
• PDA/electronic notebook/information terminal
• Other applications using LCD of 76800 dots or less WAI T MPU CLOCK RESET BUS HIGH ENABLE MPU ADDRESS BUS MPU DATA BUS DISPLAY DATA TRANSFER CLOCK FIRST LINE MARKER LCD DISPLAY DATA BUS OSCILLATOR INPUT HIGH WRITE STROBE LOW WRITE STROBE READ STROBE VRAM CHIP SELECT MPU ADDRESS BUS MPU DATA BUS DI SPLAY DATA LATCH PULSE OSCILLATOR OUTPUT LCD ALTERNATING SIGNAL LCD CONTROL SI GNAL CONTROL REGISTER CHIP SELECT 8/16 MPU SELECT M66271FP VSS VSS VSS VSS VSS VSS VSS VSS VDD VSS A<1> A<10> A<11> A<12> A<13> VSS VDD D<6> D<7> D<8> D<9> D<10> D<11> D<12> D<13> D<14> VSS VDD L CDENB N.C VDD VDD VDD A<0> A<2> A<3> A<4> A<5> A<6> A<7> D<15> M UD<2> UD<3> UD<1> UD<0> OSC2 OSC1 BHE N.C N.C N.C N.C N.C FLM LP CP D<5> D<4> D<3> D<2> D<1> D<0> N.C N.C N.C N.C VSS VDD A<9> A<8> IOCS LWR RD MCS WAIT MPUCLK RESET MPUSEL HWR

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> BLOCK DIAGRAM 1 BLOCK DIAGRAM 2 (In case of LCD module built-in system) A<13:0> D<15:0> OSC1 OSC2 LCDENB CP LP FLM M UD<3:0> VDD FIR S TLIN EM A R K E R SIGNAL LCD DISPLAY DATA BUS OSCILLATOR INPUT MPU DATA BUS IOCS 2 LWR 4 RD 5READ STROBE MCS 6VRAM CH I P SELECT WAIT 7WAIT MPUCLK 9MPU CLOCK RESET 11RESET MPUSEL 128/16 MPU SELECT BHE 14BUS HIGH ENABLE MPU ADDRESS BUS 8 23 34 42 52 63 77 1 10 13 24 25 35 40 41 51 64 65 80 VSS HWR 3HIGH WRITE STROBE 32 33 36 37 38 39 73 74 75 76 N.C ADDRESS BUFFER DATA BUFFER MPU I/F CONTROL CIRCUIT CLOCK CONTROL (BASIC TIMING CONTROL) CONTROL REGISTER VRAM 9600byte BUS ARBITER TIMING CONTROL LCD DISPLAY TIMING CONTROL CIRCUIT (CYCLE STEAL CONTROL) LCD DISPLAY DATA CONTROL CIRCUIT CONTROL REGISTER CH I P SELECT LOW W RITE STROBE OSCILLATOR OUTPUT DISPLAY DATA LATCH PULSE LCD ALTERNATING SIGNAL DISPLAY DATA TRANSFER CLOCK LCD CONTROL SIGNAL A<4:1> D<7:0> OSC1 OSC2 LCDENB CP LP FLM M UD<3:0> VDD IOCS 2 LWR 4 RD 5 8 23 34 42 52 63 77 1 10 13 24 25 35 40 41 51 64 65 80 VSS 32 33 36 37 38 39 73 74 75 76 N.C VRAM 9600byte VRAM ADDRESS INDEX REGISTER DATAPORT REGISTER 3 6 7 9 11 12 14 NO USE PINS 20 22 26 31 53 – – 60– BUS ARBITER TIMING CONTROLCLOCK CONTROL (BASIC TIMING CONTROL) MPU I/F CONTROL CIRCUIT DATA BUFFER LCD DISPLAY DATA CONTROL CIRCUIT LCD DISPLAY TIMING CONTROL CIRCUIT CONTROL REGISTER OSCILLATOR OUTPUT OSCILLATOR INPUT READ STROBE LOW W RITE STROBE CONTROL REGISTER CH I P SELECT MPU DATA BUS MPU ADDRESS BUS LCD CONTROL SIGNAL DISPLAY DATA TRANSFER CLOCK DISPLAY DATA LATCH PULSE LCD ALTERNATING SIGNAL LCD DISPLAY DATA BUS ADDRESS BUFFER FIR S TLIN EM A R K E R SIGNAL

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> PIN DESCRIPTIONS Generate an internal clock. For crystal oscillator or external clock signal. No connectionN.C 10 Ground 12VSS Power supply.(source +5V ) 7VDD MPU data bus Connect to MPU data bus. Selecting 8bit MPU by MPUSEL input, D<15:8> connect to VDD or VSS . Input/ OutputD<15:0> 16 Input High-Write strobe input When this pin is "L", data write to the internal VRAM. HWR is valid only in using 16-bit MPU controlled byte access by LWR and HWR. (Refer to Figure-1) 1HWR Input MPU address bus Connect to MPU address bus. When selecting 8-bit MPU, use A<13:0>. And selecting 16-bit MPU, use A<13:1> for the address bus with combining A<0> and BHE by the method of access to internal VRAM (Refer to Figure-1). Use A<4:0> for selecting address of control register. A<13:0> 14 Input Low-Write strobe input When this pin is "L", data write to the internal control register or VRAM. (Refer to Figure-1)1LWR Chip select input of control register When this pin is "L", select the internal control register. Assign to I/O space of MPU.Input 1IOCS Input Chip select input of VRAM When this pin is "L", select the internal VRAM. Assign to memory space of MPU. 1MCS Input Read strobe input When this pin is "L", data read from the internal control register or VRAM.(Refer to Figure-1)1RD Input 8/16-bit MPU select input According to MPU, set "VSS " for 8bit MPU and set "VDD " for 16bit MPU.MPUSEL 1 Input Reset input Use reset signal of MPU.When this pin is "L", initialize all internal control register and counter.1RESET Input MPU clock Input of MPU clock.MPUCLK 1 Input Bus-High-Enable input This pin is valid when using 16-bit MPU controlled byte access by A<0> and BHE (Refer to Figure- 1). Connect to "VDD " when using 8-bit MPU. Set to "L" when using the additional function for the LCD Module built-in system. BHE 1 Output WAIT output for MPU This signal makes WAIT for MPU. Change WAIT "L" at timing of falling edge of overlapping with MCS and (RD or LWR or HWR). And return to "H" at synchronizing with the rising edge of MPUCLK after internal processing. (Output WAIT only when requested access from MPU to VRAM during cycle steal access.) 1WAIT 4Output Display data bus for LCD Transfer the LCD display data with 4-bit parallel signal. Mutually output upper/lower data every CP output. UD<3:0> Display data transfer clock Shift clock for the transfer of display data to LCD. Take the display data of UD<3:0> to LCD at falling edge of CP. Output 1CP Output Display data latch pulse This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal. LP output when finish the transfer of display data of a line. Latch of display data and the transfer of scanning signal at falling edge of LP. 1LP First line marker signal Output the start pulse of scanning line. This signal is "H" active,the IC for driving scanning line catch FLM at falling edge of LP. Output 1FLM LCD alternating signal output Signal for driving LCD by alternating current.Output 1M Output LCD(ON/OFF) control signal output Output data which is set at bit"0 " of mode register(R1) in control register. This signal can use for controlling the LCD power supply, because LCDENB set to "L" byRESET. 1LCDENB Output Output pin for oscillator 1OSC2 Input Input pin for oscillator 1OSC1 MPU interface LCD interface Oscillator Others Pin name Input/ Output Function Number of pinsItem

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Difference in VRAM between 8-bit and 16-bit MPU (1) When accessing built-in VRAM by 8-bit MPU (MPUSEL="L",BHE="H",HWR="H" :set) (2) When accessing built-in VRAM by 16-bit MPU (2-1) In case MPU use A<0> and BHE for byte access (MPUSEL="H",HWR="H":set) Figure-1 Difference in VRAM between 8-bit and 16-bit MPU (2-2) In case MPU use LWR and HWR for byte access VRAM 9600byte A<13:0> A<13:0> MCS CEC LWR WEC RD D<7:0> DI<7:0> DO<7:0> A<13:1> A<0> A<13:1> CEC WEC A<0> MCS LWR A<13:1> CEC WEC A<0>BHE VRAM 4800byte VRAM 4800byte RD D<7:0> DI<7:0> DO<7:0> D<15:8> DI<15:8> DO<15:8> A<13:1> A<13:1> CEC WEC MCS LWR A<13:1> CEC WEC VRAM 4800byte VRAM 4800byte HWR RD D<7:0> DI<7:0> DO<7:0> D<15:8> DI<15:8> DO<15:8> OUTLINE M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data memory (VRAM) which is equivalent to 320·240 dots LCD. l Control register When access the control register from MPU side, use IOCS, LWR,RD,A<4:0> and D<7:0>. Refer to Table-1,when set control type inputs. Control registers are R1 – R8 for the normal mode function and R9 – R11 for the exclusive register for the LCD module built-in system. l VRAM When access VRAM from MPU side, use MCS,HWR,LWR, RD,BHE, A<13:0> and D<15:0>. And enable to correspond to both 8-bit and 16-bit MPU by using MPUSEL input.Refer to Figure-1 and Table-2 – 6 for a form of VRAM and input setting for 8/16-bit MPU. l Cycle steal system Cycle steal is interact method of transferring display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle of OSC. Basic timing is two clocks of OSC,and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. In accessing VRAM from MPU,output WAIT. Change WAIT to "L" at the timing of the falling edge of overlapping with MCS and (RD or LWR/HWR). And return to "H" at synchronizing with rising edge of MPUCLK after internal processing. Cycle steal system can transfer data with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. Refer to the following description of cycle steal. l Output to LCD side LCD display data UD<3:0> output synchronized with the rising edge of CP output per 4bits. LP output synchronized with the falling edge of OSC when finish the transfer of display data for a line. Enable to adjust the fittest value of the frame frequency requested by the LCD PANEL side with adjusting pulse width by LPW register. FLM output, when finish the transfer of display data of 1st line. M output is the LCD alternating signal which is signal for driving LCD by alternating current. M-cycle enable to set variably by M-cycle variable register in lineunit, and enable to utilize for preventting LCD from being inferior. (Lower byte) (Upper byte) (Lower byte) (Upper byte)

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Combination of control input pins for MPU interface (1) Access control register (Use address=A<4:0>,Data=D<7:0>) OperationIOCS LWR RD LH L Invalid LL H Write to control register HX X Read from control register (2-2) When use 16-bit MPU (In MPU controls byte access with A<0> and BHE. MPUSEL=HWR="H":set) MPU SEL A<0>BHEMCS HWR LWR HL H LLLH Upper byte Lower byte H H L Write Invalid Write Invalid Write Invalid Invalid Write Invalid Invalid Valid data bus width of MPU L H L H L H X H XXH Invalid Invalid Invalid Invalid Invalid Write 16-bit Upper 8-bit Lower 8-bit Lower 8-bit Even if A<0>="H", enable to write (2-3) When use 16-bit MPU (In MPU controls byte access with LWR and HWR. MPUSEL=BHE=A<0>="H":set) MPU SEL A<0>BHEMCS HWR LWR LLHHLH Upper byte Lower byte H H Write Write Invalid Invalid Invalid L H XX Write Invalid Write H Valid data bus width of MPU 16-bit Lower 8-bit Upper 8-bit (3) Reading from VRAM (3-1) When use 8-bit MPU (MPUSEL="L",BHE="H":set) MPU SEL MCS H L Odd address Even address Invalid Invalid X A<0> RD L H L H X L Read Read Invalid Invalid BHE H Valid data bus width of MPU 8-bit Table-1 – 6 show conditions of input setting when access the control register and VRAM from MPU (2) Writing to VRAM (2-1) When use 8-bit MPU (MPUSEL="L",BHE=HWR="H":set) (3-2) When use 16-bit MPU (MPUSEL="H":set) Note:Avoid setting combination except above,as cause of error action :X="L" or "H" MPU SEL MCS H Upper byte Lower byte X A<0> RD H L H Read Read Invalid Invalid BHE Valid data bus width of MPU 16-bitLXX MPU SEL A<0>BHEMCS HWR LWR LH L H HL XH L HXX Odd address Even address Invalid Write Write Invalid Invalid Invalid Valid data bus width of MPU 8-bit Table-1 Table-2 Table-3 Table-4 Table-5 Table-6

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Function of cycle steal control Ex.) Assuming 320·240 dots LCD UD<3:0> 4bit transfer LP Output when finish transfer of display data with a line CP Output every transfer of a display data Displaying term (Cycle steal method) (Necessity for data transfer from VRAM to LCD side) Horizontal synchronous term (No necessity for data transfer from VRAM to LCD side) CSE (Internal signal) Start WAIT for MPU according to cycle steal access. Access with bus timing of MPU without WAIT for MPU. Start WAIT for MPU in timing of CSE "H" according to bus timing of MPU. Setting by CR register

1 Line

Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input). Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to LCD BASIC TIMING Description of cycle steal Figure-2 BASIC TIMING OSC (Internal clock after dividing OSC1 input) CP output (Display data transfer) Data transfer from VRAM to LCD Access from MPU to VRAM LCDMPU Basic cycle Writing or Reading operation for VRAM during cycle steal needs 1 cycle in best case or 3 cycles in worst case, Cycle of LCD access Cycle of MPU access Worst case Best case Cycle of LCD access Cycle of MPU access Cycle of LCD access Operation cycle of MPU access(during WAIT output) MCS WAIT MCS WAIT Figure-3 Operation cycle of MPU access MPUCLK MPUCLK Operation cycle of MPU access according to the condition of the internal cycle steal at staring access requested from MPU. Ex.) Assuming that MCS input is later than RD,LWR and HWR input. Cancel WAIT,when synchronize with rising edge of MPUCLK Cancel WAIT,when synchronize with rising edge of MPUCLK M66271FP has a function for processing data of a line with more efficient.This function access with the cycle steal method as taking WAITfor MPU during the display term with necessityfor the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during the horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. But certainly set aterm of accessing with the cycle steal method by CSW register, for controlling an error action near the end of horizontal synchronous term. Setting by CSW register Figure-4 Function of cycle steal control Operation cycle of MPU access 78 79 80

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Additional function for LCD module built-in system As all of the VRAM address in M66271FP are externallyopened for addressing VRAM from MPU directly. When consider the LCD module built-in system,connect pins are increased. But M66271FP has an additional function for the LCD module built-in system by lessening connect pins. Outline of the additional function for the LCD module built-in system l Interface pins with MPU 15 kinds of Interface with MPU:A<4:1>,D<7:0>,IOCS,LWR,RD l Method of accessing the internal VRAM Access the internal VRAM through the VRAM address index register (IDXL,IDXH) and the Data port register (DP) which are used for I/O register. The following show the process of accessing VRAM. Application A<4:1> D<7:0> IOCS LWR RD Open M66271FP OSC1 OSC2 Rf Rd M66271FP OSC1 OSC2 VRAM address is increased of +1. Handling of oscillator pin <1> Crystal oscillator <2> Input from external clock directly Clock generator Crystal oscillator As far as possible, connect C,R and the crystal oscillator at near the pin. Figure-5 Oscillator pin Select VRAM address index register (IDXL, IDXH),and write access address(14bit) as data. Select Data port register (DP). Reading/Writing data for appointed VRAM address. Setting to MPUSEL,BHE="L" l No use pins set the following. HWR="H",MCS="H",WAIT= open,MPUCLK="L",MPUSEL="L", l RESET=Power on reset or soft ware reset. (In case of soft ware reset RESET ="H" :set) l Enable to change IDXL and IDXH,even if either. l Access the DP after writing the mode register (DISP(R1-D2)) =" 0". Always enable to access (CSES register ="0"),because the display signal fix "H" or "L" in DISP="0" and a term is no wait access. l VRAM address is automatically increased of +1 ,when finished access to DP. When access to continuous address,it doesn't need to set IDXL and IDXH. MPU side LCD side M66271FP Crystal Oscillator Common driver Graphic LCD PANEL Segment driver LCD module of small size for only graphics l Access DP without WAIT function.

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Control register M66271FP has 9 kinds of control register. To set mode from MPU to control register,use IOCS, LWR,RD,A<4:0> and D<7:0>. (1) Kind of control register Kind of register Address Functions of register R/W No. Name A3 A2 A1 Horizontal display character number register Set the number of horizontal display characters per line. W Horizontal synchronous pulse width register Set the pulse width of LP per line. W R5 Set the number of display line of vertical direction. W Set the display start address of VRAM. Set lower 8-bit to SAL and upper 6-bit to SAH. Max=257F H Control register Table Display start address register R/W R1 Mode register D6 – D0 set the basic mode. D7 is the status register of cycle steal state. Cycle steal enable width register Set the term of cycle steal enable access during horizontal synchronous term. W R8 M cycle variable register Set the cycle of LCD alternating signal from M . W D7=Only "R" R/W Data D7 D6 D5 D4 D3 D2 D1 D0 CR LPW SLT SAL SAH DISP REV LCDEOSCC CSW MT CSES R10 R11 Data port register VRAM address index register 01000 10000 00000 11000 01100 10100 00100 11100 00001 01001 10001 Data port register for accessing VRAM through the register. Set the address for accessing VRAM. Set lower 8-bit to IDXL and upper 6-bit to IDXH. Max=257F H And automatically increase in continuous address . R/W DP IDXL IDXH R/W Note:Data port register(DP) and VRAM address index register(IDXL,IDXH) are exclusive register,when using this IC for the LCD module built-in system. When RESET,each register is initialize the setting which is assumed LCD size of 320·240 dots. Then,even if each register has not setting,output the signal to LCD side ,it is possible to be alternation of LCD. RESET Vertical line number register

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (2) Description of register (2-1) Mode register [R1] 000 R/WAddress D7= Only "R" R/W Function Reset CSES No wait access Cycle steal access

• Status register for identifying active or inactive in cycle steal function.
• Set "1" during active with cycle steal function.
• CSES is for only reading,not for writing. RESET Reset OFF Reset ON
• Software reset.
• Surely return to reset off after reset on. OSCC D5 D4 D3 000 001 010 011 100 Division of OSC1 1/2 Division 1/4 Division 1/8 Division 1/16 Division
• Set the division of OSC clock for internal operation from OSC1 input pin.
• When reset,OSCC=000,OSC1 clock doesn't divide.
• Don't set except left table.
• Control the displaying ON/OFF of LCD.
• When reset,DISP=0,set display OFF.
• REV(D1) set "1", and when DISP= "0" display data UD<3:0> output "1" in reversal mode. REV Normal display Reversal display LCDE LCDENB="0"output LCDENB="1"output
• Control normal/reversal of LCD display.
• When reset,REV=0,set normal display .
• In using LCD of permeation method,REV="1" has effect. DISP Display OFF Display ON
• Set the output data from LCDENB output pin.
• When reset,LCDE=0,LCDENB output "0"(VSS potential).
• This function is prepared for controlling the voltage of LCD. When the power supply is ON after finish each register setting ,LCDE="1",supply voltage of LCD. Conversely for setting power supply OFF,first LCDE="0",the voltage of LCD is OFF. Therefore enable to prevent LCD from being unusual voltage as DC. This function use for satisfy the need of LCD. (2-2) Horizontal display characters number register [R2] Note: Definition of the number of display characters The number of display characters means data which is corresponding with 1 byte of VRAM. In case of binary,1 bit of VRAM corresponds to 1 dot of display,then 1 character means 8 dots of display. W 28H R/W Function Reset
• The number of horizontal display characters per line can set to the extent of max=504 dots(=63 characters)
• When reset,CR= "28H "(=40 characters =320 dots) Address 00000 CR D7 D6 D5 D4 D3 D2 D1 D0 000000 000001 000010 111111 504 Character number Display dot number 00010

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (2-3) Horizontal synchronous pulse width register [R3] W 01H Address R/W Function Reset LPW D7 D6 D5 D4 D3 D2 D1 D0 000000 000001 000010 111111 255 Character number

• Set the length of horizontal synchronous pulse width which appeared per line in character unit. Horizontal synchronous pulse output from LP output pin,and use for changing serial/parallel of displaying data. Adjusting this pulse width is possible to set frame frequency the fittest value. And the actual LP output pulse is (LPW setting value - 1CP) in consideration of timing with CP output.
• When reset,LPW= "01 H "(=1 character) (2-4) Cycle steal enable width register [R4] 00H Address R/W W Function Reset
• During the horizontal synchronous term, set term of access by cycle steal method in character number unit. Setting value of CSW sets below LPW value.
• When reset,CSW= "00H ". Note: Be careful with first and second byte of display data UD<3:0> output indefinite data when setting value of CSW is still reset (00H ). Surely CSW set over 01H . (When select 8-bit MPU,1 byte is indefinite. When 16-bit and SAL:D<0>=0, 2 byte are indefinite. When 16-bit and SAL:D<0>=1, 1 byte is indefinite.) CSW D7 D6 D5 D4 D3 D2 D1 D0 000000 000001 000010 111111 255 Character number (2-5) Vertical line number register [R5] F0H Address R/W W Function Reset SLT D7 D6 D5 D4 D3 D2 D1 D0 000000 000001 000010 111111 255 Vertical line number
• SLT combine the setting of display driving duty of LCD.
• Setting of SLT is sure to adjust to the number of display line of LCD.
• When reset,SLT= "F0 H "(=240 lines). 00100 01000 00110

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (2-6) Display start address register [R6,R7] (2-7) M cycle variable register [R8] 00HW Address R/W Function Reset MT D7 D6 D5 D4 D3 D2 D1 D0 000000 000001 000010 111111 Cycle of M Toggle change at every 1 frame. Toggle change at every 1 line(1LP). Toggle change at every 2 lines. Toggle change at every 255 lines.

• Set the cycle of M. In case of MT=01H ,M repeat reversal(toggle) at every 1 line (at every 1 count of LP).
• When reset,MT="00H ",toggle M signal at every 1 frame.
• We recommend this register set suitable value for user's LCD. (2-8) Data port register [R9] R/W DP Address R/W Function Reset
• Exclusive data port register for the LCD module built-in system. Reading or writing 8bit data between MPU and VRAM through this register.
• VRAM address index register (IDXL,IDXH) is increased of +1,when finished access to DP.
• Output indefinite data when reset. XX H (indefinite) 01110 D7 D6 D5 D4 D3 D2 D1 D0 10000 Data port (8bit) R/W 0000H SAH SAL Address R/W Function Reset
• D6 and D7 output "0" when read SAH.
• It is possible to set display start address to the extent of 257F H (=9600 address).
• Don't set over 2580H .
• When reset,SAL and SAH= "0000H ".
• Display start address is established by the writing data to SAH register. Even if only change SAL, surely set SAH after SAL.
• When select 8-bit MPU,start address set in SAL <D7 – D0> + SAH <D5 – D0>. When select16-bit MPU,start address set in SAL <D7 – D1> + SAH <D5 – D0>.
• Even if selecting 16-bit MPU,enable to set display start address in character unit. In case the display reading data from VRAM start at D<15:12>,set SAL <D0>="0", and if start at D<7:4>,set SAL <D0>="1". (Refer to Figure-8) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 000 0 0 0 0 0 100 0 0 0 0 1 000 0000H 0001H 0002H 1 1 1 1 1 110 257FH SAH SAL Display start address 01010 01100

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (2-9) VRAM address index register [R10,R11] 0000H IDXH IDXL R/W Address R/W Function Reset D7 D6 D5 D4 D3 D2 D1 D0 000000 000000 000000 100101 D7 D6 D5 D4 D3 D2 D1 D0 00000000 00000100 00001000 0000H 0001H 0002H 11111110 257F H IDXH IDXL Accessing VRAM address

• Exclusive VRAM address index register for the LCD module built-in system.
• It is possible to change the register only one side,because IDXH and IDXL are independent each other.
• It is possible to set VRAM access address to the extent of 257F H (=9600 address).
• Don't set address over 2580H .
• D6 and D7 output "0" when read IDXH
• When reset,IDXL and IDXH="0000 H ". CR SLT LPW CR LPW UD<3:0> 1 2 n-1 n3 n-2 CP OSC LP 1 2 CSW Relation between setting of control register and LCD displaying Expectant LCD PANEL Condition of control register (CR · 8)· SLT 76800 dots 1 horizontal line Character number of horizontal display Horizontal syncronous pulse width

1 Character number=8 dots display

• Vertical line numberSLT CR, LPW,CSW : Unit of character number SLT : Unit of line number fOSC : Internal OSC clock frequency after dividing OSC1 input (1) Time for proccessing a horizontal line(TH) (2) Time for proccessing a frame(TFR) TFR= TH · SLT TH = 2 · (CR+LPW) fOSC By adjusting LPW,it is possible to set a frame frequency which is requested from LCD PANEL the fittest value. Figure-6 Relation between setting of control register and LCD displaying 10010 10100 Description of LCD display 1 horizontal line

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Relation between address of VRAM and LCD display Figure-7 Relation between address of VRAM and LCD display 1000H 1001H 257EH 257FH 0000H 0001H 0000H 0001H 257EH 257FH CR ·8 dots SLT line 0000H 0001H 257EH 257FH VRAM 9600byte 0000H 0001H 257EH 257FH 1000H 1001H VRAM 9600byte ex.1) When display start address =0000H ex.2) When display start address =1000H VRAM address mapping on the LCD PANEL Remark) VRAM address counter return to "0000H ", after count up address to "257FH ". Relation between VRAM data ,LCD display and display start address register LCD PANEL LCD display data Data of one address for VRAM

• Only upper byte data of the display start address is invalid data(cut off data).
• Output the display data normally from next address of the display start address. Invalid display data Figure-8 Relation between VRAM data ,LCD display and display start address register LCD display data Data of one address for VRAM LCD display data Data of one address for VRAM D7 D6 D5 D4 D3 D2 D1 D0 1 01 0010 1 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 D15 D14 D13 D12 D11 D10 D9 D8 101 0010 1 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 1 1 11 D15 D14 D13 D12 D11 D10 D9 D8 1010 0101 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 D7 D6 D5 D4 D3 D2 D1 D0 000 0 1111 (3) When select 16-bit MPU (SAL :D0="1") (1) When select 8-bit MPU (2) When select 16-bit MPU (SAL :D0="0") LCD PANEL LCD PANEL LCD PANEL LCD PANEL

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Output when finish the transfer of one line of display data. Output signal of LCD side Ex.) Assuming 320·240 dots LCD (In setting of CR=40characters,LPW=2characters,SLT=240lines,OSCC=1division,MT=1toggle per line) CP UD<3:0> LP Output every display data transfer. 4bit parallel output OSC1 (1) Output signal per line Division of OSC1 = 1. 80 1 2 79 80 21 Output at finishing the transfer of first line display data. Cycle of reversing output of M is able to be set by MT register. LP 240 1 239 240 1 FLM M 239 (2) Output signal per frame (3) LCDENB output signal OSC1 LCDENB (4) Reset – 1st line of 1st frame RESET OSC1 1 2 34 56 CP LCDENB LP FLM M 1st line of 1st frame "L" (5) 1st line – 2nd line OSC1 123 CP LP FLM M 45 67 8 2nd line 76 77 78 79 80 1st line (6) 240th line of 1st frame – 1st line of 2nd frame OSC1 123 CP LP FLM M 45 67 876 77 78 79 80 240th line of 1st frame 1st line of 2nd frame "L"

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> ABSOLUTE MAXIMUM RATINGS (Ta=0 – +70˚C unless otherwise noted) VDD V VI V VO V IO mA Pd mW Tstg ˚C Symbol Parameter Conditions Ratings Unit Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature –0.3 – +6.5 –0.3 – VDD +0.3 –0.3 – VDD +0.3 –55 – +150 600 –10 RECOMMENDED OPERATING CONDITIONS (Ta=0 – +70˚C unless otherwise noted) VDD V4.5 5.0 5.5 Topr ˚C+70 VI V0V DD VO V0V DD VSS V0 +25 Symbol Parameter Conditions Limits UnitMin. Typ. Max. Operating temperature Supply voltage Supply voltage Input voltage Output voltage ELECTRICAL CHARACTERISTICS (V DD =5V–10%, Ta=0 – +70˚C unless otherwise noted) VIH VIL VOH VOL VT + VT – VIH VIL IDD(A) Operating supply current IIH IIL IOZH IOZL OSC1 VOH VOL OSC2 VDD =5.5V,VI=VDD VDD =5.5V,VI=VSS VDD =5.5V,VO =VDD VDD =5.5V,VO =VSS –10 –10 mA mA mA mA mAVDD =5.5V,VI=VDD or VSS fosc=10MHz,Output=open 3.5 1.0 2.2 0.8 V V V V VDD =4.5V VDD =4.5V IOH =–4mA IOL = 4mA IOH =–50uA IOL = 50uA 4.1 V 0.4 V 4.1 0.4 V V V V1.25 3.7 VDD =5.5V VDD =4.5V VDD =5.5V VDD =4.5V VDD =5.0V VDD =5.0V 2.3 2.3 IDD(S) Stand-by supply current mA VDD =5.5V, IOCS,MCS=V DD Other's VI=VDD or VSS (valid) 500 Symbol Parameter Conditions Limits Unit Min. Typ. Max. High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Positive-going threshold voltage Negative-going threshold voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage High-level input current Low-level input current Off-state high-level output current Off-state low-level output current All inputs except for OSC1,RESET and MPUSEL MPUSEL, RESET All outputs except for OSC2 and outputs of D<15:0> D<15:0> (Average)

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> SWITCHING CHARACTERISTICS (V DD =5V–10%, Ta=0 – +70˚C) ta(RD-D) 70 ns tdis(RD-D) 20 ns tpd(OSC-CP) 40 ns tpLH(OSC-LP) tpHL(OSC-LP) 40 ns ta(UD) 40 ns tpLH(OSC-FLM) tpHL(OSC-FLM) 40 ns tpd(OSC-M) 40 ns tpLH(OSC-LE) tpHL(OSC-LE) 40 ns tpHL(WR-WAIT) tpLH(CLK-WAIT) 20 ns tpHL(RD-WAIT) 40 ns C L=50pF ta(IOCS-D) ta(MCS-D) tdis(IOCS-D) tdis(MCS-D) tpHL(MCS-WAIT) tpd(D-WAIT) 0n s Symbol Parameter Test condition Limits Min. Typ. Max. Unit RD data access time IOCS data access time MCS data access time Output disable time after RD Output disable time after IOCS Output disable time after MCS WAIT output propagation time after WR WAIT output propagation time after RD WAIT output propagation time after MCS WAIT output propagation time after MPUCLK CP output propagation time after OSC LP output propagation time after OSC UD access time FLM output propagation time after OSC M output propagation time after OSC LCDENB output propagation time after OSC Data definite time before cancelling WAIT TIMING REQUIREMENTS (V DD =5V–10%, Ta=0 – +70˚C) (1) Accessing to control register tW(LWR) 70 ns tsu(D-LWR) 0n s th(LWR-D) 15 ns tsu(A-IOCS) 15 nstsu(A-LWR) th(LWR-A) 15 ns tsu(A-RD) th(RD-A) tW(IOCS) tsu(D-IOCS) th(IOCS-D) th(IOCS-A) Symbol Parameter Test condition Limits UnitMin. Typ. Max. LWR pulse width IOCS pulse width Data set up time before falling edge of LWR Data set up time before falling edge of IOCS Data hold time after rising edge of LWR Data hold time after rising edge of IOCS Address set up time before falling edge of IOCS Address set up time before falling edge of LWR Address set up time before falling edge of RD Address hold time after rising edge of LWR Address hold time after rising edge of RD Address hold time after rising edge of IOCS (2) Accessing to VRAM tW(WR) 70 ns tsu(D-WR) 0n s th(WR-D) 15 ns tsu(A-MCS) 15 nstsu(A-WR) th(WR-A) 15 ns tsu(A-RD) th(RD-A) tW(MCS) tsu(D-MCS) th(MCS-D) th(MCS-A) Symbol Parameter Test condition Limits UnitMin. Typ. Max. WR pulse width MCS pulse width Data set up time before falling edge of WR Data set up time before falling edge of MCS Data hold time after rising edge of WR Data hold time after rising edge of MCS Address set up time before falling edge of MCS Address set up time before falling edge of WR Address set up time before falling edge of RD Address hold time after rising edge of WR Address hold time after rising edge of RD Address hold time after rising edge of MCS

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> Note: Clock frequency of OSC1 input is less than fmax=20MHz. Limit of OSC clock for the internal operation is fmax=10MHz. When OSC1 is more than 10MHz from external input, set OSC clock up to 10MHz by using division of OSCC register. Division is set with rising edge of OSC1 input. (3) Clock and accessing to LCD display 1/n =Division of OSC1 LPW=Setting value of LPW register tC(CLK) 50 ns tWH(CLK) tWL(CLK) ns ns ns ns ns ns tC(OSC) tWH(OSC) tWL(OSC) tC(CP) tWH(CP) tWL(CP) tW(FLM) P.G DUT Input V DD Outputs except for D<15:0> 50W C L VDD R L=1K W R L=1K W SW1 SW2 D<15:0> C LVSS Parameter SW1 SW2 tdis(LZ) tdis(HZ) ta(ZL) ta(ZH) OpenClosed Input pulse level : 0 – 3V Input pulse rise/fall time : tr,tf=3ns Input decision voltage : 1.5V Output decision voltage : V DD /2 (However,tdis(LZ) is 10% of output amplitude and tdis (HZ) is 90% of that for dezision.) Load capacity CL include float capacity of connection and input capacity of probe. (1) (2) Symbol Parameter Test condition Limits Unit MIn. Typ. Max. MPUCLK cycle time MPUCLK "H" pulse width MPUCLK "L" pulse width OSC cycle time OSC "H" pulse width OSC "L" pulse width CP cycle time CP "H" pulse width CP "L" pulse width FLM pulse width tC(CLK) 50(note) tC(OSC) (1/n) tC(OSC) 2•(1/n) tC(OSC) 2•tC(OSC) •LPW (1/n) Test circuit Closed Closed Closed Open Open Open

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> IOCS LWR WAIT D<7:0> A<4:0> th(LWR-D)tsu(D-LWR) "H" tsu(D-IOCS) tsu(A-IOCS) tsu(A-LWR) th(LWR-A) tw(LWR) tw(IOCS) th(IOCS-A) th(IOCS-D) Without WAIT IOCS RD WAIT D<7:0> A<4:0> tdis(RD-D) "H" ta(IOCS-D) tsu(A-IOCS) tsu(A-RD) th(RD-A) th(IOCS-A) tdis(IOCS-D) ta(RD-D) Note 1: Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD). Limits of IOCS,LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. TIMING DIAGRAM (1) Write to control register( RD = "H" ) Without WAIT Data input is established Address is established (2) Read from control register (LWR= "H" ) Data output is established Address is established

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (4) Read from VRAM(LWR,HWR = "H" ) Term of non cycle steal access (3) Write to VRAM( RD = "H" ) MCS WAIT MCS RD WAIT D<7:0> (D<15:0>) D<7:0> (D<15:0>) LWR (+HWR) A<13:0> (+BHE) A<13:0> th(WR-D)tsu(D-WR) "H" tsu(D-MCS) tsu(A-MCS) tsu(A-WR) th(WR-A) tw(WR) tw(MCS) th(MCS-A) th(MCS-D) tdis(RD-D) "H" ta(MCS-D) tsu(A-MCS) tsu(A-RD) th(RD-A) th(MCS-A) tdis(MCS-D) ta(RD-D) Term of non cycle steal access Data input is established Address is established Address is established Data output is established Note 2: Writing/Reading operation for VRAM during non cycle steal access is performed during overlapping MCS and [LWR(+HWR) or RD]. Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (5) Write to VRAM( RD = "H" ) Term of cycle steal access MPUCLK MCS WAIT D<7:0> (D<15:0>) tWH(CLK) tC(CLK) tWL(CLK) LWR (+HWR) A<13:0> (+BHE) th(WR-D)tsu(D-WR) tsu(D-MCS) tsu(A-MCS) tsu(A-WR) th(WR-A) tw(WR) tw(MCS) th(MCS-A) th(MCS-D) tpHL(MCS-WAIT) tpHL(WR-WAIT) tpLH(CLK-WAIT) Address is established Data input is established (6) Read from VRAM( LWR,HWR = "H" ) Term of cycle steal access MPUCLK MCS WAIT D<7:0> (D<15:0>) tWH(CLK) tC(CLK) tWL(CLK) RD A<13:0> tdis(RD-D)ta(RD-D) ta(MCS-D) tsu(A-MCS) tsu(A-RD) th(RD-A) th(MCS-A) tdis(MCS-D) tpHL(MCS-WAIT) tpHL(RD-WAIT) tpLH(CLK-WAIT) tpd(D-WAIT) Data output is established Address is established Note 3: Reading/writing operation for VRAM during cycle steal needs 1tc(Internal) in best case or 3tc(Internal) in worst case,according to the condition of the internal cycle steal at starting access requested from MPU. tc(Internal) = Clock cycle time after setting division of OSC1. Data output D in reading is established before changing WAIT to "H". 4: Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. 5: Always once return MCS,LWR(+HWR) or RD to "H" after canceling WAIT output. In case of latching "L",as don't output next WAIT,this is cause of error action.

OPERATION PANEL CONTROLLER M66271FP MITSUBISHI <DIGITAL ASSP> (7) Interface timing with LCD <7-2> LCD control signal FLM M tW(FLM) OSC1 CP LP tpLH(OSC-FLM) tpHL(OSC-FLM) tpd(OSC-M) LCDENB tpLH(OSC-LE) tpHL(OSC-LE) <7-1> Transfer of LCD display data OSC1 CP LP UD<3:0> Data is indefinite tC(CP) tWH(OSC) tWL(OSC) tWH(CP) tWL(CP) tC(OSC) ta(UD) tpLH(OSC-LP) tpd(OSC-CP) tpHL(OSC-LP) (OSCC = 1 division : set) Note 6: Output signal to LCD side is syncronized with OSC clock for internal operation. When division is set to 1/2 – 1/16 by OSCC register, switching characteristics is defined by rising edge of OSC1. When OSCC = 1 division ,OSC clock for internal operation = OSC1 input.*