M66258FP MITSUBISHI | Alldatasheet

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MITSUBISHI <DIGITAL ASSP> PIN CONFIGURATION (TOP VIEW)DESCRIPTION The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits. The M66258FP, performing reading and writing operations at different cycles independently and asynchronously, is optimal for buffer memory to be used between equipment of different data processing speeds.

FEATURES

  • Memory configuration 8192 words x 8 bits configuration
  • High speed cycle 20 ns (Min.)
  • High speed access 16 ns (Max.)
  • Output hold 3 ns (Min.)
  • Reading and writing operations can be completely carried out independently and asynchronously.
  • Variable length delay bit
  • Input/output TTL direct connection allowable
  • Output 3 states APPLICATION
  • Digital copying machine,laser beam printer, high speed facsimile, etc. FUNCTIONAL DESCRIPTION When write enable input WE is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write lock input WCK to perform writing operation. When this is the case,the write address counter is also incremented simultaneously. When WE is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRES is set to "L", the write address counter is initialized. When read enable input RE is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented simultaneously. When RE is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in a high impedance state. When read reset input RRES is set to "L", the read address counter is initialized. Outline 24P2U-A(SSOP) 205 196 169 1510 1411 1312 RE RRES WE WRES M66258FP GND RCK VCC WCK DATA OUTPUT READ ENABLE INPUT READ RESET INPUT READ CLOCK INPUT DATA OUTPUT DATA INPUT WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT DATA INPUT

MITSUBISHI <DIGITAL ASSP> BLOCK DIAGRAM Input buffer Output buffer Write control circuit WCK VCC RCK GND Write enable input Write reset input Write clock input Read enable input Read clock input Read reset input WE WRES RE RRES 1 2 4 9 10 11 123 13 14 16 21 22 23 2415 Data inputs D0 to D7 Data outputs Q0 to Q7 Write address counter Memory array 8192 x 8 bits Read address counter Read control circuit

MITSUBISHI <DIGITAL ASSP> C O Off-time output capacitance V V V V m A ICC IIL Supply voltage Input voltage Output voltage Vcc ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted) Symbol Ratings UnitParameter Conditions VI VO Pd Tstg Power dispersion Storage temperature Value based on the GND pin Ta=25 °C -0.5– +6.0 -0.5– VCC +0.5 -0.5– VCC +0.5 825 -65– 150 °C mW V V V RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=5V–10%, GND=0V unless otherwise noted) V V Limits Min. Typ. Max.Symbol UnitParameter Vcc Supply voltage 5.0 4.5 5.5 0GND Topr Supply voltage Operating temperature 0 – 70 Limits Min. Typ. Max.Symbol Conditions UnitParameter VIH High-level input voltage 2.0 Low-level input voltage 0.8 VCC -0.8 0.55 -1.0 m A Off-state high-level output current m A m A 150 mA 10 pF pF VIL VOH VOL IIH IOZH IOZL C I Off-state low-level output current Average supply current during operation Input capacitance I OH = -4mA IOL = 4mA VI =V CC VI = GND WE, WRES, WCK, RE, RRES, RCK, – D7 WE, WRES, WCK, RE, RRES, RCK, – D7 VO =V CC VO = GND VI =V CC , GND, output open tWCK , tRCK = 20ns f = 1MHz f = 1MHz 1.0 5.0 -5.0 High-level output voltage Low-level output voltage High-level input current Low-level input current

MITSUBISHI <DIGITAL ASSP> 20tWCK tWCKH tWCKL tRCK Write clock (WCK) cycle Output disable time ns ns ns ns SWITCHING CHARACTERISTICS (Ta=0 – 70 °C, Vcc=5V–10%, GND=0V unless otherwise noted) Limits Min. Typ. Max.Symbol UnitParameter tAC 16 tOH tOEN tODIS Access time Output hold time Output enable time ns TIMING REQUIREMENTS (Ta=0 – 70 °C, Vcc=5V–10%, GND=0V unless otherwise noted) Limits Min. Typ. Max.Symbol UnitParameter tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data set up time for WCK Input data hold time for WCK Reset set up time for WCK/RCK Reset hold time for WCK/RCK Reset non-selection set up time for WCK/RCK Reset non-selection hold time for WCK/RCK WE set up time for WCK WE hold time for WCK WE non-selection set up time for WCK WE non-selection hold time for WCK RE set up time for RCK RE hold time for RCK RE non-selection set up time for RCK RE non-selection hold time for RCK Input pulse up/down time Data hold time (Note 1) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Note 1: For 1 line access, the following conditions must be satisfied: WE high-level period £ 20 ms - 8192 • tWCK - WRES low-level period RE high-level period £ 20 ms - 8192 • tRCK - RRES low-level period 2: Perform reset operation after turning on power supply.

MITSUBISHI <DIGITAL ASSP> SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT Input pulse level : 0 – 3V Input pulse up/down time : 3 ns Judging voltage Input : 1.3V Output : 1.3V(However, t ODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ ) is judged with 90% of the output amplitude.) Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe. RCK RE tODIS(HZ) 1.3V 1.3V Item tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH) SW1 Close GND GND 90% 1.3V VOH 10% 1.3V VOL Qn RL=1K W CL = 5pF : tOEN , tODIS RL=1K W VCC SW1 SW2 Qn Qn Qn CL = 30pF : tAC , tOH SW2 Open Close Open Open Close Open Close tODIS and tOEN measurement condition tODIS(LZ) tOEN(ZL) tOEN(ZH)

MITSUBISHI <DIGITAL ASSP> OPERATION TIMING WCK Dn n cycle n+1 cycle n+2 cycle n+3 cycle n+4 cycleDisable cycle tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES tDS tDH WCK Dn n-1 cycle n cycle 0 cycle 1 cycle 2 cycleReset cycle tWCK tNRESH tRESS tRESH tNRESS tDS tDH WRES = "H" WE = "L" WE WRES

  • Write cycle
  • Write reset cycle

MITSUBISHI <DIGITAL ASSP> WCK Dn n cycle n+1 cycle n cycle Disable cycle tWCK tDS tDH (n) (n) Period for writing data (n) into memory WE

  • Matters that needs attetion when WCK stops tNWES tDS tDH WRES = "H" Period for writing data (n) into memory Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.

MITSUBISHI <DIGITAL ASSP>

  • Read cycle
  • Read reset cycle RCK Qn n cycle n+1 cycle n+2 cycle n+3 cycle n+4 cycleDisable cycle tRCK tRCKH tRCKL tREH tNRES tNREH tRES tAC tOH tODIS tOEN HIGH-Z RRES = "H" RE RCK Qn n-1 cycle n cycle 0 cycle 1 cycle 2 cycleReset cycle tRCK tNRESH tRESS tRESH tNRESS tAC tOH (0) (0) RRES RE = "L"

MITSUBISHI <DIGITAL ASSP> WRES RRES WCK RCK Dn Qn WRES RRES VARIABLE LENGTH DELAY BIT

  • 1 line (8192 bits) delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay. 8192 cycle 8193 cycle 8194 cycle 8190 cycle8191 cycle0 cycle 1 cycle 2 cycle (0') (1') (2') tRESS tRESH tDS tDH (8191) tDS tDH (0) (1) (2) (3) tAC tOH8192 cycle WE, RE = "L"
  • n-bit delay bit (Reset at cycles according to the delay length) n cycle n+1 cycle n+2 cycle WCK RCK n-2 cycle n-1 cycle0 cycle 1 cycle 2 cycle Dn (0') (1') (2') Qn tRESS tRESH tDS tDH (n-1) tDS tDH (0) (1) (2) (3) tAC tOHm cycle n+3 cycle (3') tRESS tRESH WE, RE = "L" m ‡3

MITSUBISHI <DIGITAL ASSP> RRES

  • n-bit delay 2 (Slides input timings of WRES and RRES at cycles according to the delay length.) n+1 cycle n+2 cycle n+3 cycle WCK RCK n-1 cycle n cycle0 cycle 1 cycle 2 cycle tDS tDH tDS tDH tRESS tRESH Dn Qn (1) (2) (3) tAC tOHm cycle n-2 cycle tRESS tRESH (0) WE, RE = "L" WRES tNREH tRES n+1 cycle n+2 cycle n+3 cycle WCK RCK n-1 cycle n cycle0 cycle 1 cycle 2 cycle tDS tDH tDS tDH tRESS tRESH Dn Qn (1) (2) (3) tAC tOH (0)HIGH-Z
  • n-bit delay 3 (Slides address by disabling RE in the period according to the delay length.) WE, RE = "L" m ‡3 WRES RRES RE m cycle

MITSUBISHI <DIGITAL ASSP> Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.

  • Reading shortest n-cycle write data "n" (Reading side n-1 cycle starts after the end of writing side n-1 cycle.) WCK Dn RCK Qn n-2 cycle n-1 cycle n cycle invalid (n) (n) (n+1) n+1 cyclen cycle n+3 cyclen+2 cycle (n+2) (n+3) When the reading side n-1 cycle starts before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid. In the following diagram, reading operation of n-1 cycle is invalid.
  • Reading longest n-cycle write data "n": 1 line delay (When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts.) Qn WCK Dn RCK (n)<1>* (0)<2>*

MITSUBISHI <DIGITAL ASSP> APPLICATION EXAMPLE Sub Scan Resolution Compensation Circuit with Laplacean Filter M66258 D0 Q0– D7 Q7 1 line delay M66258 Adder A+B Subtracter 2N-(A+B) XK Adder N+K {2N-(A+B)} Compensated image data B (n+1) line image data A (n+1) line image data N n line image data A X B Main scan direction (n-1) line n line (n+1) line N'=N+K { (N-A) + (N-B) } =N+K { (2N - (A+B) } K: Laplacean coefficient D0 Q0 D7 Q7 1 line delay Sub scan direction