M66257FP MITSUBISHI | Alldatasheet

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MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO)

DESCRIPTION

The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit double con- figuration which uses high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over mul- tiple lines. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between de- vices with different data processing throughput.

FEATURES

  • Memory configuration of 5120 words × 8 bits × 2 (dynamic memory)
  • Fully independent, asynchronous write and read operations APPLICATION Digital photocopiers, high-speed facsimile, laser beam print- ers. PIN CONFIGURATION (TOP VIEW) BLOCK DIAGRAM MEMORY ARRAY OF 5120-WORD × 8-BIT × 2 CONFIGURATION 1-LINE DELAY DATA ONLY MEMORY/ 2-LINE DELAY DATA ONLY MEMORY WRITE CONTROL CIRCUIT READ ADDRESS COUNTER READ CONTROL CIRCUIT WRITE ADDRESS COUNTER WE WRES WCK 18VCC 28VCC 36VCC WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT RE RRES RCK READ ENABLE INPUT READ RESET INPUT READ CLOCK INPUT

1 GND

19 GND

29 GND

2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 INPUT BUFFER DATA INPUT D 0 D 7 OUTPUT BUFFER DATA OUTPUT Q 00 Q 07 DATA OUTPUT Q 10 Q 17 DATA INPUT DATA OUTPUT READ ENABLE INPUT M66257FP READ RESET INPUT READ CLOCK INPUT WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT 352 343 334 325 316 307 298 289 2710 2611 2512 2413 2314 2215 2116 2017 1918 Q 00 ← Q 01 ← Q 02 ← Q 03 ← Q 04 ← Q 05 ← Q 06 ← Q 07 ← Q 10 ← Q 11 ← Q 12 ← Q 13 ← Q 14 ← Q 15 ← Q 16 ← Q 17 ← GND VCC ← D7 ← D6 ← D5 ← D4 ← D3 ← D2 ← D1 ← D0 ← WCK ← WRES ← WE ← RCK ← RRES ← RE VCC VCC GND GND Outline 36P2R-A ~~~

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) FUNCTION When write enable input WE is “L”, the contents of data inputs D 0 to D7 are written into 1-line delay data only memory in syn- chronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data only memory is also incremented simultaneously. The write functions given below are also performed in syn- chronization with rise edge of WCK. When WE is “H”, a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line delay data only memory is stopped. When write reset input WRES is “L”, the write address counter of 1-line delay data only memory is initialized. When read enable input RE is “L”, the contents of 1-line delay data only memory are output to data outputs Q 00 to Q07 and those of 2-line delay data only memory to data outputs Q10 to Q 17 in synchronization with the rise of read clock input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented simulta- neously. Moreover, data of Q 00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK. At this time, the write address of 2-line delay data only memory is incremented. The read functions given below are also performed in syn- chronization with rise edge of RCK. When RE is “H”, a read operation from both of 1-line delay data only memory and 2-line delay data only memory is inhib- ited and the read address counter of each memory is stopped. The outputs of Q 00 to Q07 and Q10 to Q17 are in the high impedance state. Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay data only memory is stopped. When read reset input RRES is “L”, the read address counter of 1-line delay data only memory, and the write address counter and read address counter of 2-line delay data only memory are initialized.

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted) Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Unit V V V mW Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 660 –65 ~ 150 Conditions A value based on GND pin T a = 25°C RECOMMENDED OPERATING CONDITIONS Max. 5.5 Typ. Min. 4.5 Unit V V Parameter Supply voltage Supply voltage Operating ambient temperature Symbol V CC GND Topr Limits ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V , unless otherwise noted) Parameter “H” input voltage “L” input voltage “H” output voltage “L” output voltage “H” input current “L” input current Off state “H” output current Off state “L” output current Operating mean current dissipa- tion Input capacitance Off state output capacitance Symbol V IH VIL VOH VOL IIH IIL IOZH IOZL ICC C I C O Max. 0.8 0.55 1.0 –1.0 5.0 –5.0 120 Typ.Min. 2.0 VCC –0.8 Unit V V V V mA mA mA mA mA pF pF Limits Test conditions IOH = –4mA IOL = 4mA VI = VCC VI = GND VO = VCC VO = GND VI = VCC , GND, Output open tWCK , tRCK = 25ns f = 1MHz f = 1MHz WE, WRES, WCK, RE, RRES, RCK, D 0 ~ D7 WE, WRES, WCK, RE, RRES, RCK, D 0 ~ D7

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted) Parameter Access time Output hold time Output enable time Output disable time Symbol t AC tOH tOEN tODIS Max. Typ.Min. Unit ns ns ns ns Limits TIMING CONDITIONS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V , unless otherwise noted) Parameter Write clock (WCK) cycle Write clock (WCK) “H” pulse width Write clock (WCK) “L” pulse width Read clock (RCK) cycle Read clock (RCK) “H” pulse width Read clock (RCK) “L” pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset nonselect setup time to WCK or RCK Reset nonselect hold time to WCK or RCK WE setup time to WCK WE hold time to WCK WE nonselect setup time to WCK WE nonselect hold time to WCK RE setup time to RCK RE hold time to RCK RE nonselect setup time to RCK RE nonselect hold time to RCK Input pulse rise/fall time Data hold time (Note 1) Symbol t WCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Max. Typ.Min. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Limits Note 1: For 1-line access, the following should be satisfied: WE “H” level period < 20ms – 5120 tWCK – WRES “L” level period RE “H” level period < 20ms – 5120 tRCK – RRES “L” level period 2: Reset the IC after power is turned on.

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) TEST CIRCUIT VCC R L=1kΩ R L=1kΩ SW1 SW2 C L=5pF : tOEN , tODIS Q n Q n C L=30pF : tAC , tOH Input pulse level : 0 ~ 3V Input pulse rise/fall time : 3ns Decision voltage input : 1.3V Decision voltage output : 1.3V (However, t ODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of that for decision). The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe. Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH) SW1 Closed Open Closed Open SW2 Open Closed Open Closed tODIS /tOEN TEST CONDITION RCK 1.3V 90% 10% 1.3V GND tODIS(HZ) tODIS(LZ) 1.3V 1.3V tOEN(ZH) tOEN(ZL) RE Q 0n Q 1n Q 0n Q 1n GND VOH VOL

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) OPERATING TIMING

  • Write cycle
  • Write reset cycle (n) tWCK tWCKH tWCKL tWEH tNWES tDS tDHtDS tDH tNWEH Cycle n Cycle n+1 Cycle n+2 Disable cycle Cycle n+3 Cycle n+4 tWES WCK WE WRES = “H” D n tWCK tNRESH tRESS tRESH tNRESS tDHtDStDHtDS Cycle n–1 Cycle n Reset cycle Cycle 2 Cycle 0 Cycle 1 WCK WRES WE = “L” D n

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO)

  • Read cycle
  • Read reset cycle tRCK tRCKH tRCKL tREH tNRES tNREH tRES tODIS HIGH-Z tAC tOEN tOH Cycle n Disable cycle Cycle n+3 Cycle n+4Cycle n+2Cycle n+1 RCK RE RRES = “H” Q 0n Q 1n tRCK tNRESH tRESS tRESH tNRESS tAC tONtONtON Cycle n–1 Cycle 0 Cycle 2Cycle n Reset cycle Cycle 1 RCK RRES RE = “L” Q 0n Q 1n

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) tDS tDH tDS tDH (n) (n) n cycle n+1 cycle n cycle Disable cycle WCK WE D n tWCK Period of writing data (n) into memory tNWES Period of writing data (n) into memory WRES = “H”

  • Note at WCK stop Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the “L” period of WCK of n+1 cycle and ends at the rising edge after n+1 cycle. To stop reading write data at n cycle, input WCK for up to the rising edge of n+1 cycle. When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO)

  • Shortest read of data “n” written in cycle n Cycle n–1 on read side should be started after end of cycle n+1 on write side When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n–1 is invalid.
  • Longest read of data “n” written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* over- lap each other. invalid (n) Cycle n Cycle n+1 Cycle n+2 Cycle n+3 Cycle n–2 Cycle n–1 Cycle n WCK RCK D n Q n WCK RCK D n

MITSUBISHI 〈DIGITAL ASSP 〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction. D 0 D 7 M66257 1-line delay Adder A+B Q 00 Q 07 Q 10 Q 17 Line (n–1) Line n Line (n+1) Subtractor 2N–(A+B) Adder N+K {2N–(A+B)} N' = N+K {(N–A)+(N–B)} = N+K {2N–(A+B)} K : Laplacean coefficient 2-line delay A N B B Line (n+1) image data A Line (n–1) image data N Line n image data Corrected image data Secondary scanning direction Primary scanning direction