M66256FP MITSUBISHI | Alldatasheet

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MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO)

DESCRIPTION

The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between de- vices with different data processing throughput.

FEATURES

  • Fully independent, asynchronous write and read operations
  • Variable length delay bit APPLICATION Digital photocopiers, high-speed facsimile, laser beam print- ers. PIN CONFIGURATION (TOP VIEW) BLOCK DIAGRAM DATA INPUTDATA OUTPUT DATA OUTPUT DATA INPUT READ ENABLE INPUT WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT READ RESET INPUT READ CLOCK INPUT M66256FP Q 0 ← Q 1 ← Q 2 ← Q 3 ← RE → RRES → GND RCK → Q 4 ← Q 5 ← Q 6 ← Q 7 ← ← D0 ← D1 ← D2 ← D3 ← WE ← WRES ← WCK VCC ← D4 ← D5 ← D6 ← D7 MEMORY ARRAY OF 5120-WORD × 8-BIT CONFIGURATION WRITE CONTROL CIRCUIT READ ADDRESS COUNTER READ CONTROL CIRCUIT WRITE ADDRESS COUNTER WE WRES WCK VCC WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT RE RRES RCK GND READ ENABLE INPUT READ RESET INPUT READ CLOCK INPUT INPUT BUFFER DATA INPUT D 0 D 7 OUTPUT BUFFER 14 15 16 21 22 23 24 1 2 3 4 9 10 11 12 DATA OUTPUT Q 0 Q 7 Outline 24P2U-A

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) FUNCTION When write enable input WE is “L”, the contents of data inputs D 0 to D7 are written into memory in synchronization with rise edge of write clock input WCK. At this time, the write address counter is also incremented simultaneously. The write function given below are also performed in synchro- nization with rise edge of WCK. When WE is “H”, a write operation to memory is inhibited and the write address counter is stopped. When write reset input WRES is “L”, the write address counter is initialized. When read enable input RE is “L”, the contents of memory are output to data outputs Q 0 to Q7 in synchronization with rise edge of read clock input RCK. At this time, the read address counter is also incremented simultaneously. The read functions given below are also performed in syn- chronization with rise edge of RCK. When RE is “H”, a read operation from memory is inhibited and the read address counter is stopped. The outputs are in the high impedance state. When read reset input RRES is “L”, the read address counter is initialized. ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted) Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Unit V V V mW Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 440 –65 ~ 150 Conditions A value based on GND pin T a = 25°C RECOMMENDED OPERATING CONDITIONS Max. 5.5 Typ. Min. 4.5 Unit V V Parameter Supply voltage Supply voltage Operating ambient temperature Symbol V CC GND Topr Limits ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V) Parameter “H” input voltage “L” input voltage “H” output voltage “L” output voltage “H” input current “L” input current Off state “H” output current Off state “L” output current Operating mean current dissipa- tion Input capacitance Off state output capacitance Symbol V IH VIL VOH VOL IIH IIL IOZH IOZL ICC C I C O Max. 0.8 0.55 1.0 –1.0 5.0 –5.0 Typ.Min. 2.0 VCC –0.8 Unit V V V V mA mA mA mA mA pF pF Limits Test conditions IOH = –4mA IOL = 4mA VI = VCC VI = GND VO = VCC VO = GND VI = VCC , GND, Output open tWCK , tRCK = 25ns f = 1MHz f = 1MHz WE, WRES, WCK, RE, RRES, RCK, D 0 ~ D7 WE, WRES, WCK, RE, RRES, RCK, D 0 ~ D7

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V) Parameter Access time Output hold time Output enable time Output disable time Symbol t AC tOH tOEN tODIS Max. Typ.Min. Unit ns ns ns ns Limits TIMING CONDITIONS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted) Parameter Write clock (WCK) cycle Write clock (WCK) “H” pulse width Write clock (WCK) “L” pulse width Read clock (RCK) cycle Read clock (RCK) “H” pulse width Read clock (RCK) “L” pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset nonselect setup time to WCK or RCK Reset nonselect hold time to WCK or RCK WE setup time to WCK WE hold time to WCK WE nonselect setup time to WCK WE nonselect hold time to WCK RE setup time to RCK RE hold time to RCK RE nonselect setup time to RCK RE nonselect hold time to RCK Input pulse rise/fall time Data hold time (Note 1) Symbol t WCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Max. Typ.Min. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Limits Notes 1: For 1-line access, the following should be satisfied: WE “H” level period ≤ 20ms – 5120 tWCK – WRES “L” level period RE “H” level period ≤ 20ms – 5120 tRCK – RRES “L” level period 2: Perform reset operation after turning on power supply.

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) TEST CIRCUIT VCC R L=1kΩ R L=1kΩ SW1 SW2 C L=5pF : tOEN , tODIS Q n Q n C L=30pF : tAC , tOH Input pulse level : 0 ~ 3V Input pulse rise/fall time : 3ns Decision voltage input : 1.3V Decision voltage output : 1.3V (However, t ODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of that for decision). The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe. Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH) SW1 Closed Open Closed Open SW2 Open Closed Open Closed tODIS /tOEN TEST CONDITION RCK 1.3V 1.3V GND GND VOH VOL 90% 10% 1.3V 1.3V tODIS(HZ) tODIS(LZ) tOEN(ZL) tOEN(ZH) RE Q n Q n

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) OPERATING TIMING

  • Write cycle
  • Write reset cycle tWCK tWCKH tWCKL tWEH tNWES tDS tDHtDS tDH tNWEH Cycle n Cycle n+1 Cycle n+2 Disable cycle Cycle n+3 Cycle n+4 tWES WCK WE WRES = “H” D n tWCK tNRESH tRESS tRESH tNRESS tDHtDStDHtDS Cycle n–1 Cycle n Reset cycle Cycle 2 Cycle 0 Cycle 1 WCK WRES WE = “L” D n

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) tDS tDH tDS tDH (n) (n) n cycle n+1 cycle n cycle Disable cycle WCK WE D n tWCK Period for writing data (n) into memory tNWES Period for writing data (n) into memory WRES = “H”

  • Matters that needs attention when WCK stops Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO)

  • Read cycle
  • Read reset cycle tRCK tRCKH tRCKL tREH tNRES tNREH tRES tODIS HIGH-Z tAC tOEN tOH Cycle n Disable cycle Cycle n+3 Cycle n+4Cycle n+2Cycle n+1 RCK RE RRES = “H” tRCK tNRESH tRESS tRESH tNRESS tAC tOH Cycle n–1 Cycle 0 Cycle 2Cycle n Reset cycle Cycle 1 RCK RRES RE = “L” Q n

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) VARIABLE LENGTH DELAY BITS

  • 1-line (5120 bits) delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
  • N-bit delay bit (Making a reset at a cycle corresponding to delay length) tDS tDH tDS tOHtACm cycles tDH tRESS tRESH tRESS tRESH (0) Cycle 0 Cycle 1 Cycle 2 Cycle n–2 Cycle n–1 Cycle n (0') Cycle n+1 (1') Cycle n+2 (2') Cycle n+3 (3') WCK RCK D n Q n WE, RE = “L” WRES RRES (0) (1) (2) (3) tDS tDH tDS tOHtAC5120 cycles tDH tRESS tRESH (0) (1) (2) (3) Cycle 0 Cycle 1 Cycle 2 Cycle 5118 Cycle 5119 Cycle 5120 (0') Cycle 5121 (1') Cycle 5122 (2') WCK RCK WRES RRES WE, RE = “L” D n Q n m ≥

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) (Sliding WRES and RRES at a cycle corresponding to delay length)

  • N-bit delay 3__ (Disabling RE at a cycle corresponding to delay length) m cycles tRESS tRESH tDS tDHtDS tDH (0) (1) (2) (3) Cycle 0 Cycle 1 Cycle 2 Cycle n–2 Cycle n–1 Cycle n Cycle n+1 Cycle n+2 Cycle n+3 WCK RCK D n Q n WE, RE = "L" m ≥ 3 tAC tOH tRESS tRESH RRES WRES m cycles HIGH-Z tNREH tRES tRESS tRESH tDS tDHtDS tDH (0) (1) (2) (3) Cycle 0 Cycle 1 Cycle 2 Cycle n–1 Cycle n Cycle n+1 Cycle n+2 Cycle n+3 WCK RCK D n Q n WE = “L” m ≥ 3 WRES RRES RE tAC tOH

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO)

  • Shortest read of data “n” written in cycle n Cycle n–1 on read side should be started after end of cycle n+1 on write side When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n–1 is invalid.
  • Longest read of data “n” written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* over- lap each other. invalid (n) Cycle n Cycle n+1 Cycle n+2 Cycle n+3 Cycle n–2 Cycle n–1 Cycle n WCK RCK D n Q n WCK RCK D n

MITSUBISHI 〈DIGITAL ASSP 〉 M66256FP 5120 × 8-BIT LINE MEMORY (FIFO) APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction. D 0 D 9 M66256 1-line delay Adder A+B ~ Q 0 Q 9 ~ D 0 D 9 M66256 Line (n–1) Line n Line (n+1) Subtractor 2N–(A+B) Adder N+K {2N–(A+B)} N' = N+K {(N–A)+(N–B)} = N+K {2N–(A+B)} K : Laplacean coefficient 1-line delay ~ Q 0 Q 9 ~ A N B B Line (n+1) image data A Line (n–1) image data N Line n image data Corrected image data Secondary scanning direction Primary scanning direction