M66250FP

M66250P MITSUBISHI | Alldatasheet

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MITSUBISHI <DIGITAL ASSP > 5120 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION

The M66250P/FP is a high-speed line memory with a FIFO PIN CONFIGURATION (TOP VIEW) (First In First Out) structure of 5120 -word8-bit configura- tion which uses high-performance silicon gate CMOS pro- lo Gy [22] ~~ Do | cess technology. ara ours a~ Ee OT oasaneus The M66250 can also be used for LIFO (Last In First Out) jor a | The start address of reading can be specified. nent is fle we | wareeats It has separate clock, enable and reset signals for write [rots es Te z fl wes voremee and read and is most suitable as a buffer memory between (oviend 2 EI Vecisv) devices with different data processing throughput. Fer ee RCK -- g l—wer feet 3 - | aE 3 Ds | FEATURES oancuns | Oo Bo Bes © Memory configuration of 5120 words X 8 bits (dynamic | os - Hy [De | memory) anoness. o,f FD D7) cmap cxcon veut + - Se Par © High-speed cycle «sree eseeeen $0n8 (Min) co eed Enc, Se © High-speed access sss seieeeesseenees 4Ons(Max.) — poesiirurtse BARS) OB ne Nes © Output hold vss sees ssseeseseseenemnseeeneeee ns (Min.) 2apay weur © FIFO/LIFO switching function Outline 28P2W-C @ Start address specification function (at reading) © LIFO operation on single chip e i i Note 1: SRES sets the system reset mode. Built in ullup/pulidewn resistor for the mode control pin Note 2: LAE can switch to a validness or invalidness of start © Write and read operations can be performed separately. address except during instruction cycles. ® Variable-length delay bit © Output rnrsninernnannnnenennnnenn3.Sta® APPLICATION High-speed facsimiles, digital photocopiers, laser beam printers. BLOCK DIAGRAM ____DATAINPUTS DATA OUTPUTS Dp 1D; D304 05060; Oy G, 0203 0,0, 0,0, ( pager? PLOGP PDE | L im | — i | i ' 8 35 MEMORY ARRAY 35 418 ! WRITE RESET ——_ 3 g La 8 4 ” WRES @ 2 28 a “6) ARES REAO RESET INPUT 5 erg si20x@ Bits, 3g ros { ARES INPUT ware i z H 3 é : Sneur WCK @) g Ea ® 3 @ ACK AEADCLOCK & iNeur | q | = | | —= conaot cincuit ef — | =f dg 4 | ACK SA M/A cE aooness (SRES) (LAE) COMMAND CLOCKINEUT Seniae «= MODE/_—-ENABLE INPUT ADORESS _ ADDRESS INPUT) SELECTION INPUT MITSUBISHI re SBS

MITSUBISHI <DIGITAL ASSP) 5120 8-BIT LINE MEMORY(FIFO/LIFO) FUNCTION When RE is high-level, read is prohibited, and the read Write is performed by taking in the content of data inputs address counter stops. The output enters the floating state Do~Dr, in synchronous with the rise of the write clock input (high-impedance state). WCK, when write enable input WE is low-level, the write When the read reset input RRES is set to low-level, the address counter incrementing or decrementing simul- read address counter is initialized. taneously. When WE is high-level, write is prohibited and = When command enable input CE is low-level, the instruc- the write address counter stops. When the write reset input __ tion cycle is enabled. The FIFO/LIFO mode is set by the WRES is set to low-level, the write address counter is in- _ serial address input SA in synchronous with the rise of the itialized. When the read enable input RE is low-level, read address clock input ACK during the instruction cycle when is performed by outputting the memory content to data out- the mode/address selection input M/A is high-level. The put Qo~Q; in synchronous with the rise of the read clock __ start address is set by the serial address input SA in syn- input RCK, and the read address counter is incremented or —_chronous with the rise of the address clock input ACK dur- decremented at same time ing the instruction cycle when M/A is low-level. FUNCTIONAL DESCRIPTION 1. Function Setting (1) Function setting table @ System reset setting z (SA) | aare CE — HoT ek L t FIFO mode, no start address setting, read counter reset se | 654) |aoee Ce | Smeg | WRES we | Fuction Wop 1 | FIFO mode, no stan address soiting, wito counter eset @ Mode setting == | M/A SA [| Hf t | | FiFo mode setting [eT 0 mode seting XiLorH Note : The above mode becomes effective after the first reset. @® Effect of start address setting —_ SA | (M/A) | [H | _H_ | UL | C_| tf _| Star edcress setting i effective [LH fH | H | | t _| Startaddress setting is not effective MITSUBISHI aes

MITSUBISHI <DIGITAL ASSP > M66250P/FP 5120X8-BIT LINE MEMORY(FIFO/LIFO) (2) FIFO/LIFO mode setting input WRES is low-level, mode setting is completed in syn- When the mode/address selection input M/A is high-level __chronous with the rise of the write clock input WCK, also and the command enable input CE is low-level, the FIFO/- _ provided that the write reset input WRES is low-level, in LIFO mode is selected by the serial address input SA, in _ synchronous with the rise of the read clock input RCK and synchronous with the address clock input ACK. When the the read reset input RRES is low-level. The address coun- command enable input CE is high-level and the write reset _ter is initialized at the same time. wk a (tae) tC Ce _ ES Ld RES wares LC Cy RCK wCK

1 Mode setting is completed

In the FIFO mode, the write address counter moves to (3) Start address setting address 0 in synchronous with the rise of the write clock in- When the mode/address selection input M/A is low-level put WCK when the write reset input WRES is set to low- and the command enable input CE is low-level, the level. The address of the write address counter increases —_address that reading starts from is set by serial address in- in synchronous with the rise of the write clock input WCK. put SA in synchronous with the rise of the address clock in- When the read reset input RRES is low-level, the read put ACK. When the command enable input GE is high-level address counter moves to address 0 if the start address is and the read reset input RRES is low-level, the read not specified, and moves to the start address if the start address counter moves to the specified address in syn- address i8 specified, in synchronous with the rise of the chronous with the rise of the read clock invut RCK. read clock input RCK, The cycles of the read address counter increases in synchronous with the read clock input RCK. In LIFO mode the write address counter moves to address 0 or 5119 in synchronous with the rise of write clock input WCK, when the write reset input WRES is low-level, and, the read address counter moves to address 0 or 5119 if the start address is not specified or to the start address m or 5119-m if the start address is specified, in synchronous with the rise of the read clock input RCK. When the read reset input RRES is low-level. The cycle of the write address counter goes up or down in synchronous with the rise of the write clock input WCK. MITSUBISHI ae TRS

MITSUBISHI <DIGITAL ASSP>

5120 X8-BIT LINE MEMORY(FIFO/LIFO)

wk twas wan | | usen (THE) | po} é teess a ‘san, teas Team teas toan tas SA tans a U MSB 12 " 10 1 0 RRES: ‘a | RCK

1 Start address setting is completed

(4) System reset setting (FIFO and address counter reset setting) When the command enable input CE is high-level and SRES is low-level, and if the write reset input WRES and read reset input RRES are set to low-level, then the FIFO mode setting and the address counter are reset in synchro- nous with the rise of WCK and RCK. CE teese Toene tenes: tsresn SA SRES tess taesh wox t RCK WARES RRES | (Note) To unetfect system reset, SA(SRES) should be set to high-level during WRES and ARES are low-level MITSUBISHI palteRs

MITSUBISHI <DIGITAL ASSP> 5120X8-BIT LINE MEMORY(FIFO/LIFO) 2. Write address and read address operation in FIFO and LIFO mode FIFO and LIFO Write addresa/road address in read Start address setting Write address and read address operation mode setting roset/write reset operation FIFO. No | | Wrte address | i‘ w A 5119 | | i — = — — — =" | wate address : address counter is set to 0 | | 0 R A 5119 | Read address : address counter is sot to 0 _— a | nesseone Ot +, | LFO ° © Read address 9 RUD Write address 9 sw SN @® Read address je read tho write data | Wite address: the set addrass of 0 or 5119 | is set mutually. Write address je WO Ce | .d the write data@® | Read address : the set address of 0 or 5119 read the write data’ ‘is set mutually. Write addrese ; Wy FIFO | Yes White addre | te address 0 Ww A 5119 | Titan arn comtriato 0 | 0 _,m__R_A __ 5119 | Read address : address counter is set to m which Is Readaddress (2 | specified by the start address } C2 2 | | | i \\ | | | LIFO Ye 19+ i es © Read address sigma 88 | Wiite address : the sot address of 0 or S119 | mutual | Write address }_W Vast meaty | 1@ Read address je—R | | read the write data D | Write address wy Road address : address counter Is set to address which is specified as tho start ' @ Read address a vasrese | rend he wit data | | | | write address | Woy | i MITSUBISHI ELECTRIC

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) OPERATION FLOW CHART Sete eset Po | | ! | l l | 1 \\ FIFO mode | SA (address) SA (Address) ack ot ack ot Y Y CEs “H" ce= Hn” SRES= “x” SRES= “H” Start address Start address 1s not effective is not effective Start addres Start address is effective is effective wok +t} [rock t} [wok __t| Lack t Rok ft} pwok ty Lack ot] [wok t Write from | | Read from Write Read from| Read trom] | write from] | Read trom } | Write from start address, address start address address 0 | | address address 0 | | address 0 Oersiis | | oorsira | | searess Dor5119 Start address eS VY . , FIFO mode LIFO mode Note : Perform write reset and read reset before setting function after power-on,

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MITSUBISHI <DIGITAL ASSP>

5120 X 8-BIT LINE MEMORY (FIFO/LIFO)

ABSOLUTE MAXIMUM RATINGS (1a=~20+706, unless otherwise noted) ["Symbor] Parameter Conditions Ratings ‘Supply voltage =0.5~+7.0 | vi [input votage =0.5~Voo-+0.5 Vo Output voltage te =0.5~Vect0.5 Pq ____| Maximum power dissipation Ta=25e ___550(Note 1) Tstg Storage temperature range =65 ~+150 Note 1: Tax68°C are derated at —9, 7mw/'C (28P,W) RECOMMENDED OPERATING CONDITIONS (12=-20~+70) fm [oe rel | ves | Sippivvotege a | | ano [aroun [Tope | Operainganbion wempuraurerange a ee | ELECTRICAL CHARACTERISTICS (ta-—20~+70°, Voc=5v+10%, unless otherwise noted) fee ee | ee Mie Lowievel input voltage re Vou High-level output voltage lon=—4mA . Mco—0. 8 v Low-level output voltage —_ io=ima 7 v Vi=Vec | WE, WRES, WCK, RE, RRES, A ACK, CE, Do~D7 “ ok, SABRES). WATER) —[ a | a] Vi=GND | WE, WRES, WCK, RE, RRES, RCK, ACK, SA(SRES), 1.0 uA tne Low-level input current WACLAE), Do~b? - tf _ ce =0.27 | mA [ tozn | Off state Kioh-level output current Ve=Veo [Tso | a] loz. | Off state 1ow-lovel output current Vo=GNO [[=s0 tna] Vi=Vin. Vi, Output open ve i loo Average operating supply current twig taox™=100n8 | ft | fom Input capacitance teiMiz _ fo io | pF Output capacitance when a (mite i 15 | pF SWITCHING CHARACTERISTICS (ta=-20~+70C, Voo= 5 V210%, unless otherwise noted) fee me | tac | Access ime {| 40 [ns | Output od te a Output “L* period when reset a ee toon Output enable time _ a - 5 | | 4 | toors | Output dieable time sj | 40 | ns] SK EES MITSUBISHI ae ELECTRIC

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120 8-BIT LINE MEMORY (FIFO/LIFO) TIMING REQUIREMENTS (1a=—20~+70°. Voc= 5 V+10%, unless otherwise noted) Lirnts| Symbol Parameter Test conditions ape 4 Unit Min. [ Typ. | Max twox __| Write clock (WK) cycle oO fT 50 ns twoxn | Write clock (WGK) “H" pulse width _ — al | ns ‘wort __| Write clock (WCK) *L* pulse width 25 tnox | Read clock (ACK) “H" pulse width — a | | [tncxt | Read clock (ROK) “L” pulse width ee 25 ns | tos __| Data set up time betore WCK _ 15 [_ns_| tow Data hold time ater WGK 5 ns [tnass | Reset setup time botore WOK ROK I is a tuean [Reset hold time alter WOK, RCK = ae “tuness _| Non-reset set up time before WOK, RK _ Fa ee | tuinesrs | Non-reset hold time after WOK, ROK 7 5 ns “lwes | WEsset uptime before WOK _| 15 : ns twen WE hold time after WOK Sd 3 as | tuwes | WE non-select sot up time before WOK | “1s [ns tuwen WE non-select hold time atter WOK 5 ns “tars | RE setup time betore ACK ~ — 15 tons then RE hold time atter RCK_ oe ~~ _ 5 | as | “tunes | AE nonselect setuptimebetre ACK S™S~S~S is_| a tunen | RE non-selectholdtime afterRCK 5 __ ns te, 4___| Input pulse rise and fall time SY [20 Note 1: For 1 line access, the following should be satis fil WE “H" level period< 20ms—5120-twox- WRES “L" level period RE “H" level period= 20ms—5120-tnc- ARES "L level period TIMING REQUIREMENTS (ta=—20~+706, Voc= 5 V+10%, unless otherwise noted) Limits symbol Parameter Tost conditions — unit a oe Min [typ | Man | tran M/A hold time ater ACK _ 5 ns_| toes: | CEsetuptime before ACK 3 | || ns | tens | CE hold time atter ACK OO 8 yas _| tons | SA setup time before ACK — [ons | toan SA hold time after ACK 5 ns Tuaes | LAE set up time before WOK, ACK ——— Fa en ce tren | LAE hold time ater WOK,ACK __ 3s | ns teas | SAH" sot up timo betore WOK, ROK when reset —— (3s 18 tsann | SA“H" hold time after WOK, ROK when reset __ ~~ 5 [ns toese __| OE set up time betore WOK, RGK when system rest [25 [ons] toene GE hold time after WOK, RCK when system reset Ss as 'SRES hold time after WOK, ROK when system reset +2+— ns tacke | “L pulse width for ACK _ ~| [ns “tnecn | WCK, ACK recovery time after mode set t—| ras | tnecce | GE recovery time alter eset =” [100] ne

9 MITSUBISHI

MITSUBISHI <DIGITAL ASSP> R.=1kQ ; swi L308 F tao, ton ao. : I miko : T C.=5PF | toon, toors {input puise amplitude i0~3v Input pulse rise and fall time: 3ns toorsuz) | Close | Open Reference voltage Input 21.3V 1 va Se Close] Output 1.3V. (However, tooiscu2) I 1096 of output tooveue)| Or a amplitude and toorsiy2) 18 9096 of foenczu) _Open_ that for decision). toswiz | Open _| Close Load capacity C, includes float capacity of connection and input capacity of probe. tovis, toe Test Condition CK 1.3 1.3V sevtseneeneeee: GND RE sevtntneueneeess GND tomate toen(zH) 50% ssesnnsssnes Voy @n | 1.3V Qn L-1.3v 10% Nn eeetstsenene: Yop MITSUBISHI a iteas

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120X8-BIT LINE MEMORY(FIFO/LIFO) OPERATION TIMING 1. FIFO mode @ Write cycle (This operation timing is irrelevant to start address setting) noycle ntl oycle __n+2 cycle Disable cycle nt3 cycle nt4 cycle wen mune won | twen twes we | tos. | tow tos | ton » TTTMTIK 2 KX ce Nike NULPTTTTTITTTTL 2 XK 2 XD SRES= “H” © Write reset cycle (Irrelevant to start address setting) (The reset cycle requires a minimum of two cycles. Before the first reset cycle and after the power is turned on WRES should be set to high-level for 1 cycle or more.) ntl cycle neycle Reset cycle O cycle Voycle 2 cycles we mY fos ton LTT = AK XIII TIX © XX XX 2 YX) ‘SRES “H"

MITSUBISHI <DIGITAL ASSP> 5120X8-BIT LINE MEMORY(FIFO/LIFO) © Matters that needs attetion when WCK stops We a as a ° LM LLL Lo © NUE: » LK © KUL LLL. Period for writing data Period for writing data (n) into memory (n) into memory WARES ="H" Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-ievel period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well. MITSUBISHI ae ELECTRIC

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120 8-BIT LINE MEMORY(FIFO/LIFO) @ Read cycle (This operation timing Is Irrelevant to start address setting) __neyole ntloycle nt2 cycle Disable cycle nt3oycle nA cycle * ry a HIGH-z ~ TT OK) Tos | ton ton ‘SRES= “H" © Read reset cycle (The reset cycle requires two cycles at minimum. During the first two cycles Qn is low-level. For one cycle or more, ARES should be set to high-level befor the first reset cycle, and after power is turned on.) n~1 cycle ncycle Reset cycle O cycle Leycle 2 cycle ARES mR “s ~ TT 0 1 00 RE= “u" ,TAE= “H” ‘SRES= “H” eee MITSUBISHI aa lteRs

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120 8-BIT LINE MEMORY(FIFO/LIFO) © Read reset cycle (start address Is set) (The reset cycle requires two cycles at minimum. During the first two cycles, Qn is low-level. For at least one cycle RRES should be set to high-level before the first reset cycle, and after power is turned on.) cycle cycle cycle) neycle Reset cycle meycle cycle cycle cycle tnecn _ Ta - | on MTR KX Xo Ko KX) AX = XK Korte Kets) M/K (CAE) taecce ce | x XeaXX@Y ACK J \\--f \\ FE= “L" MITSUBISHI ees

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120X8-BIT LINE MEMORY(FIFO/LIFO) 2. LIFO mode © Start address is not set (The reset cycle requires two cycles at minimum. During the first two cycles, Qn is low-level. For at least one cycle, RRES should be set to high-level and WRES should be set to high-level before the first reset cycle and after power is tumed on.) ge See Reset cycle Gyae ole Oeycle Reset cycle | Ocycle 1 cycle RCK N cycle Noycle WRES ‘ARES: / (/ Ko (/ (/ Uke KK Kee TILT Ke X Ke XK © XT K © XK on XKeeXKer) CK KenX 2) Ke XK Nz3 RE,WE = “L" TE ="H" e ="H" SRES =H" EE are MSR ELECTRIC

MITSUBISHI <DIGITAL ASSP) ©@ Start address is set (The reset cycle requires two cycles at minimum, and the first two cycles Qn is low-level. More than one cycle should be set when ARES is high-level before the first reset cycle after power on.) 5119—m+3 5119—m+2 5119—m+1 5119—m cycle cycle cycle cycle Reset cycle Ocycle meycle Reset cycle 5119 cycle 5119—m 5119 3 cycle 2 cycle 1 cycle O cycle Reset cycle cycle cycle Reset cycle m cycle tagca N cycle RRES: Ey POSS = XK ZILLI XK XL OK SOK DOEXKDYOXOD>_ 5, KOK XK _, KKK M/A (TAE)| $f gp tecce — py ce LX Sh ACK eee we NGS Nl N23 RE, WE= “L” a MITSUBISHI ae ELECTRIC

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) 3. Variable length delay bits (1) FIFO mode/without setting of start address @ 1-line (5120 bits) delay A write input data is written to memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge ‘of RCK in the cycle, so that 1-line delay can be made easily (A reset cycle requires at least 2 cycles. Qn goes to the “L” level during the first 2 cycles. However, it is necessary to set at least one cycle of RRES="H" and WRES="H” before the first reset cycle after power is turned on), cycle Cycle Cycle Cycle 5120 5121 5122 Reset cycle Cycle 0 | Cycle 1 5119 (0') (1) (2) wCK " RCK tress WRES | } , RRES || /—| =i QoemeneaaDeae Ps LLLLLL EK OKKIXKREXRE XK KK XKKEXD Ll [7 LY Qn LA) MLLLL GILL LLL LIK XOX EXD ae ERR ELECTRIC

MITSUBISHI <DIGITAL ASSP> 5120 8-BIT LINE MEMORY(FIFO/LIFO) © N-bit delay 1 (Sliding input timing of WAES and ARES at a cycle corresponding to delay length) (A reset cycle requires at least 2 cycles. Qn goes to the L” level during the first 2 cycles. However, it is necessary to set at least one cycle of RRES= “H" and WRES="H" before the first reset cycle after power is turned on). Reset cycle cycled | Cycle 1 Cycle n—2| Cyclen—1| Gyclen | Cycle n+] wek , RCK tress / : ae | RRES q J

0 TK OKA IKON

LL KKKYO KKK KX? N oycles ton on LLLLLLLLL LLL Lf L cD.¢ LLLL LD Non N23 © N-bit delay 2 (Disabling RE during the period corresponding to delay length to slide an address) (A reset cycle requires at least 2 cycles, Qn goes to the “L” level during the first 2 cycles. However, it is necessary to set at least one cycle of RAES= “H" and WRES="H" before the first reset cycle after power is turned on). Reset cycle Cycle 0 | Cycle 1 cycle n—1) Cycle n |Cycle n+1|Cycle n+2| wck : RCK TRESS WRES y 5 RRES RE [7 [v “|, {i >> IOI DIS tart Qe aes? HIGH-Z L KK XKND

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MITSUBISHI <DIGITAL ASSP) M662S50P/FP

5120 X8-BIT LINE MEMORY (FIFO/LIFO)

wees oo "tacom | | » TK open we » TTT, few NX Ma \\ » JAI TA Ano aaa

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120X8-BIT LINE MEMORY (FIFO/LIFO) @ N-m bit delay 2 (Disabling RE during the period corresponding to delay length to slide an address) a (A reset cycle requires at least 2 cycles. Qn goes to the L” level during the first 2 cycles. However, it is necessary to set at least one cycle of RRES= “H" and WRES="H" before the first reset cycle after power is turned on). WCK h RCK WRES TREGR | | RRES RE i am

9 LTEETEETETETETETETETETEEEETTTTTX © XK NK eM KON Kem

Qn (om 1} (m+1) Me, \\ cE i s TOON MMMM Tn (SRES) Ee teeny] ACK a ee WE, RE="L" Nz mis an address specified as a start address. m<n ae MTSUESH ELECTRIC

MITSUBISHI <DIGITAL ASSP> M66250P/FP 5120 8-BIT LINE MEMORY (FIFO/LIFO) (3) Inter-FIFO delay compensation by setting a start address FIFO! 3338 te EEE ETE eels} —> ome Delay FIFO2 7 TSE ERISA} —> oe FIFO2 With setting of start address Address 2 (A react arcs requires at east 2oyces, On 088 ‘0 the level uring the first 2 cycles. However, it is necessary to set at least one cycle of RRES= Reset cycle Cycle 0 Cycle 1 Cycle 2 ee See Gye Oye Oxee am corre TTT ONCE MENS ae Cenc MMIII CO NCO NCS SEE HEED = RRES1, 2 w oycee us ke on TMM. | Oe Love MMMM ee WE1, 2=RE1, 2="L" LAE!, 2="L" SRES!1, 2=“H" N23 ees ELECTRIC

MITSUBISHI <DIGITAL ASSP > 5120X8-BIT LINE MEMORY(FIFO/LIFO) © Shortest read of data n” written in cycle n Cycle n—1 on read side should be started after end of cycle n+1 on write side When the start of cycle n—1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n—t Is invalid { Cycle n i. _Cyclontt | Cyclent2_— |} Cyclent3 | pe Ot EY te Se? yl nS 7 ; Ff i 5 L_ oycte n-2 H Oyclen—t oycle n ol i j 1 f RCK f 4 p f y © Longest read of data “n” written In cycle n: 1-line delay Cyole n <1>* on read side should be started when cycle n <2>* on write Is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1* and the start of writing side n cycle <2* overlap each other. Hy Cycle n <1) . Cycle 0 <2>* Hi Cycle n <2) . ; j j ; j j wex 7 aN Nee Ne Aes ae oe 1 cyclen @* | 1 cycleo* } 1 oyclencp* } —_ — — Qn (n-1)<0>* Kino» X <1" (-1)41* (ay *, a)* and «D* indicates a line value. MITSUBISHI Jalen