M66238FP MITSUBISHI | Alldatasheet

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MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER

DESCRIPTION

The M66238 is a LSI that incorporates a PLL synthesizer and a sync clock generator in it. The PLL synthesizer covers the range of 25MHz to 50MHz at the minimum steps of 3kHz. The sync circuit outputs a clock and a one-shot pulse which are synchronized with an external trigger signal. Setting a dividing ratio allows acquisition of sync clock outputs within the range of 0.78MHz to 25MHz.

FEATURES

  • Sync clock output frequency range: 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of 25 to 50MHz
  • Sync accuracy (jitter): ±3ns
  • Trigger input: Polarity selectable
  • One-shot pulse output: Polarity and width selectable
  • 5V power supply APPLICATION Pixel clock generator BLOCK DIAGRAM PIN CONFIGURATION (TOP VIEW) 21 20 24 26 CS SIN SCLK XOUT RESET TR XIN TCKI TCKO CKO/PLLO CKOB PULSE SERIAL WRITE CONTROL CIRCUIT COMMAND REGISTER COMMAND CONTROL CIRCUIT CRYSTAL OSCILLATOR CIRCUIT 12-BIT DIVIDER 15-BIT COUNTER PHASE COMPARATOR CHARGE PUMP SYNC/DIVIDER CIRCUIT SYNC CLOCK GENERATOR ) fin fvcoVCO 25MHz ~ 50MHz UP DOWN CPOUT CPIN RV RESET INPUT CHIP SELECT INPUT SERIAL DATA INPUT SERIAL CLOCK INPUT CLOCK OUTPUT CLOCK INPUT TEST PIN PLL OUTPUT CLOCK OUTPUT ONE-SHOT PULSE OUTPUT VCO LOAD OUTPUT FILTER CONNECT PIN FILTER CONNECT PIN TEST PIN TRIGGER INPUT DGND 1 2RESET → CS → SIN → SCLK → XOUT ← XIN → DGND DVCC TCKI → TCKO ← CKO/PLLO ← CKOB ← PULSE ← VCCO GNDO AGND AVCC AGND → RV AVCC AGND ← CPIN AGND → CPOUT DGND DVCC → UP → DOWN DVCC DGND ← TR DIGITAL GND PIN RESET INPUT CHIP SELECT INPU T SERIAL DATA INPUT SERIAL CLOCK INPUT CLOCK OUTPUT CLOCK INPUT DIGITAL GND PIN DIGITAL POWER SUPPLY PIN TEST PIN PLL OUTPUT CLOCK OUTPUT ONE-SHOT PULSE OUTPUT SYNC OUTPUT POWER SUPPLY PIN SYNC OUTPUT GND PIN ANALOG GND PIN ANALOG POWER SUPPLY PIN ANALOG GND PIN VCO LOAD OUTPUT ANALOG POWER SUPPLY PIN ANALOG GND PIN FILTER CONNECT PIN ANALOG GND PIN FILTER CONNECT PIN DIGITAL GND PIN DIGITAL POWER SUPPLY PIN TEST PIN DIGITAL POWER SUPPLY PIN DIGITAL GND PIN TRIGGER INPUT M66238FP Outline 32P2W-A

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER PIN DESCRIPTIONS Name Reset input Chip select input Serial data input Serial clock input Clock input Clock output Trigger input Clock output PLL output One-shot pulse output Filter connect pin Filter connect pin VCO load output Test pin Test pin Test pin Test pin Digital power supply pin Digital GND pin Sync output power supply pin Sync output GND pin Analog power supply pin Analog GND pin Pin name RESET CS SIN SCLK XIN XOUT TR CKOB CKO/PLLO PULSE CPOUT CPIN RV TCKI TCKO UP DOWN DVCC DGND VCCO GNDO AVCC AGND I/O Input Input Input Input Input Output Input Output Output Output Output Input Output Input Output Output Output Function Initialize M66238 internal status. Transfer serial data when CS=“L”. Synchronize 32-bit serial data from MCU with SCK, and enter. Enter a sync clock for writing 32-bit serial data. Used by connecting crystal oscillator between XIN and XOUT. When using an external clock signal, connect the clock oscillator to XIN pin and open XOUT pin. Trigger input for clock sync. Output an inverted CKO signal. CKO outputs a clock synchronized with a trigger signal and PLLO outputs a PLL oscillator clock as it is. Output a one-shot pulse synchronized with a CKO signal. Connect a low pass filter to charge pump output. Low pass filter input pin. Connect a load resistor for VCO circuit operation between RV and GND. Shipping test pin. Connect to GND when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Digital power supply pin. Digital GND pin. Power supply pin for sync output. GND pin for sync output. Analog power supply pin. Analog GND pin. LIST OF REGISTER SETTING COMMANDS Setting Setting of CKO/PLLO dividing ratio, PLL synthesizer 15-bit generation dividing ratio and reference clock generation 12-bit dividing ratio. Setting of one-shot pulse polarity and width, setting of trigger edge, HALT of entire M66238, HALT of charge pump and VCO, phase comparator output UP/DOWN, CKO/PLLO switching. Dummy trigger generation command SERIAL DATA WRITE TIMING A0 A1 D0 D1 D2 D3 D4 D5 D6 D26 D27 D28 D29 CS SCLK SIN Address bit Data bit

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER REGISTER CONFIGURATION 1. Clock frequency setting command Reference clock generation 12-bit division ratio, PLL synthe- sizer 15-bit division ratio and CKO/PLLO division ratio are set at address (A1, A0) = (0, 0). Data bit D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 Default 12-bit reference clock dividing ratio is set. D11 and D0 correspond to MSB and LSB, respectively. K = ∑ (Dk × 2k) k = 0 K: Reference clock dividing ratio 15-bit PLL synthesizer dividing ratio is set. D26 and D12 correspond to MSB and LSB, respectively. N = ∑ (Dn × 2n–12) n = 12 N: PLL synthesizer dividing ratio Setting of CKO/PLLO dividing ratios Dividing ratio D29 D28 D27 PLLO/CKO oscillator frequency 25MHz ~ 50MHz 12.5MHz ~ 25MHz 6.25MHz ~ 12.5MHz 3.125MHz ~ 6.25MHz 1.563MHz ~ 3.125MHz 0.781MHz ~ 1.563MHz Remarks

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER When trigger occurs: spike of sync clock is not eliminated. When trigger occurs: spike of sync clock is eliminated (disabled when D1=1). Polarity of one-shot pulse: Negative pulse Polarity of one-shot pulse: Positive pulse CKO/PLLO pin: CKO output CKO/PLLO pin: PLLO output Entire M66238: Operating state Entire M66238: Halt state VCO: Operating state VCO: Halt state Charge pump: ON Charge pump: OFF Low pass filter: Operating state Low pass filter: Separated Normal use: Not output to outside Phase comparator UP/DOWN output enable Normal use VCO test circuit set Normal use Charge pump test circuit set Normal use 15-bit counter test clock enable Normal use Sync clock generator test clock enable Normal use Sync clock generator test input enable Normal use 12-bit counter test output enable Normal use 15-bit counter test output enable Normal use Sync clock generator trigger test output enable Normal use Sync clock generator test output enable In normal use: “0” set 2. Operating mode setting commands Address (A1, A0) = (1, 0) allows setting of one-shot pulse polarity and width, trigger edge, M66238 entire halt, charge pump and VCO halt, phase comparator UP/DOWN output, LPF cutoff, CKO/PLLO switching, VCO switching and charge pump switching. Data bit D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D29 Default Setting of one-shot pulse width Synchronizes with TR CKO is stopped when TR=“H”. Synchronizes with TR CKO is stopped when TR=“L”. Synchronizes with TR CKO is output when TR=“H”. Synchronizes with TR CKO is output when TR=“L”. Setting of trigger edge

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER 3. Dummy trigger generating command The internal status of sync clock generator becomes un- stable and a stable sync clock output (CKO) is not obtained after the power is turned on, after a reset is cleared or after an internal VCO oscillator frequency is set. To obtain a stable sync clock output, enter a trigger signal from the TR input af- ter VCO oscillator becomes stable, or enter a dummy trigger generating command from the MCU. The PLL synthesizer oscillator frequency after the cancellation of a reset depends on a default (See the register configuration). Set the command for address (A1, A0) = (1, 1). The command must be stored two times continuously when a dummy trigger is generated. For the first time, set the dummy trigger generating command with D0=1. For the second time, set the dummy trigger generating command with D0=0. The second setting becomes a sync edge and a clock begins to be output from CKO. After the first setting, CKO is in the halt state. In normal use: “0” Data bit D29 Default

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER OPERATING TIMING 1. Sync clock spike non-removal mode upon occur- rence of trigger 1-1 Setting of trigger edge when D1=0 One-shot pulse start timing:1st leading edge of CKO after TR fall One-shot pulse polarity: Negative pulse One-shot pulse width: 16 cycles of CKO CKO output dividing ratio: 1/2 division An example set for the condition of address (A1, A0)=(1, 0), shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise of CKO. 1-2 Setting of trigger edge when D1=1 One-shot pulse start timing:1st leading edge of CKO after TR rise (except the rise of a spike which occurs when CKO is stopped). One-shot pulse polarity: Negative pulse One-shot pulse width: 16 cycles of CKO CKO output dividing ratio: 1/2 division An example set for the condition of address (A1, A0)=(1, 0), shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise of CKO. Internal VCO oscillator clock tp=1/fvco tlp tp=1/fout TR tw(TR) tsp(CKO) tss(CKO) Δt Δt tss(PULSE) tw(PULSE) SPIKE CKO PULSE Internal VCO oscillator clock tp=1/fvco tlp tp=1/fout TR tw(TR) tsp(CKO) tss(CKO) Δt Δt tw(PULSE) SPIKE CKO PULSE

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER 2. Sync clock spike removal mode upon occurrence of trigger When address (A1, A0)=(1, 0) and data (D6, D5, D4, D3, D2, D1, D0)=(0, 1, 1, 0, 1, 0, 0), CKO with the first rise after oc- currence of a trigger is output and then CKO stops. However, this mode is not available when D1=1 in trigger edge setting. Set a wide TR so that TR sync edge is entered 200ns or more after CKO stops. 1) 200ns or more required 2) Note: tss (CKO, CKOB, PULSE) is defined by input clock width "L" + α . In addition, the value of α denotes IC internal delay, and the values of α and tss are definite unless tem- perature, Vcc, etc. are changed, and tss variations at that time is defined as Δt (sync accuracy: jitter). CKO/PLLO output frequency range The M66238 requires an internal VCO oscillator frequency of 25MHz to 50MHz. Settings of dividing ratio K of 12-bit divider and dividing ratio N of 15-bit counter are required in order to determine the in- ternal VCO oscillator frequency. The relation between the settings and the internal VCO oscillator frequency is shown below. Oscillator frequency 3) Note: Setting of fin/K≥100kHz is recommended in consid- eration of the frequency accuracy characteristics of PLL out- put. Therefore, set the division ratio K of the 12 bit divider and the division ratio N of the 15 bit counter to meet the following con- ditions: 25MHz ≤fvco≤50MHz In addition, for PLLO and CKO, setting the division ratios of the sync/division circuit (synchronous clock generating area) to 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow the frequencies of 0.78Hz - 50MHz to be accommodated. fin × Nf VCO = (MHz)K K= ∑ (Dk × 2k) k = 0 N= ∑ (Dn × 2n–12) n = 12 TR tw(TR) 1st tss(CKO) 200ns or more required tss(CKOB) tss(PULSE) tw(PULSE) Δt Δt Δt CKO CKOB PULSE

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Symbol Vcc Vi Vo P d Tstg Conditions When board is mounted Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 650 –65 ~ 150 Unit V V V mW RECOMMENDED OPERATING CONDITIONS (Ta=0 to 70°C) Symbol Vcc GND Vi Vo T opr Parameter Supply voltage Supply voltage Input voltage Output voltage Operating ambient temperature Unit V V V V Limits Min. 4.75 Typ. Max. 5.25 V CC VCC ELECTRICAL CHARACTERISTICS (Ta=0 to 70°C, Vcc=5V±5%, GND=0V) Conditions TR XIN GND=0V, IOH=–4mA GND=0V, IOL=4mA GND=0V, Vl=Vcc or GND GND=0V, CKO=50MHz Vl=Vcc or GND GND=0V, VI=V CC GND=0V, VI=0V Symbol VIH VIL VIH VIL VOH VOL I CC(S) ICC(a) IIH IIL CI Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Supply current (at time of standstill) Supply current (at time of operation) High-level input current Low-level input current Input capacitance Unit V V V V V V µA mA µA µA pF Limits Min. 0.85 V CC VCC –0.8 Typ. Max. 0.8

0.25 VCC

0.55 120 –10 Remarks: The direction of current flowing to the circuit is specified to be positive (no sign). Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Remarks: All voltages adopt the GND pin of the circuit as the base (0V) and absolute values are displayed for maximum and minimum values. Remarks: The direction of current flowing into a circuit is defined to be positive (no sign) and the direction of current flowing out is defined to be negative (– sign). Absolute values are displayed for maximum and minimum values. Measurement circuit (Note)

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER SWITCHING CHARACTERISTICS (Ta=0 to 70°C, Vcc=5V±5%, GND=0V) Symbol fvco fout Δt tss(CKO) tss(CKOB) tss(PULSE) tsp(CKO) tsp(CKOB) tw(PULSE) f oDUTY (CKO) foDUT (CKOB) Parameter VCO oscillation frequency Synchronous output frequency Synchronous accuracy (jitter) Synchronous clock output start Synchronous clock reversible output start One-shot pulse output start Synchronous clock output stop Synchronous clock reversible output stop One-shot pulse output width Synchronous clock output duty Synchronous clock reversible output duty Limits Unit MHz MHz ns ns ns ns ns ns ns Typ. Max. tlp+200 tlp+200 tlp+200 n • tp+10 Min. n • tp–10 TIMING REQUIREMENTS (Ta=0 to 70°C, Vcc=5V±5%, GND=0V) Symbol tw(CS) tsu(CS-SCK) th(SCK-CS) tw(SCK) tsu(SIN-SCK) th(SCK-SIN) fin fiDUTY tw(TR) tr tf Parameter CS width CS set up time CS hold time SCK width SIN set up time SIN hold time Clock input frequency Clock input duty Trigger input "H" pulse width Clock input rising time Clock input falling time Limits Unit µs ns ns ns ns ns MHz ns ns ns Typ. Max. Min. 200 Conditions Conditions CL=15pF (Notes)

  • tp=1/fout, tlp=tp 5 (100 – fvcoduty)/100
  • The n value of one-shot pulse output width is set in the register. MEASUREMENT CIRCUIT
  • Waveform for switching test Input pulse level XIN: 0 to Vcc, TR: 0 to 3V Input pulse rising time: 3 ns Input pulse falling time: 3 ns Zo: 50Ω Decision voltage Input voltage XIN: Vcc/2, Tr: 1.3V Output voltage All outputs: Vcc/2
  • Electrostatic capacitance: CL includes floating capacitance of connection and probe input capacitance. PG Tested element Input Output VCC ZO CL

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER INPUT TIMING (1) Register setting (2) Clock from trigger input and one-shot pulse output (3) Stop of clock from trigger input (4) Trigger input width (5) One-shot pulse width CS SCK SIN TR CKO CKOB PULSE 50% 50% 50% 50% 1.3V 50% 50%50% tsu(CS-SCK) th(SCK-CS) tw(CS) tw(SCK) tw(SCK) tsu(SIN-SCK) th(SCK-SIN) VCC VCC VOH VOL 3.0V VOL VOH VOL VCC tss TR TR CKO CKOB 50% 50%50% 1.3V 1.3V 1.3V tsp tw(TR) VOH PULSE tw(PULSE)

MITSUBISHI 〈DIGITAL ASSP 〉 M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER APPLICATION CIRCUIT EXAMPLE Digital power supply Analog power supply Analog GND Programmable Interface Programmable Interface 1M Ω Crystal oscillator 30pF 30pF Digital GND NC NC NC 7.5kΩ 2kΩ 1.2kΩ 0.015µF M66238FP