M66236FP

M66236FP MITSUBISHI | Alldatasheet

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Technical content

MITSUBISHI 〈DIGITAL ASSP 〉 M66236FP STANDARD CLOCK GENERATOR VCC TEST3 GND TR VCC CKO CKO CNTCK

DESCRIPTION

M66236 is produced using the silicon gate CMOS process. It is able to output clock input signal in sync with optional exter- nal trigger input signal. It features excellent synchronizing precision (jitter) over a wide frequency band range.

FEATURES

• 5V single power supply (5V ±5%)
• Frequency band: 12 ~ 25MHz
• Synchronizing precision (jitter): ±5ns
• Output types (1) Output of the same frequency as input clock, and its in- version (2) 1/2 divider clock output and its inversion (3) One-shot pulse output (4) Continuous clock output
• Noise in the positive direction to trigger input is removed by built-in noise killer circuit APPLICATION Clock phase control for horizontal synchronization PIN CONFIGURATION (TOP VIEW) BLOCK DIAGRAM MITSUBISHI 〈DIGITAL ASSP 〉 M66236FP STANDARD CLOCK GENERATOR Note: Keep test pins (TEST 1 to 3) open. Outline 16P2N-A M66236FP GND CKO SYNC CLOCK OUTPUT CKO SYNC CLOCK INVERTED OUTPUT CKO/2 1/2 DIVIDER SYNC CLOCK OUTPUT7 CKO/2 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT6 CNTCK CONTINUOUS CLOCK OUTPUT9 PULSE ONE-SHOT PULSE OUTPUT41 12 16 TEST2 TEST OUTPUT TEST3 TEST OUTPUT 1485 GNDGND TEST1TEST INPUT TRTRIGGER INPUT CLK INCLOCK INPUT VCC VCC SYNC CLOCK SELECTOR CIRCUIT DELAY CLOCK GENERATION CIRCUIT PHASE DETECTION CIRCUIT SYNC CLOCK GENERATION CIRCUIT TEST OUTPUT TRIGGER INPUT SYNC CLOCK OUTPUT SYNC CLOCK INVERTED OUTPUT CONTINUOUS CLOCK OUTPUT CLOCK INPUT TEST INPUT TEST OUTPUT ONE-SHOT PULSE OUTPUT 1/2 DIVIDER SYNC CLOCK INVERTED OUTPUT 1/2 DIVIDER SYNC CLOCK OUTPUT CLK IN TEST1 TEST2 PULSE GND CKO/2 CKO/2 GND

MITSUBISHI 〈DIGITAL ASSP 〉 M66236FP STANDARD CLOCK GENERATOR clock output from CKO is output. From 1/2 divider synchro- nous clock output (CKO/2), 1/2 divider signal of sync clock output from CKO is output. From 1/2 divider synchronous clock inverted output (CKO/2), inverted signal of that output from CKO/2 is output. From one-shot pulse output (PULSE), one-shot pulse which is almost equal to two cycles of clock input signal is output after trigger input signal falls. From continuous clock output (CNTCK), sync clock is output when trigger input signal is on “L” level; when trigger input signal is on “H” level, clock input signal, which is input to CLK IN, is output. All these outputs but continuous clock output are suspended when trigger input signal is on “H” level: Synchronous clock output, 1/2 divider synchronous clock output and one-shot pulse output stay on “L” level, and synchronous clock inverted output and 1/2 divider synchronous clock inverted output stay on “H” level. CLK IN 1/fIN tw(TR) tsp(CKO) tsp(CKO) tsp(CKO/2) tsp(CKO/2) tss(CKO) Δt Δt Δt Δt Δt tss(CKO) tss(CKO/2) tss(CKO/2) tss(PULSE) tw(PULSE) Δt tCH tss(CNTCK) tCL TR CKO PULSE CNTCK CKO/2 CKO CKO/2 VOH VOH VOL VOL VOH VOL VOH VOL VOH VOL VOH VOL VCC Note 1: tSS (CKO, CKO, CKO/2, CKO/2 and PULSE) equals the sum of input clock “L” width and α . Value α refers to internal delay in M66236. Under envi- ronment where temperature and VCC do not change, value α and tss are kept constant. Dispersion of tss under such conditions is defined as Δt [syn- chronizing precision (jitter)]. Note 2: Outputs (CKO, CKO, CKO/2, CKO/2 PULSE and CNTCK) are unknown until trigger input TR reaches “H” level for the first time after power-on. FUNCTION M66236 standard clock generator outputs clock input signal, which is input to CLK IN, synchronously with optional trigger signal, which is input to TR. Sync clock output timing is determined by trigger input signal fall edge. Time-lag between trigger input signal fall edge and sync clock output equals the sum of clock input signal “L” pulse width and M66236 internal delay. Variation in this lag (Δt) is ±5ns, ensuring excellent synchronizing accuracy. There are six types of outputs: synchronous clock output (CKO), synchronous clock inverted output (CKO), 1/2 divider synchronous clock output (CKO/2), 1/2 divider synchronous clock inverted output (CKO/2), one-shot pulse output (PULSE) and continuous clock output (CNTCK). From synchronous clock output (CKO), sync clock of the same frequency as clock input signal is output. From syn- chronous clock inverted output (CKO), inverted signal of sync

MITSUBISHI 〈DIGITAL ASSP 〉 M66236FP STANDARD CLOCK GENERATOR After Power-on Procedure After power-on, M66236 status is unknown till the trigger in- put being set to the “H” level. To get a accurate sync clock output, please keep a following procedure. Please hold the trigger input “H” level during more than tw(TR) after the input clock frequency being stable. Also, in case of changing the clock input frequency(f IN), please keep the same procedure. VCC TR CLK IN CKO tsp tw (TR) Input clock frequency is stable

MITSUBISHI 〈DIGITAL ASSP 〉 M66236FP STANDARD CLOCK GENERATOR Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Unit V V V mW Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 600 –65 ~ 150 Symbol VCC VI VO Pd Tstg ABSOLUTE MAXIMUM RATINGS Conditions When mounted Max 5.25 VCC VCC Unit V V V V Typ Min 4.75 Parameter Supply voltage Supply voltage Input voltage Output voltage Operating temperature Symbol V CC GND VI VO Topr Limits RECOMMENDED OPERATING CONDITIONS (Ta = 0 ~ 70°C unless otherwise noted) Unit V V V V V V µA mA µA µA pF Max 0.8 0.2 × VCC 0.55 LimitsTest conditions TR CLK IN GND = 0V, I OH = –4mA GND = 0V, IOL = 4mA GND = 0V, V I = VCC or GND GND = 0V , fIN = 25MHz, VI = VCC or GND GND = 0V, VI = VCC GND = 0V, VI = 0V Parameter “H” input voltage “L” input voltage “H” input voltage “L” input voltage “H” output voltage “L” output voltage Supply current (static) Supply current (active) “H” input current “L” input current Input capacitance Symbol V IH VIL VIH VIL VOH VOL ICC (s) ICC (a) IIH IIL C I ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ±5%, GND = 0V) TypMin 0.8 × VCC VCC – 0.8 LimitsTest conditionsParameter Clock input frequency Clock input duty Trigger input “H” pulse width Clock input rise time Clock input fall time Symbol f IN fDUTY tw(TR) tr tf TIMING REQUIREMENTS (Ta = 0 ~ 70°C, VCC = 5V ±5%, GND = 0V) Max Unit MHz ns ns ns TypMin 400

MITSUBISHI 〈DIGITAL ASSP 〉 M66236FP STANDARD CLOCK GENERATOR Max tLp + 50 tLp + 50 tLp + 50 tLp + 50 2tp + 10 Min 2tp – 10 LimitsTest conditions C L=15pF Parameter Synchronizing precision (jitter) Sync clock output start time Sync clock inverted output start time 1/2 divider sync clock output start time 1/2 divider sync clock inverted output start time One-shot pulse output start time Continuous clock output start time Sync clock output stop time Sync clock inverted output stop time 1/2 divider sync clock output stop time 1/2 divider sync clock inverted output stop time One-shot pulse output width Sync clock-Input clock switching time Input clock-Sync clock switching time Sync clock output duty Sync clock inverted output duty Symbol Δt t ss(CKO) tss(CKO) tss(CKO/2) tss(CKO/2) tss(PULSE) tss(CNTCK) tsp(CKO) tsp(CKO) tsp(CKO/2) tsp(CKO/2) tw(PULSE) tCH tCL fODUTY(CKO) fODUTY(CKO) SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ±5%, GND = 0V) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Typ TIMING DIAGRAM TEST CIRCUIT PG DUT VCC C L50Ω INPUT OUTPUT

• tp = 1/fIN, tLp = tp × (100 – fDUTY )/100
• Switching test waveform Input pulse level CLK IN: 0 to VCC TR: 0 to 3V Input pulse rise time: 3ns Input pulse fall time : 3ns Criterial voltage Input voltage CLK IN: VCC /2 TR: 1.3V Output voltage: VCC /2 for all outputs
• Capacitance: CL includes stray wiring capacitance and probe input capacitance. CKO/2 TR tss tCL CKO CKO/2 CKO PULSE CNTCK TR 1.3V 50% 50%50% 1.3V 1.3V tw(TR) 3.0V VOH VOH VOL VOL 3.0V CKO/2 TR tsp tCH CKO CNTCK PULSE 1.3V 50% 50% 50% tw(PULSE) 3.0V VOH VOL VOH VOL VOL 50% CKO/2 CKO VOH