M66230FP

M66230P MITSUBISHI | Alldatasheet

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MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)

DESCRIPTION

The M66230P/FP is an integrated circuit for asynchronous | PIN CONFIGURATION (TOP VIEW) serial data communications.it is used in combination with an 8-bit micro-processor and is produced using the silicon- gate CMOS technology. oo [i] Vec ; or-+[2] TD DAT OUTEUY FEATURES o2~ [3] [22] ~ RO Sarin © Baud rate generator S00kbps (max) oaranus (9 EE] =z Et] ets aaeatero-seno © 4-byte FIFO data butter for transmission and reception orm [5] fo] + ATS REQUEST IO © Error detection : CRC-CCITT, parity, overrun, os+[e| 8 [19]—- po , 8 poRT OUTPUT and framing D6 + z [18]—> Pt © Wakeup function sean contro. 197 +[2] UD inet NTERAUPT @ Transmisson / reception data format (number of bits) input RD [9 | [76]—GS cHpsevecr , aa SS NPUT Start bit 1 WRITE cone ‘Wr — [io] [15] — RESET reser INPUT Data bit 8 lcommanotoatac/6 — [ii] [ia] —x1 crock eur Wakeup bit 1 or nil CONTROL INPUT " eno [iz] —* X2_ CLOCK OUTPUT Parity bit 1 or nil Stop bit 1 or 2 © Access time ta (RD-D) : 100ns (max) Outline 24P4D © High output current 24P2W-A lon=—24mA, loL=24MA TxD, RTS, PO, P1 pins © Schmitt triggered input RxD,CTS,RESET pins ternal circuits and converts it into parallel format, and sends APPLICATION the parallel data via the data bus. Data communication contro! FUNCTION The M66230P/FP is a UART (Universal Asynchronous Re- ceiver/Transmitter) and is used in the peripheral circuit of a MPU. The M66230 receives parallel data, converts into serial format, and then transmits the serial data via the TxD pin. The device also receives data via the RxD pin from ex- BLOCK DIAGRAM Vee RE: ty Commard/ona Gs hd geay | wonnsome) | omaur be Read control input RD o| warre 8 — J * output — CONTROL | —— Wet cont input WR BA Sieur TRANSWIT CONTROL, ERROR DETECTION ni GTS Clear-to-send input Chip select input CS G Are Request-to- send ' 8 COMMAND ~>ap RTS ‘output ph —[__ resister od @-) DATA bd | Data bus D4 ERROR DETECTION (CRC) CIRCUIT | rorel Tl ——— 08 - RECEIVE DATA BUFFER e ref meetcovare "|_| gees 4 AO Recestion data input 6 49 PO o7 o~ } Port output i [7 SAMPLING CLOCK ® Pr Clock input xt & BAUD RATE 1) INT Interrupt output — _ ar }— TRANSFER prow Clock output x2 je J Loenemaron ~~ "L_encur FE SSS

9 MITSUBISHI

MITSUBISHI < DIGITAL ASSP > A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) OPERATION ‘The M66230 is interfaced to a system bus and provides all functions needed for data communication. adress bus

4 AO — Decoder

cB cs 0~07 RO wR RESET m66230P/FP Fig. 1 Interface between the M66230 and MPU system bus. When using the M6620, it Is necessary to program the ini- (RXEN) by a command instruction. tial setting, baud rate, character length, CRC, parity, in The MPU is able to read data when the interrupt output, accordance with the communication system. Once prog- __INT, goes low by packet end (PE) or buffer full (BF). rammed, the communcation system functions are executed — While receiving data, the M66230 checks for errors and continuously. provides status information. it checks for four types of When initial setting of M66230 is completed, data com- errors : CRC, parity, overrun and framing errors. When an munication becomes possible. When the transmitter is error occurs, M66230 continues operation. The error status transmit-enabled (TXEN) by a command instruction and is maintained until the error reset, (ER) is modified by a CTS is low-level, data transfer starts up. If these conditions command instruction. are not satisfied, data transmission is not executed. Recep- —_The access method of the M66230 is shown Table 1, tion is possible when the receiver is receive -enabled TABLE 1 Access method of the M66230. A [ot [HT eT bata bus-=Transmit data butt (FIFO) | Write tranemit data ‘| | H | eT [Toate buse-status regieter | Read tho status | [4 [wt] _t [Bata bus-=Command register Wiite the command — | x | HTH L_| Data bus : nigh impedance = .. STH | ata ue © high impedance = Sg MITSUBISHI we MISRS

MITSUBISHI < DIGITAL ASSP) A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) PIN DESCRIPTIONS Name vo Function Glock input Input | A crystal is externally connected to these pins for generating an internal clock. An external clock signal can be input to X1 instead of a crystal, Then X2 output opened. RESET | rove input | _tput_| thrones a mater reset ert coma shu bo lade ater fe reve cs Chip select A low level signal on the chip select input enables the M66230. The device can not be accessed when the Input signal is high-evel. c/D Command/ This signal distinguishes whether the information on the M66230 data bus is data, command or status in- Data control input formation. When the signal fs high-level, the data bus has command or status information. When the signat Is low-level, the data bus has data, DO~D7 | Data bus Input/output} This is an 6-bit bi-directional bus buffer. Command, status Information, and transfer data are transferred to/trom the MPU via this data bus butter. int Interrupt output ‘This Is used as an interrupt request to MPU. The interrupt request is generated when the receive FIFO is. full, the transmit FIFO is empty, or the block reception is complete. D2 bit of command 6 controls the ‘switching of low-level and high-level interrupt. | x0 | necepten dota np The serial data is sont to his pln Port output Output | This is an ordinary pott pin. This pin is controlled by the 00 bit of command 6. Port output Output | This pin has the same function as that of PO pin and provides information of packet transmission’s comple- tion, The switching of this function is controlled by command 6, D1 bit cTs Clear-to-send Input | When the TXEN bit (D0) of command 4 is set to 1 and the CTS input is low-level, serial data is sent from input the TxD pin, This is used as the clear-to-send signal ATS Request-to-send This is used as the request-to-send signal. This pin is controlled by the 03 bit of command 4 output

4 MITSUBISHI

MITSUBISHI <DIGITAL ASSP) M66230P/FP A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) DISCRIPTION OF FUNCTION @ Baud rate generator The 8-bit programmable divider (baud rate generator) Example ; Block length=2 generates the baud rate for transmit or receive. The divi- sion rate is (n+1) with a range of n=0~ 255. The baud [|- rrsfoar [| rate is calculated by the following formula : Coo hw pin MPU Tranemit data bute (FIFO) at putter (PS) baud rate= 1(X1)/(prescaler division rate (2 or 32) - baud rate gener- ator division rate (nt+1) - 16). The prescaler division rate is set by the DO bit of command _Block length=4 or more 1. The baud rate generator division rate is set by command — When the transmit data butter (FIFO) becomes empty and 2. Example as follows : INT is set low-active, the interrupt output INT becomes low. The MPU verifies the butter is empty by reading the D2 bit ‘9600bps=(9.8304MHz)/(2 + (31-+1) « 16) of the status 1 information. When this happens, the MPU should write the 4-bytes of where prescaler division rate is 2 and baud rate division data to the transmit data buffer (FIFO). The data in the rate is 31 transmit data buffer (FIFO) is sent to the transmit buffer, when CTS is low-level and TXEN is high-level. When the @ Block length counter number of bytes from the MPU becomes less than 4 at the The M66230 can handle multiple-bytes of data as one last stage of the block transmission, the same operation block (packet). should be made as the block length=1~3. Therefore, CRC of bytes is possible. The block tength When the buffer becomes empty, the data in the transmit counter is a 6-bit programmable counter. The block length data buffer (FIFO) is not be sent to the transmit buffer until is (m+1) bytes with the allowed values of m=0~63, MPU writes data of the fixed block length to the transmit data buffer (FIFO), The MPU cannot write data to the @ Transmit data buffer (FIFO) transmit data butter (FIFO) until the buffer becomes empty, The transmit data buffer (FIFO) consists of 4-bytes. The transmit data buffer (FIFO) functions according to the Example : Block length=6 block tength. [_]- = Block length=1~3 | — TD pin When the transmit data buffer (FIFO) becomes empty MPU Transit data butter (FIFO) mit buffer(P—sS) (buffer empty) and INT is set to low-active, the interrupt or ‘output INT is set to a low-level. The MPU verifies the buffer is empty when the D2 bit of the status 1 information is read. bara J] The MPU should write the block length data to the transmit data buffer (FIFO) at this moment. Transmit ata butter (FIFO) When a block of data is written to the transmit data buffer (FIFO),CTS is low-level and TXEN is high-level, the data in the transmit data buffer (FIFO) is sent to the transmit but- ter. It CTS is high-level while data is transmitted, all data is transmitted (including the data in the transmit data buffer (FIFO)), When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the transmit butter until MPU writes a new block of data to the transmit data buffer (FIFO). The MPU can not write new data to the transmit data buffer (FIFO) until the buffer becomes empty. MITSUBISHI oe iiee

MITSUBISHI <DIGITAL ASSP> M66230P/FP A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) @ Receive data buffer (FIFO) SUPPLEMENTARY DESCRIPTION The receive data buffer (FIFO) consists of 4-bytes. The re- FIFO ceive data buffer (FIFO) functions according to the block The major purpose is not to interrupt the MPU by each length character. The MPU is interrupted when : Transmit data buffer (FIFO) empty Block length=1~3 Receive data buffer (FIFO) full or packet end When the data of the block length is received and INT is The MPU interruption interval is as follows : set to low-level, the interrupt output INT becomes low- Approximately 90s (min) until the FIFO becomes full at level. The MPU acknowledges the packet end by setting —_ 500kbps. the DO bit of the status 1 information. Approximately 36.7ms (min) until the FIFO becomes full at In this case, the MPU should read all data from the receive 4. 2kbps. data buffer (FIFO). Read/write operation by the MPU should be made for all At the packet end, the data from the receive buffer cannot data in FIFO at once. be transmitted to the receive data buffer (FIFO) until the MPU reads all data in the receive data butter (FIFO). The MPU cannot read data in the receive data buffer unti! the packet end. Example : Block length=2 MPU Receive data buffer (FIFO) (Interrupt-packet end) Receive butter(P=-S) Block length=4 or more When 4-byte data enters the receive data buffer (FIFO) (buffer full) and INT is set to low-active, the interrupt out- put INT becomes low-level. The MPU acknowledges the buffer full status by setting the D1 bit of the status 1 in- formation. In this case, the MPU should read all data in the receive data buffer (FIFO). When the last data enters the receive data buffer (FIFO), the packet end becomes the same operation as for 1~3 byte block length. If the block length is a multiple of four, the DO and D1 bits of the status 1 information are set when the last data enters the receive data buffer (FIFO). At packet end or buffer full, the new data cannot be transfer- red from the receive buffer to the receive data buffer (FIFO). The MPU cannot read data in the receive data buf- fer (FIFO) until packet end or buffer full occurs. Example : Block length=6 L)- — MPU Receive data butler (FIFO) pecoive buller ws) FAP Pin (First interrupt-bufter full) or copa [J Receive data buffer (FIFO) (Second interrupt-packet end) ———— SSSSSFSSSSSSSSSSSSSSSSSSSSSSFssSSSSSSSSSSSSSSSSSSSSSSSSSSSese MITSUBISHI pales

MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) @ Wakeup be input as the second byte of command 4 by setting The wakeup mode of the M66230 can be set by setting the D2 bit of the command 4 to “1” and each address is in- D2 bit of command 4 to “1”. In wakeup mode, a 9th bit is put. In the wakeup mode, the Sth bit is automatically automatically added (the wakeup bit). added. Others remain the same. Only the Sth bit of the first byte is “1”, and the remainer @ Wakeup and data transfer (between master MPU blocks 9th bits are set to “0”. and local MPU1) The wakeup is used when one master MPU and multiple Data is transmitted from the master MPU to each local local MPU are connected by serial 1/0. MPU. Examples of wakeup are shown below. The first byte should hold the address of the local Initial setting MPU. (in this case local MPU1.) The initial setting should be made by the input of each Each local M66230 checks the data (address) against command. command 5 (each address) when the first byte @® Wakeup mode (address) is received. the M66230 which matches the The wakeup mode of the M66230 is activated by set- address starts to accept the following data (wakeup). ting D2 bit of the command 4 to "1". Command 5 can the M66230 which does not match the address, only accepts data, where the 9th bit is “1”. When GRC is enabled = of local MPUI Transter block Block check character as 8-bit The 9th 8-bit The 9th 8-bit The Sth 8-bit The 9th 8-bit The Sth data bit data bit data bit data bit data bit a ge sp ec 4 ‘ a 4 + Start bit Stop bit Start bit ‘Stop bit Start bit Stop bit Start bit Stop bit Start bit Stop bit When parity is enabled = of local MPUT Transfer block el Sie 8-bit The 9th Stop 8-bit The Sth Stop 8-bit The 9th Stop ‘ Note : The wakeup function i data bit bit data bit bit data it it automatically canceled when the ‘ ’ transfer block data has been read by the MPU. (The wakeup mode continues.) Start bit parity bit Start bit parity bit Start bit Parity bit LHI / M66230 Local 66230 Local / put MPut C } 7, , \\ LH] \\ ~ {_H_] Master mseza0. M6200 «Local Master mesza0 “06290 «Local MPU \\ Mpu2 MPU \\ mpu2 OW] LAI (M66230 Local M66230 Locat MPU3 MPU3 MITSUBISHI wales

MITSUBISHI < DIGITAL ASSP> A?7RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) @ Error detection SUPPLEMENTARY DESCRIPTION Parity error, Comparison between parity check and CRC When a parity error occurs, D5 bit of status 1 information is Parity check set. The data is send to the receive data buffer (FIFO). Parity check needs only one additional bit and is highly efficient. The formula is straightforward, and includes even Framing error parity and odd parity checks. In both cases, one bit is When a framing error occurs, DS bit of the status 1 informa- added. tion is set. The data is sent to the receive data buffer © CRC (FIFO). The CRC polynominal expression is CRC-CCITT X'®-+X'?-++ xeH1. Overrun error CRC deals with data characters in transmitted or received When data is received before all data in the receive data _blocks. (Start, stop and wakeup bits are excluded.) buffer (FIFO) has been read by MPU, D4 bit of the status 1 When the CRC is enabled, the transmit and receive data information is set as an overrun error. consists of block length (1~ 64 bytes) +2 bytes (block In this case, the new data in the receive buffer are lost. check characters). The following table shows the compari- sion between parity check and CRC, CRC error When an error occurs after receiving block check charac- ter, D6 bit of the status 1 information is set. The above error information is maintained until D4 bit of | — command 4 is set. | Burst error is not detected. Parity check | (60% of which can be de- tected.) | Burst error can be detected CRC (Burst error detection rate is more than 99.9%.) MITSUBISHI a TSee

MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) PROGRAMMING The command must be loaded first to the M66230 by the MPU before data communication. M66230 has 6 command registers. Data transfer is possible when commands have been loaded to these command registers after reset. The flowchart of the initial setting is shown in the following diagram. Flowchart of the M66230 initial setting. a SRR ELECTRIC

MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) COMMAND-INSTRUCTION FORMAT The commands are decoded by D7 and D6. Commandt Stop bit ae oribt Patity ch arly check FT Even parity 0. Odd parity Pant enable + treble 0 : Disable Sf eRe enable 0 | Disable Baud rate setting S999 Fo command 2 (Baud rate setting) Proscaler —— ‘oscaler +7732 division 0 ! 1/2 division [oo [oJ st ep [Pen crceN | BAUD Ps o7 Dé DS Ds x} D2 o1 DO Note 1 : Priority is given to parity enable, if parity enable and CRC enable are both “1" (03, D2=1). Attention : TxD output wave is Stop bit (D5) setup value +1 (always) Command 2 (Baud rate setting. The second byte when D1 bit of the command 1 is set to "1") = o oa oO ~ o ~ br D6 Ds D4 03 b2 ot 0 {n] 0 | ~ [ass] Command 8 (Block length setting) oT~ |] — - to o[~ 4 0 1 05 03 ba D1 DO {m[-o | ~ | 63 o7 D6 [2] a Command 4 etd Error reset 1 | Error flag clear Transmission carrier control —————

1 RTS="v

0: RTS="H" noe mee (7 ? Enable 0 : Disable

1 Enable

Transmit 2: Disable enable 1: Enable O: Disable 1 [30 i | ER RTS | WUMODE | AXEN TXEN o7 06 05 D4 03 02 Di Do MITSUBISHI ane ELECTRIC

MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) Command § (Address setting. The second byte when D2 bit of the commnd 4 bit is set to “1".) cae 05 oa | _b2 Py _ do | Command 6

1 FIFO disable |

LO: FIFO enable | TINT 0: iNT _

1 Pt=Packel transmission

| icmp 0: PI=Po | 1: PO="H" I 02 POR"E (as [ab be [os 0 07 06 a STATUS INFORMATION ‘Status 1 and 2 cannot address setting from external pin, Discrimination of status used to D7 bit. ‘Status 1 and 2 has read matually. (There are not continuity read of same status.) Status 1 ~ 1 indicates that a CRC error is found in the received data i 1 indicates theta pay error Is found Inte recelved data 1 indicates that framing errors found in the recelved an 1 indicates thatthe transmission data butter (FIFO) is empty [1 T indicates that the received | data butter (FIFO) is full | ~-—-[ indicates that the received data bier (FIFO) packet ond

0 CRGE PE OE “FE | TxBEMP | RXBFULL [ _AXBPE

7 06 05 Da cr) D2 Dt Do Status 2 — a LT inate tate tanariion™ charcors ara und in the bensmitee EE compo fo the taster ml 1 indicates the wakeup made a | t ‘TxEMP TxPE | _WUEN | WUMODE | *Transmitter=Transmit data buffer o7 D6 DS “pa BS b2 ‘DI bo (FIFO)-+Transmit butter MITSUBISHI ELECTRIC

MITSUBISHI <DIGITAL ASSP> A’RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) TRANSMISSION FORMAT Transmit format Parity enabled MPU-+M66230 Data character (8 bits) Assembled data format Start bit Wakeup bit Parity bit Stop bit (bit) Data character (6 bits) (nit or | bit) (itor bit) — | (1~2 bite) +1 Transmitter output ‘TxD mark Start bit Wakeup bit Parity bit Stop bit condition Data character (8 bits) (1 bit) (nil or 1 bit) (nil or ¥ bit) (1~2 bits)-+1 CRC enabled MPU-*M66230 Data character (8 bits) Alter assembly rt bit Keup bit top bil Star bl Data character (8 bits) Wakeup bi Stop bit (1 bit) (nil ort bit) (1~2 bits)-+1 Transmitter output TxD mark Start bit Wakeup bit Stop bit condition Data character (8 bits) (1 bit) (nil oF 1 bit) (1~2 bits) +1 Block \\ length ' m+1 ’ Start bit Wakeup bit Stop bit Data character (8 bit (1 bit) ta character (8 bits) (ail ort bit) (1~2 bits)+1 * Start bit Wakeup bit Stop bit Block check character (8 bits) ° oP (1 bit) (nil of F bit) (1~2 bits)+1 Start bit Wakeup bit Stop bit + Block check character (8 bits) ° ° (1 bit) (nit oF 1 bit) (12 bits)-+1 SSS MITSUBISHI ate MIB

MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) TRANSMISSION FORMAT Receive format Parity enabled Receiver input RxD mark. Start bit Cf (ete) Wakeup bit Parity bit Stop bit condition (bi) Data character(8 bits) (nit oF 1 bit) (nit ort bit) (1-2 bits) Receive format Start bit Wakeup bit Parity bit Stop bit M66230--MCU CRC enabled Receiver input RxD mark Start bit Wakeup bit Stop bit condition (1 bit) Dota character (8 bits) (oil oF 1 bit) (1~2 bits) Block ' length ' m+! ' Start bit Wakeup bit Stop bit (1b) Data character (8 bits) (nil or 1 bit) (1~2 bits) Start bit Wakeup bit ‘Stop bit + (1 bit) Block check character (8 bits) (nit ort bit) (1~2 bits) + Stan bit Block check character (8 bits) Wekeup bit Stop bit (1 bit) (nil oF 1 bit) (1~2 bits) Receive format ‘Start bit Wakeup bit ‘Stop bit (1 bi) Data character (8 bits) {nil ort bit) (1~2 bits) M66230--MCU eee

MITSUBISHI <DIGITAL ASSP > A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) ABSOLUTE MAXIMUM RATINGS (1a=—40~+85°, unless otherwise noted) =0.5~+7.0 v input vatage - Value using the GND pin as reference =0.5~Veo+0.5 Output voltage __ =0.5~Voo+0.5 [ Pg | Power dissipation ‘Actually mounted 500 =6~+150 RECOMMENDED OPERATING CONDITIONS (ta=—40~+85¢) ee ee | “eno | Ground a Operating temperature a ELECTRICAL CHARACTERISTICS (12=—40~+85°, Voc=5V+10%, GND=OV, unless otherwise noted) — in [typ | Max | High-level input voltage oe [20 rv Low-level put vatage a] FFF. 6S. c0-7 [os |v High-level input voltage: at Nexo | |v +t | Weexa.a) v | Positive threshold votage 24] Vv Vr— Negative threshold voltage _______| Px, CTS, RESET 0.6 v Vir | Hysteresis with oz{ | | v_| lou —8mA_INTDO~D7 a You __| Mamlevel owe votage [owmeima To. ATE.popr ee YY lag=8mA_NT.DO~D7 [| os | Vou _| owlevel ouput voltage lou=2émA_ TxD, ATS, PO, PI [Toss] [tm __| High-level input current WeVeo 1.0] ua Low-level Input current V=GND 1.0] uA [lozn | Offstate high-level output current Vo=Veo [| 50! ya | [tec | Staie suppiycurent Wine @ND YY ||| cy Input capacitance _10_ Cvo \\/O capacitance 20 p MITSUBISHI ate MISES

MITSUBISHI <DIGITAL ASSP> M66230P/FP A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) TIMING REQUIREMENTS (ta-—40~+85C, Voo=5V+10%, Vss=0V, unless otherwise noted) [Min [tye | Max_| fens] | | me | | twatcxr __| Clock high-level pulse width | (Except Wakeup, CRC mode) [30 [ns turn) ‘Clock low-level pulse width 30 (Wekeup, CRC mode) | se {fy ns | (3ef | Cs a ‘Address setup time before read (68, G/B) a | ‘Address hold time after reed (CS, C/D) a ead pulse with [iol | | a fof TT ns Cc a Data hold time after write rs trectRese) __| Recoverry time between wiite J00 SWITCHING CHARACTERISTICS (ta=—40~+285°C, Voc=5V+10%, Vss=0V, unless otherwise noted) (oe ee == eae Min Typ. Max [| 52] 00 [ns | Data output disable time after read [ [733 | 5 | ns | ae tuna) TNT output propagation time after read data 62 | 170 tenu(h—int) | INT output propagation time after read data 6 | 170 | TNT output propagation time after wrte data TNT output propagation time after write data | |4 | a [| 35 [100 _| In output propagation ime ater wit command (command 6) 28 tena) TNT output propagation time attr write command (command 6) Lt “30 | 100 teuncw—Po) PO output propagation time after write command [___{ 25 70 tenu(@—ro) ___| PO output propagation time after write command [| 2 | 70 | ns ‘| a A | [| 8 70 | ns | MITSUBISHI ees

MITSUBISHI <DIGITAL ASSP > A?’RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) TEST CIRCUIT Input Veo Output Vee fo) fs) Riko [Parameter [swi [swe] be pur fg sw tez | Closed | Open _teuz | Open | Closed Q sw2 tez.__| Closed | Open ia tezn Open | Closed Son a Sa tka (1) The pulse generator (PG) has the Oanpd following characteristics (10% ~ 90%) | t=3ns, tj=3ns cd (2) The ‘capacitance CG. = 150pF in- cludes stray wiring capacitance and the probe input capacitance. TIMING DIAGRAM Input/output waveform at read data and read status ROD 1.3 1.3 ov teauiF-o0 tr2R—b0) Vou Do~o7 1.3v 10% Vou 90% DO~D7 1.3V Vou Clock Timing teow btwn tow 30% 30% Vee x 50% 50% 50% ov MITSUBISHI a eRs

MITSUBISHI <DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) Write control cycle (MPU--M66230) tsuta—W) thi») 6 wy \\ | > wy [| : ov tw ov tsuoo-#) thioay - wy pore? i” . ov teu, teHu(W—iNT) —— Vou “ | > a Vou tein, teHL(W—ATE.P0.P1) Von RTS, Po, Pt 1.3v Vou Read control cycle (M66230-*MPU) foun thin su nha) av ov c/o 1.3V Koon | 13v Isuta—A) Lo thie) ov RD 1.3 1.3v | ov trzu.tezwiA~oa) | truz, tenztR—o0 Vou por Vou MITSUBISHI ate MISES

MITSUBISHI < DIGITAL ASSP> A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) Write data cycle (MPU-+M66230) teua—w) tniw—a) “ wy \\ | > m ov teua-W) thaw) — av cD 1.3V 1.3 ov Bi av wa 1.3V 1.3v ov thew-o0 aN av over ay, a ov oun, toni —in) Vow int 1.3V Vou Read data cycle (M66230--MPU) tour tha ° m \\ | wy ov teurAd tna) 3Vv °° aa \\ | i ia ov wim - 3v RD 1.3V 1.3v ov tezt. teewtR—oa) | tz: teuzti-no) | vow aad teu bene cR=inT) Vou _ Vow int 1.3V Vou MITSUBISHI oe MRS

MITSUBISHI <DIGITAL ASSP> M66230P/FP A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) Transmitter control and flag timing (block length=1) cD WR 4 TxEN) 6 DATA2 * Le TxBEMP , if 7 f (Status ) N fr

10 QUOT TT WOH

Transmitter control and flag timing (block length=3) cD WR f TXEN | (OATAIDATA2 DATA3, (DATA4DATAS DATAG a ri wr 4 | | , T.BEMP XN J i. \\ fA (Status) - / 10 iT ut VOT LI WJ DATA! DATA2 DATA3 DATA4 DATA5 DATA6 Transmitter contro! and flag timing (block length =5) co TXEN\\ DATA DATA3 Gatad — (DATAS_DATAS DATAIO crs \\,_DATA2 DATAS \\ N DATA7 DATAQ| ST \\ 4 1.8EMP 7 PAUP A A ( Status ) % 7 a % S cy, wo YET ~ IY J ULI~ wy VWI DATAI DATA4 DATA5: DATA6 DATA9 DATAIO

MITSUBISHI <DIGITAL ASSP> M66230P/FP A?RT(ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) Receiver control and flag timing (block length=1) a a A wa RXEN VU * int f if rere f Lf LIA ( Status ) ° ° | (Status) L y 4 7+ mo CTT LO LO Loo) DATA DATA2 DATA3 DATA4 Receiver control and flag timing (block length=3) RD __ DATA IDATA 2{DATA3 DATA4DATAS| DATA6 wr RXEN eR RXBPE 7 (Status) fi % Mi ® OE 71 ( Status) t " DATA! DATA2 DATA3 DATA4 DATAS DATA6 DATA7 Receiver contro! and flag timing (block length=5) RO MAA. us ON DATAD DATAS Re 7) 7a i ¢ PRBFULL, eA) eS (Status ) ”¢ 7 (. Status ) 4 m0 ~LLJ [ | CT ~ Io Uo DATA! DATA4 DATAS DATA6 DATAS DATAIO MITSUBISHI eines