M66222SP MITSUBISHI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX

DESCRIPTION

The M66222 is a mail box that incorporates two complete CMOS shared memory cells of 128 × 8-bit configuration using high- performance silicon gate CMOS process technology, and are equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations individually. This product exclusively performs a write operation from A port and a read operation from B port for one memory, and a read operation from A port and a write operation from B port for the other memory.

FEATURES

  • Memory configuration of 128 × 8 bits × 2 memory areas
  • High-speed access, address access time 40ns (typ.)
  • Complete asynchronous accessibility from ports A and B
  • Fixed read/write access ports for memory
  • Completely static operation
  • Low power dissipation CMOS design
  • 5V single power supply
  • TTL direct-coupled I/O
  • 3-state output for I/O pins APPLICATION Inter-MCU data transfer memory, communication buffer memory MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX BLOCK DIAGRAM PIN CONFIGURATION (Top view) READ/ WRITE CONTROL CIRCUIT MEMORY AREA(1) 128-WORD × 8-BIT CONFIGURATION 0-127 ADDRESSES SENSE AMPLIFIER OUTPUT BUFFER READ/ WRITE CONTROL CIRCUIT ROW/COLUMN DECODER ROW/COLUMN DECODER MEMORY AREA(2) 128-WORD × 8-BIT CONFIGURATION 128-255 ADDRESSES OUTPUT BUFFER SENSE AMPLIFIER INPUT DATA CONTROL CIRCUIT INPUT DATA CONTROL CIRCUIT Write Read A0A~A 6AA 0B~A 6B VCC GND CSA WEA OEA A7A A0A A1A A2A A3A A4A A5A A6A I/O0A I/O1A I/O2A I/O3A I/O4A I/O5A I/O6A I/O7A CSB WEB OEB A7B A0B A1B A2B A3B A4B A5B A6B I/O0B I/O1B I/O2B I/O3B I/O4B I/O5B I/O6B I/O7B CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT A PORT ADDRESS INPUT A PORT DATA I/O CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT B PORT ADDRESS INPUT B PORT DATA I/O Read Write 7 7 CSA → WEA NC OEA I/O7A GND I/O6A I/O5A I/O4A I/O3A I/O2A I/O1A I/O0A A7A A6A A5A A4A A3A A2A A1A A0A CSB V CC NC WEB A OEB A1B A2B A3B A4B A5B I/O7B A6B A7B I/O6B I/O5B I/O4B I/O3B I/O2B I/O1B I/O0B CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT A PORT ADDRESS INPUT A PORT DATA I/O CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT B PORT ADDRESS INPUT B PORT DATA I/O Outline NC: No Connection 42P4B 42P2R-A M66222SP/FP

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX FUNCTION The M66222 is a mail box most suitable for inter-MCU data communication interface. Provision of two pairs of addresses and data buses in its shared memory cell of 128 × 8-bit configuration allows independent and asynchronous read/write operations from/to two access ports of A and B individually. Two memory areas of 128 × 8-bit configuration are incorporated in the chip. Memory area (1) is used only to perform a write operation from A port and a read operation from B port, and memory area (2) only to perform a read operation from A port and a write operation from B port. In this case, address A 7A should be set to “L” when writing data from A port in memory area (1), and address A7B should be set to “L” when reading data from B port in memory area (1). Also, address A 7B should be set to “H” when writing data from B port in memory area (2), and address A7A should be set to “H” when reading data from A port in memory area (2). Therefore, an attempt to set addresses A7A and A7B from each port in a mode other than the above setting invalidates any read/write operation from the corresponding port (See Table 1 and Fig 1). As a basic write operation to memory, one of addresses A 0 to A7 is specified. The CS signal is set to “L” to place one of I/O pins in the input mode. Also, the WE signal is set to “L”. Data at the I/O pin is written into memory. As a read operation, the WE signal is set to “H”. Both CS signal and OE signal are set to “L” to place one of I/O pins in the output mode. One of addresses A 0 to A7 is specified. Data at the specified address is thus output to the I/O pin. When the CS signal is set to “H”, the chip enters a non-select state which inhibits a read and write operation. At this time, the output is placed in the floating state (high impedance state), thus allowing OR tie with another chip. When the OE signal is set to “H”, the output enters the floating state. In the I/O bus mode, setting the OE signal to "H" at a write time avoids contention of I/O bus data. When the CS signal is set to Vcc, the output enters the full stand-by state to minimize supply current (See Tables 2 and 3). Access portOperation A port A7A = “L” A7A = “H” B port A7B = “H” A7B = “L” Write Read Note 1: No input data is written into any port having address A7 set under any condition other than Table 1. Undefined data is read to an output pin during a read operation. Fig 1 Access from Ports Table 2 A Port Function Table CSA L L L H WEA L H H OEA L H A7A L H L H Mode Write Invalid Invalid Read Non-select I/O pin D IN D IN D OUT D OUT High impedance High impedance ICC Operation Operation Operation Operation Operation Stand-by Note 2:× indicates “L” or “H”. (Irrelevant) “H” = High level, “L” = Low level Table 3 B Port Function Table CSB L L L H WEB L H H OEB L H A7B L H L H Mode Invalid Write Read Invalid Non-select I/O pin D IN D IN D OUT D OUT High impedance High impedance ICC Operation Operation Operation Operation Operation Stand-by A7B = “L” ReadWrite A7A = “L” A7B = “H” WriteRead A7A = “H” A port B port Memory area (1) of 128-word × 8-bit configuration 0-127 addresses Memory area (2) of 128-word × 8-bit configuration 128-255 addresses Table 1 Port Operations and Address A7 Setting Conditions

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX FUNCTIONAL DESCRIPTION The M66222 with independent and asynchronous accessibility from two ports has the following four basic operations depending on an address and mode set from both ports: In this case, the same address is not selected when the same read/ write instruction is being executed at both ports as given in (1) and (4). There is no concern about uncertainty of read/write data at an active address. If one port operates in the write mode and the other does in the read mode as given in (2) and (3), however, the same address may be selected. In this case, data of the port operating in the write mode is written. If the port in the read mode comes first, read data of the first-in port becomes uncertain until write data of the last-in port is determined (If the same address is selected, data of the port operating in the write mode is written into memory. Therefore, data of the port in the read mode may change from previously written data to newly written ones during the same cycle) (See Fig 2). Ex.) A port - address setting first-in read operation A port address B port address WEB B port I/O (DIN) A port I/O (DOUT ) : When selecting the same address Data B Data BData A (Data read to A port) B port - address setting last-in write operation Fig 2 Example of Read Data Transition at Selection of Same Address (Data written from B port)

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted) Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature range Conditions When defining GND pin as a reference. Ta = 25°C Ratings –0.3 ~ +7.0 –0.3 ~ V CC + 0.3 0 ~ VCC 700 –65 ~ 150 Unit V V V mW RECOMMENDED OPERATING CONDITIONS Symbol VCC GND VI Topr Parameter Supply voltage Ground Input voltage Operating temperature range Unit V V V Limits Min. 4.5 Typ. 5.0 Max. 5.5 V CC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc=5V±10%, unless otherwise noted) Test conditions IOH = –2mA IOL = 4mA VI = VCC VI = GND CS = VIH or OE = VIH VO = VCC CS = VIH or OE = VIH VO = GND CS < 0.2V, Another input VIN > VCC – 0.2V or VIN < 0.2V, Output pin open CSA, CSB = VIH CSA or CSB = VIH IOUT = 0mA (Active port output pin open) CSA, CSB > VCC – 0.2V Another input VIN > VCC – 0.2V or VIN < 0.2V CSA or CSB > VCC – 0.2V Another input VIN > VCC – 0.2V or VIN < 0.2V, IOUT = 0mA (Active port output pin open) Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC ISB1 ISB2 ISB3 ISB4 C I C O Parameter “H” input voltage “L” input voltage “H” output voltage “L” output voltage “H” input current “L” input current Off state “H” output current Off state “L” output current Static current dissipation (active) Two-port stand-by One-port stand-by Two-port full stand-by One-port full stand-by Input capacitance Output capacitance in off state Stand-by current Unit V V V V µA µA µA µA mA mA mA mA mA pF pF Limits Min. 2.2 –0.3 2.4 Typ. Max. V CC +0.3 0.8 0.5 10.0 –10.0 10.0 –10.0 0.1 Notes 3: The direction in which current flows into the IC is defined as positive (no sign). 4: The above typical values are standard values for VCC =5V and Ta=25°C.

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V±10%, unless otherwise noted) Read cycle Symbol tCR ta(A) ta(CS) ta(OE) tdis(CS) tdis(OE) ten(CS) ten(OE) tv(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after CS (Note 5) Output disable time after OE (Note 5) Output enable time after CS (Note 5) Output enable time after OE (Note 5) Data effective time after Address Limits Unit ns ns ns ns ns ns ns ns ns Typ. Max. Min. TIMING REQUIREMENTS (Ta = 0 ~ 70°C, VCC = 5V±10%, unless otherwise noted) Write cycle Parameter Write cycle time Write pulse width Address setup time (for WE) Address setup time (for CS) Address setup time for rise of WE Chip select setup time Data setup time Data hold time Write recovery time Output disable time after WE (Note 5) Output disable time after OE (Note 5) Output enable time after WE (Note 5) Output enable time after OE (Note 5) Limits Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Typ. Max. Min. Note 5: The time required for the output to change from a steady state to ±500mV under the load conditions shown in Figure 4. This parameter is guaranteed but is not tested at shipment. Symbol tCW tw(WE) tsu(A)1 tsu(A)2 tsu(A-WEH) tsu(CS) tsu(D) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE)

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX TIMING DIAGRAM Read Cycle (WE = VIH) Read cycle No. 1 (Address control) (CS = OE = VIL) A0~A7 I/O0~I/O7 (DOUT ) tCR ta(A) tv(A) tv(A) Previous cycle data Data output determined Read cycle No. 2 (CS control) A0~A 7 I/O0~I/O7 (DOUT ) tCR ta(A) ta(CS) tdis(CS) CS OE ten(CS) ta(OE) tdis(OE) ten(OE) High impedance Data output determined

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX Write Cycle Write cycle No.1 (WE control) See Notes 6, 7 and 8. A0~A7 I/O0~I/O7 (DIN) CS OE WE I/O0~I/O7 (DOUT ) tCW tsu(CS) tsu(A-WEH) tsu(A)1 tw(WE) trec(WE) tsu(D) th(D) tdis(WE) tdis(OE) ten(WE) ten(OE) Data input determined Write cycle No.2 (CS control) See Notes 7 and 8. A0~A7 I/O0~I/O7 (DIN) CS WE tCW tsu(A)2 tsu(CS) trec(WE) tsu(D) th(D) Data input determined Notes 6: The WE of the port must be set to “H” when an address input changes. 7: A write operation is performed during the overlap period when both CS and WE are “L”. 8: Do not apply any negative-phase signal from outside when an I/O pin is in output state. 9: The shaded part means a state in which a signal can be “H” or “L”.

MITSUBISHI 〈DIGITAL ASSP 〉 M66222SP/FP 128 × 8-BIT × 2 MAIL-BOX SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT Input pulse level : V IH = 3.0V, VIL = 0V Input pulse rise/fall time : tr/tf = 5ns Input timing reference voltage : 1.5V Output timing decision voltage : 1.5V Output load : Figure 3 ~ 4 (The capacitance includes stray wiring capacitance and the probe input capacitance.) Fig 4. Output Load (to ten, tdis) + 5V 1250Ω 100pF775Ω I/O 1250Ω 5pF775Ω I/O Fig 3. Output Load