M66221SP MITSUBISHI | Alldatasheet
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MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX
DESCRIPTION
The M66221 is a mail box that incorporates a complete CMOS shared memory cell of 256 × 9-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
FEATURES
- Memory configuration of 256 × 9 bits
- High-speed access, address access time 40ns (typ.)
- Complete asynchronous accessibility from ports A and B
- Completely static operation
- Built-in port arbitration function
- Low power dissipation CMOS design
- 5V single power supply
- Not Ready output pin is provided (open drain output)
- TTL direct-coupled I/O
- 3-state output for I/O pins. APPLICATION Inter-MPU data transfer memory, buffer memory for image processing system. FUNCTION The M66221 is a mail box most suitable for inter-MPU data transfer which is used in a multiport mode. Provision of two pairs of addresses and data buses in its shared memory cell of 256 × 9 bit configuration allows independent and asynchronous read/write operations from/to two access ports of A and B individually. This allows access to shared memory as simple RAM when viewing from one MPU. The concurrent accessibility to shared memory from two MPUs provides remarkable improvement of a multiport mode processor system in throughput. The arbitration function incorporated in the chip decides the first-in port to assign a higher priority to the access from one MPU, even if two MPUs contend for selection of the same address in shared memory from ports A and B. A Not Ready signal “L” is output to the last-in port and invalidates any access from the other MPU. As a write operation to memory, one of addresses A 0 to A7 is specified. The CS signal is set to “L” to place one of I/O pins in the input mode. Also, the WE signal is set to “L”. Data at the I/O pin is thus written into memory. As a read operation, the WE signal is set to “H”. Both CS signal and OE signal are set to “L” to place one of I/O pins in the output mode. One of addresses A 0 to A7 is specified. Data at the specified address is output to the I/O pin. When the CS signal is set to “H”, the chip enters a non-select state which inhibits a read and write operation. At this time, the output is placed in the floating state (high impedance state), thus allowing OR tie with another chip. When the OE signal is set to “H”, the output enters the floating state. In the I/O bus mode, setting the OE signal to “H” at a write time avoids contention of I/O bus data. When the CS signal is set to Vcc, the output enters the full stand-by state to minimize supply current (See Tables 1 and 2). MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX PIN CONFIGURATION (Top view) CSA → WEA Not Ready A OEA I/O7A GND I/O6A I/O5A I/O4A I/O3A I/O2A I/O1A I/O0A A7A A6A A5A A4A A3A A2A A1A A0A CSB VCC Not Ready B WEB A0B OEB A1B A2B A3B A4B A5B I/O7B A6B A7B I/O6B I/O5B I/O4B I/O3B I/O2B I/O1B CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT A PORT ADDRESS INPUT A PORT DATA I/O CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT B PORT ADDRESS INPUT B PORT DATA I/O Outline 48P4B M66221SP NOT READY OUTPUT NOT READY OUTPUT 23 26 NC NC ↔I/O NC NC ↔ I/O8B ↔ I/O0B ↔I/O7A I/O6A I/O5A I/O4A I/O3A I/O2A I/O1A I/O0A A7A A6A A5A A4A A3A A2A A1A A0A A0B A1B A2B A3B A4B A5B I/O7B A6B A7B I/O6B I/O5B I/O4B I/O3B I/O2B I/O1B Outline 52P2G-A M66221FP ← 3 23 30 NC NC ↔I/O8A NC NC ↔ I/O8B ↔ I/O0B2726 25 28 GND NC NC NC NC NC: No Connection CSA WEA Not Ready A OEA CSB VCC Not Ready B WEB OEB CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT A PORT ADDRESS INPUT A PORT DATA I/O CHIP SELECT INPUT WRITE ENABLE INPUT OUTPUT ENABLE INPUT B PORT ADDRESS INPUT B PORT DATA I/O NOT READY OUTPUT NOT READY OUTPUT
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX Table 1 Mode Settings of Ports (A0A ~ A7A ≠ A0B ~ A7B) A port input B port input Flag CSA H L L WEA L H OEA L CSB H L L WEB L H OEB L Not Ready A H H H H H H Not Ready B H H H H H H Operation A port is set to the non-select mode. B port is set to the non-select mode. A port is set to the write mode for memory. A port is set to the read mode for memory. B port is set to the write mode for memory. B port is set to the read mode for memory. Table 2 Basic Functions of Ports BLOCK DIAGRAM CS H L L L WE L H H OE L H Mode Non-select Write Read I/O pin High impedance D IN D OUT High impedance ICC Stand-by Operation Operation Operation Note 1:× indicates “L” or “H”. (Irrelevant) “H” = High level, “L” = Low level Not Ready A WEA CSA OEA I/O0A I/O1A I/O2A I/O3A I/O4A I/O5A I/O6A I/O7A I/O8A A0A A1A A2A A3A A4A A5A A6A A7A WRITE ENABLE INPUT CHIP SELECT INPUT OUTPUT ENABLE INPUT A PORT DATA I/O A PORT ADDRESS INPUT CONTROL CIRCUIT I/O BUFFER ROW/COLUMN DECODER ARBITRATION CIRCUIT MEMORY ARRAY OF 256-WORD ×9-BIT CONFIGURATION CONTROL CIRCUIT I/O BUFFER ROW/COLUMN DECODER Not Ready B WEB CSB OEB I/O0B I/O1B I/O2B I/O3B I/O4B I/O5B I/O6B I/O7B I/O8B A0B A1B A2B A3B A4B A5B A6B A7B WRITE ENABLE INPUT CHIP SELECT INPUT OUTPUT ENABLE INPUT B PORT DATA I/O B PORT ADDRESS INPUT V CC GND OEA WEA WEB OEB A0A A7A ~ A0B A7B ~ NOT READY OUTPUT NOT READY OUTPUT
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX This comes into question. When both ports are operating in the write mode as given in (4), reverse data is written into each port and the contents of memory may become uncertain. Consequently, no result will be guaranteed. The M66221 incorporated an arbitration function circuit to solve such problems when contentionally selecting an address from both ports. The arbitration function decides which of A and B ports determines an address first, and unconditionally assigns access priority to the first-in port (At this time, the Not Ready signal holds “H”). As for the last-in port operation, the function inhibits any write to that port from MPU at the same time when “L” is output to the Not Ready output pin at the port regardless of a read or write operation during the period of address matching of both ports. If the address of the first-in port changes after that and both ports do not have the same address, the Not Ready output is reset to “H” and the access in the stopped state is accepted from the last-in port. If the same address is selected by an address input from both ports simultaneously, a decision by the arbitration function on the chip also affords access only from one port, and outputs “L” to the Not Ready output for the other port invalidate any access from MPU. Tables 3 and 4 give the relationship between the port arbitration function and port access. FUNCTIONAL DESCRIPTION Arbitration Function The M66221 has asynchronous accessibility from two independent ports to shared memory, thus remarkably improving the throughput of the entire processor system used in the multiport mode. On the other hand, this accessibility causes a problem of contending for selecting the same address in shared memory during the addressing from both ports. If the same address is contentionally selected, the following four basic operations are possible depending on an access mode set from both ports: In this case, when both ports are operating in the read mode as given in (1), correct data is read to both ports and the contents of memory are not destroyed. There is no special problem. If the other port is in the read mode while one port is operating in the write mode as given in (2) or (3), however, data is written correctly but the data read from the other port in the read mode may change during the same cycle.
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX Arbitration Function and Port Access Contention No. 1 (Address control) Table 3 gives the port access states and the Not Ready signal output states if the same address is selected in shared memory by an address Table 3 Contention Processing by Address Input Address setting when selecting same address First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port Simultaneous A and B ports A port Mode setting Read Read Read Read Write Write Write Write Access Not Ready A H L H L H L H L Arbitration Resolved B port Mode setting Read Read Write Write Read Read Write Write Access Not Ready B L H L H L H L H Arbitration Resolved Contention No. 2 (CS control) Table 4 gives the port access states and the Not Ready signal output states when setting the CS inputs from A and B ports valid, and input set from A and B ports with CSA = CSB = “L”. selecting the same address in shared memory with A 0A to A7A=A 0B to A7B. CSA = CSB = “L” Table 4 Contention Processing by CS Input CS input set when selecting same address First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port Simultaneous A and B ports A port Mode setting Read Read Read Read Write Write Write Write Access Not Ready A H L H L H L H L Arbitration Resolved B port Mode setting Read Read Write Write Read Read Write Write Access Not Ready B L H L H L H L H Arbitration Resolved A 0A ~ A7A = A0B ~ A7B Note 2: “H” = High level, “L” = Low level
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted) Symbol VCC VI VO Pd Tstg Conditions When defining GND pin as a reference. Ta = 25°C Ratings –0.3 ~ +7.0 –0.3 ~ VCC + 0.3 0 ~ VCC 800 –65 ~ 150 Unit V V V mW RECOMMENDED OPERATING CONDITIONS Symbol VCC GND VI Topr Parameter Supply voltage Ground Input voltage Operating temperature range Unit V V V Limits Min. 4.5 Typ. 5.0 Max. 5.5 V CC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc=5V±10%, unless otherwise noted) Test conditions IOH = –2mA IOL = 4mA IOL = 8mA VI = VCC VI = GND CS = VIH or OE = VIH VO = VCC CS = VIH or OE = VIH VO = GND CS < 0.2V, Another input VIN > VCC – 0.2V or VIN < 0.2V, Output pin open CSA, CSB = VIH CSA or CSB = VIH IOUT = 0mA (Active port output pin open) CSA, CSB > VCC – 0.2V Another input VIN > VCC – 0.2V or VIN < 0.2V CSA or CSB > VCC – 0.2V Another input VIN > VCC – 0.2V or VIN < 0.2V, IOUT = 0mA (Active port output pin open) Symbol VIH VIL VOH VOL VOL IIH IIL IOZH IOZL ICC ISB1 ISB2 ISB3 ISB4 C I C O Parameter “H” input voltage “L” input voltage “H” output voltage (I/O) “L” output voltage (I/O) Open drain “L” output voltage (Not Ready) “H” input current “L” input current Off state “H” output current Off state “L” output current Static current dissipation (active) Two-port stand-by One-port stand-by Two-port full stand-by One-port full stand-by Input capacitance Output capacitance in off state Stand-by current Unit V V V V V µA µA µA µA mA mA mA mA mA pF pF Limits Min. 2.2 –0.3 2.4 Typ. Max. V CC +0.3 0.8 0.5 0.5 10.0 –10.0 10.0 –10.0 0.1 Notes 3: The direction in which current flows into the IC is defined as positive (no sign). 4: The above typical values are standard values for VCC = 5V and Ta = 25°C. Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature range
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 5V±10%, unless otherwise noted) Read cycle Symbol tCR ta(A) ta(CS) ta(OE) tdis(CS) tdis(OE) ten(CS) ten(OE) tv(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after CS (Note 5) Output disable time after OE (Note 5) Output enable time after CS (Note 5) Output enable time after OE (Note 5) Data effective time after Address Limits Unit ns ns ns ns ns ns ns ns ns Typ. Max. Min. TIMING REQUIREMENTS (Ta = 0 ~ 70°C, Vcc = 5V±10%, unless otherwise noted) Write cycle Symbol tCW tw(WE) tsu(A) tsu(A-WEH) tsu(CS) tsu(D) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) Parameter Write cycle time Write pulse width Address setup time Address setup time for rise of WE Chip select setup time (for WE) Data setup time Data hold time Write recovery time Output disable time after WE (Note 5) Output disable time after OE (Note 5) Output enable time after WE (Note 5) Limits Unit ns ns ns ns ns ns ns ns ns ns ns Typ. Max. Min. Note 5: The time required for the output to change from a steady state to ±500mV under the load conditions shown in Fig. 2. This parameter is guaranteed but is not tested at shipment. NOT READY TIMING (Ta = 0 ~ 70°C, Vcc = 5V±10%, unless otherwise noted) Symbol tNAA tNDA tNAC tNDC tAPS tNO tNW Parameter Not Ready access time from Address Not Ready disable time from Address Not Ready access time from CS Not Ready disable time from CS Arbitration priority setup time Data output access time from Not Ready Write hold time from Not Ready Limits Unit ns ns ns ns ns ns ns Typ. Max. Min.
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX TIMING DIAGRAM Read Cycle (WE = VIH) Read cycle No. 1 (Address control) (CS = OE = VIL) Previous cycle data Data output determined tCR A0~A 7 ta(A) tv(A) I/O0~I/O8 (DOUT ) tv(A) Read cycle No. 2 (CS control) High impedance Data output determined A0~A 7 CS OE I/O0~I/O8 (DOUT ) tCR ta(A) ta(CS) ten(CS) ta(OE) ten(OE) tdis(OE) tdis(CS)
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX Write Cycle Write cycle No. 1 (WE control) See Notes 6, 7 and 8. Data input determined A0~A7 CS WE I/O0~I/O8 (DIN) tCW tsu(CS) tw(WE) OE I/O0~I/O8 (DOUT ) tsu(A-WEH) trec(WE)tsu(A) tsu(D) th(D) tdis(OE) Write cycle No. 2 (CS control) See Notes 6, 7 and 8. A0~A 7 CS WE I/O0~I/O8 (DIN) I/O0~I/O8 (DOUT ) tdis(WE) tCW tsu(CS) tw(WE) tsu(A-WEH) tsu(A) tsu(D) trec(WE) th(D) ten(CS) Data input determined Notes 6: The WE of the port must be set to “H” when an address input changes. A write operation is performed during the overlap period when both CS and WE are “L”. Do not apply any negative-phase signal from outside when an I/O pin is in output state. The shaded part means a state in which a signal can be “H” or “L”.
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX Contention Read Cycle (WE = VIH, OE = VIL) Contention read cycle No .1 (Address control) See Notes 10 and 11. ∗ Address A = Address B Address B (Address A) ∗ Address matching Address not matching Previous cycle data Data output determined Address A (Address B) Not Ready B (Not Ready A) I/O0B~I/O8B (I/O0A~I/O8A) tAPS tNAA tNDA tv(A) tNO ta(A) Contention read cycle No. 2 (CS control) See Notes 10 and 12. ∗ Address matching Not Ready B (Not Ready A) I/O0B~I/O8B (I/O0A~I/O8A) tAPS tNAC CSB (CSA) CSA (CSB) Addresses A & B tNDC ten(CS) tNO ta(CS) Data output determined ∗ Address A = Address B Notes 10: 11: 12: The Not Ready output of the first-in port holds “H”. When CS is set to “L” before the address input is determined. When the address input is determined before CS transition to “L”.
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX Contention Write Cycle Contention write cycle No. 1 (WE control) See Notes 6, 8, 10 and 11. ∗ Address matching Not Ready B (Not Ready A) I/O0B~I/O8B (I/O0A~I/O8A) (DIN) tAPS tNAA WEB (WEA) tNDA ∗ Address A = Address B Address A (Address B) Address B (Address A) I/O0B~I/O8B (I/O0A~I/O8A) (DOUT ) Data input determined tsu(A-WEH) tsu(A) tw(WE) tsu(D) th(D) ten(WE)tdis(WE) tNW Contention write cycle No. 2 (CS control) See Notes 6, 8, 10 and 12. ∗ Address matching Not Ready B (Not Ready A) I/O0B~I/O8B (I/O0A~I/O8A) (DIN) tAPS tNAC WEB (WEA) tNDC ∗ Address A = Address B I/O0B~I/O8B (I/O0A~I/O8A) (DOUT ) tsu(CS) ten(WE) tNW tsu(D) th(D) tw(WE) tdis(WE) Data input determined Addresses A & B CSB (CSA) CSA (CSB) ten(CS)
MITSUBISHI 〈DIGITAL ASSP 〉 M66221SP/FP 256 × 9-BIT MAIL-BOX SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT Input pulse level : V IH = 3.0V, VIL = 0V Input pulse rise/fall time : tr/tf = 5ns Input timing reference voltage : 1.5V Output timing decision voltage : 1.5V Output load : Figure 1 ~ 3 (The capacitance includes stray wiring capacitance and the probe input capacitance.) Fig 1. I/O Output Load Fig 2. I/O Output Load (to ten, tdis) Fig 3. Not Ready Output Load + 5V 1250Ω 100pF775Ω I/O 1250Ω 5pF775Ω I/O 575Ω 50pF Not Ready + +