M65821

Mitsubishi Electric Sem...

CD PLAYER DIGITAL SIGNAL PROCESSOR

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M65821FP MITSUBISHI | Alldatasheet

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| MITSUBISHI SOUND PROCESSOR ICs |

DESCRIPTION

The M65821FP is a signal processing LSI using silicon gate CMOS technology for use in a compact disc (CD) player. The M65821FP incorporates the functions of data slicer, PLL for clock extraction from HF data, demodulator, decoder, error corrector, interpolator, 4fs digital filter, digital interface and disc motor speed control in single chip.

FEATURES

Adjustment free EFM-PLL (VCO builtin) with 2 wide lock range Witter margin +8 frame MEasy-tohandle CLV servo command Sufficient mute control (zero-cross/fade mute) MiLch/Rch monaural output Attenuation can be designated independently for L & R channels [Error flag output in one byte WMHighverformance 4Fs digital filter WIBbit/20bit outputs available Outline 42P2R-A WCentralized control by microcomputer serial command 0.8mm pitch 450mil SSOP Hower power dissipation during standby in the sleep mode (Bem x 175mm x 20mm) WDigital deemphasis circuit builtin WDigital silent detector circuit builtin Reduced base area by a smaller package RECOMMENDED OPERATING CONDITIONS Supply voltage range----e---seeeeeeneeeV00 = 4.6 to 5.5V Rated supply voltagers:::s:sssseeeesseeensseetinsenees Vo = 5V Rated power dissipation «----ss--sssesesssseersseeeeessee | 25mW SYSTEM BLOCK DIAGRAM pt ST EN aah Pe ne DISPLAY ° DIGITAL Sp haa DIGITAL i guy ‘SUBCODE OUTPUT ¥ © © {INTERFACE OPTICAL cM D/A [DIGITAL | sours ae pat DIGITAL fe ace @ SILENT LG =| SILENT PICK-UP cy vL_iecsram_] {28 (OUTPUT SERVO ici sno} STEEP 7 ue M65821FP Mi 6249826 0021433 117

9 MITSUBISHI

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR serena BUILT-IN FUNCTIONS © Adjustment free EFM-PLL © Digital filter + Slice level contro! +4 times oversampling phase linear digital filter * Bit clock generation + Digital filte-thru + Adjustment free VCO + 18bit/20-bit output (only when a digital filter is used) © Demodulation & Decoding @ CLV digital servo + EFM demodulation + Low disk rotation detection + Frame syne detection, Protection & interpolation + PWM output + Subcode demodulation (serial) © Digital de-emphasis + Subeode Q-CRC check + Automatic detection of emphasis flag + Subcode Q register + Intermnal/external emphasis changeover + Emphasis detection @ Digital silence detector + Jitter absorption + 8 frame + Audio data silence detection * CIRC decoding @ Microcomputer interface Unserambiing + Mute, attenuation, disk motor ON/OFF, disk motor brake Deiinterleaving control Error-correction capability C1 : Duplex ; C2: Duplex *DigitalOUT ON/OFF, fade mute selection, digital filter ‘Interpolation processing (average value Interpolation & through selection, interpolation inhibit selection, clock Previous value hold) Precision input, 18-bit output selection, 20-bit output + Error monitor output selection, dual DAC selection, stereo/monaural selection + Interpolation inhibit + Attenuation lavel contro! + Zero cross mute *Subcode Q register interface + Fade mute * Sleep mode control + Digital attenuator Digital audio interface + Dual DAC output + Digita-OUT ON/OFF +L/R monaural output * Clock precision input @ Master clock changeover * Master clock 8.4672MHz/16.9344MHz selectable PIN CONFIGURATION (TOP VIEW) Voor [1] [#2] Vssi exp [2] fi] sock syeuk fa] EFF Lock/oro [2] B33] seco SCAND [5] fas) Pwo crcr [6] Ei] pwoe seas [36] LACKs uso [5] [5] LACK2 ACTA GY} 4] LRCK: mck [10] 3] wock ME [ 82] OscK MoDo [i] Bi] CKSEL mons (3 B30) DO2 mone [iq] 23] DO: oo [15] [28] DOTX mer [15] [27] xo HFO Ba) xi LPF (18 B25] RSIL/EST1 HF (13) ied] LSIL/EST2 Tie 2} 23) C423 vssz Qj 22] caas Outline 42P2R.4 @® 6249826 0021834 Ost

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MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR PIN DESCRIPTION [Pin No.] Name [17OT Function) [Pin No| Name [1/0] Function +4 [ @_ | Voor | = | Digital system Voo LsILy Lech silence data output : ® Emphasis output. : EST2 error status output 2: “H" for emphasis “H" at Cz decoder error detection | @ | SYCLK| 0 | Frame lock status output. Lock =H RSIL/ Reh silence data output : @ | LOCK Syne status & low disk rotation ® |esr error status outout 1: DRD staus output “H" at Ci decoder error detection Subcode sync signal output : Crystal oscillator input : @ | SCAND [0 | *H” for sync }@ |x [a] feedback resistor built in CRF CRC checked results of subcode: | [| @ [Xo | O | Crystal oscillator output __—_—_—_—+d CRC_OK =H | @ | DOTX [0 | DigitaiOUT output sBQS subcode Q register read interrupt @ Audio serial data output for DAC: signal, : "L” for read-around Lich outout at dual DAC mode @ | sp |1/0| Microcomputer interface serial data Reh output at dual DAC mode vo LRCKI inversion at single DAC mode | @ TAUCK | 1 | System reset inout:reset=C | | exge, Master clock selection input | @® | MCK | | | Microcomputer interface shift clock (H: 8MHz, L : 16MHz) [® [MLA [1 | Microcomputer interface latch clock] | @ | DSOK | © | Data shift clock for DAC | ~@ [MOD | T | Microcomputer interface mode 0 | {| @ | WOCK | O | Word clock for DAC | @ | Mod: [1 | Microcomputer interface mode 1 | @ | LRCK: | O | LR clock 1 for DAC | @ | MOD2 | “1 _| Microcomputer interface moda 2_|{ @® | LRCK2 | O | LR clock 2 for DAC | —® | Vooe | — | PLL system Voo | —@ | LRCKs [0 [LR clock 3 for DAC ® PLL circuit reference current Disc motor drive PWM output 2 setting (acceleration side) High frequency signal missing Dise motor drive PWM output 1 | @ [seco | "0 | Subcode serial output | @ [HF [1 | High frequency signal input | EFM frame clock output. | -@ [TS [OT sice tevel control outout | ore duty 6 50% | @ | Vsse_|- | PLL system Vss io Shift clock input for serial @ | cess Crystal system 8.4672MHz clock subcode data output output @ | vssi |= J Digital system Ves Crystal system 4.2336MHz clock [© [ees | o [Sue en SE oe | a SSSSSSSSSSSSSSSSSS MM! 6249826 0021836 12°59 MITSUBISHI weitere 2-107 i ee Se

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR Oe FUNCTION DESCRIPTION 1, MICROCOMPUTER INTERFACE (1) Connection MODO, i wesezire [sp] MiorocoMPuTER [Pin No. [Signal name [Contents TO] MODO to MOD2 | Mode selector pin TT | © [Msp | Microcomputer serial data 170 pin Microcomputer serial clock input_pin [| [@ [Mia Microcomputer data latch signal inout pin |_| (2) Explanation of modes Number [mois aod Poot | Hao Date contents V0 | of bytes po pot ft Tt TCL servo control pap oc ft fH [status control p2 } tT CH [tT attenuate resister control [tT ps3 [tT TH] J Subcode @ register_control [ o | io} p 4 [Ht | | RESERVED ae fs | Hw [ {TH | RESERVED {| = [= | pe [WH [tT Steep ‘mode L7 [a TH | H | Test mode (for delivery sorting) [1 o_ | Note: 1/0 is as viewed from M65821FP_ (3) Microcomputer UO timing Input timing (M65821FP <= Microcomouter) Output timing (M65821FP => Microcomputer) i aS CT) Ce a” Se ' H ' ' wso [eo [oi [ea [es [ba [os Joe] 7 1 MS Teo[br Pea [ea Teas [es [or ; ere eR oR ee te MLA Tr H ‘ote tt! [ Symbol [Description Min [Unit | | ti: _ | -Shift clock width 200__| nsec | 7 Shift clock width [200 [nsec | Shift clock setup time 100 | nsec ta | Mode setup time 250_| nsec [ts | Shift clock hold time 100 __ | nsec tio__| Mode hold time 200 | nsec | ta | Latch clock setun time Latch clock width | 200 | nsec | [ts | Mode setuo time [250 | nsec Mode hold time [200 | nsec —_—._-sw ese M™ 62494eb 0021838 77] MITSUBISHI ae MTUES 2-109

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR CHARACTERISTICS OF SLEW RATE Applied pin : MCK, SCCK . . oof ono 90% : [Symbot [Condition [Win [Tyo] Max | Unt] 1 Lt 42vevonss SV TT = 1.0 [msec | ‘TSLH! ‘Tsu (4) Mode 0:CLV servo control (Mode 0 : MOD2 to 0=(0, 0, 0)) CLV servo, mute, attenuate and fade mute are contriolled by cotrolling the register in mode 0. [OuMMY | Dontewe UL XT TT TT Co eee stop_control [ste Control for dise motor | Braking || | 0 | | ||| _] reking [No bring | | PT] TT Pd face nob ns Pes Pe an v7.20 attenuation vontl| ATT OFF SS ATT ON a Mure Mote con [Mure ON] | |_| | {of | [ure ore a S/S tow wuai| S75 rer (O38) [Timer operation | ||| || | o | | fee ein ot ge [Tntial state | Resister contents in reset conditions | 0 | 0, o,11)olol1|0] (8) Mode 1:Status control (Mode 1 : MOD2, 1, 0 =(0, 0, 1)) The status register consists of 2 bytes, and setting is By setting a register in mode 1, it is possible to determine possible by starting up MLA after inputting 2-byte data to ‘the status required in operating the signal processing unit. DSP, [1 byte] Revister name Function [bo [bi [2 [ta | oa | os | 06 | or | Se NON-AUDIO | Control for eudio or non | Audio fT PT audio dota Ae foes [em st Fp PP lean Control for 1ebit ota LLSbt outst Po [revit out |) tt [aoa | canvat for a0en ana FSB owout wa [JY Yo [2obit outst | DUALDAG | Cantral for single or dual [SINGLET | TT Od DAC mode DUAL a AO [Stereo] tT | Tr OT LMONO Leh monaural ovtout ich moneurd | | || || | +] _] [awono | Ron mona cme fowee [inital state | Register contents in reset conditions | o | o{o}fo;ololol|o WM 6249826 0021839 638 MITSUBISHI 2-110 ate MISES nr

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR [2 byte) a FMUTE Controlling fade mute ON/| Fadeout | OTT OFF (See Note) [Fadein J rar | Conteline the fade mute | 2asee_f Fo ff time [348ms | Fucnt | Fado mute used/not used} Not wwe —_f [fo ff [Used 7MCM Controlling zerocross mute | Zerocross present | | [To [tT or no zerocross mute | No Zerocross [Tf [cox | osstaton rection nour [ERR _—{ ff _}e ff} [Level WP Conteoting the presence or | Internal emphasis [ [TT fo fT absence of digiral deemohasis| External emphasis [| [TT Tt | SIL/EST Controlling silence outout [Silence output [| [TT and error monitor output | Error monitor output] [| TT | Stereo | me [een ess fee Pt ttt [initial state | Registers contents in reset conditions | 0 | o | o Jo foto foto | Note 1. The FMUTE register changing point is detected for operation + Fade in when “O"changes to “I” + Fade out when “I"changes to “0” 2. When the FMCNT register is “1°, the attenuate register becomes effective. 3. The status data input sequence is as follows Ist BYTE 2nd BYTE f eR i so [vo [er se fears [os [eefer [oper [ez [ea [ee [es [os [er] MLA f (6) Attenuate register control (Mode 2: MOD2, 1, 0=(0, 1, 0)} The attenuation level can be set independently for L and R setting is carried out by inputting a clock to the MSD pin channels by using the attenuate register. with LSB first. from L-channel side. This register is set, using 8-bit for L and R channels : this MSD, MCK, and MLA at this time are shown below : mso [eoTurf2fisfis [is [is fur [ro] ni [re [ra [re [rs [ne [7 MLA f The relation between the attenuation data and attenuation level is shown in para. 10.(4). WM 6249426 0021840 35T MITSUBISHI eee 2-11 OOOO

MITSUBISH! SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR (7) Subcode Q register interface (Mode 3: MOD2. 1, 0=(O, 1, 1)) The data of subcode Q stored in the internal 80-bit register are satisfied and the internal register is placed in readable can be read with a serial clock from the microcomputer. conditions. When MOD2, 1, 0 =(0, 1, 1), MSD is placed in output <Conditions under which the SBQS pin is placed in “L" > conditions, and the register is set by inputting 80 clocks to (@) When the CRC checked results is OK the MCK pin from SBOQS pin rise to the next SBOS fall. (b) When both subcode syne signals So, Si are detected The data from the MSD pin is output with MSB & LSB in the specified position. (So and $1) inverted in Bbit. When both conditions (a), (b) above are satisfied. the The SBQS pin outputs “L” when the following conditions SBQS pin outputs “L”. wso [er [ez] 23 [e+ Jos [86 [er | oe [50 Te] i Ses. T5H2 TYP so [or Jos os] o« Tos oa for [oof is Tre [is Piz [1] 10 Too Jos ‘ise 1 BYTE wSB The emphasis information of subcode Q data is output to the EMP pin. [Condition TEMP pin | (8) Sleep mode (Mode 6 : MOD2, 1, 0 =(1, 1, 0)) The sleep mode is used when LSI is not used: the master pin when MOD2, 1, O=(1, 1, 0). To release to the sleep clock stops, and the low power dissipation mode is selected. mode, set the ALCR pin to “L” once and set it to "H” again. The sleep mode is selected by inputting “L" to the MLA MoD2~0 OTHER THAN MODE 6 OTHER THAN MODE 6 +——tr ALOR H NORMAL MODE ° ‘SLEEP MODE : NORMAL MODE Symbol Description [Min | Unit | Set-up time of mode Lv [etsesens | 0 | me (8) Test mode (Mode 7: MOD2, 1, 0 =(1, 1, 1)) This mode is used when LSls are tested before shioment: matter as in mode 6 ; even when MOD2 to 0 is (1, 1. 1) it is a use inhibit mode. momemtarily when the mode is switched, it is not latched Mode 7 is set by latching with the MLA signal in the same to. the inside. oO M@@ 6249426 0021641 24h MITSUBISHI 2-112 oe ias a eee

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR OO (10) Reset input timing (Only digital audio interface mode) af If digital audio interface is not [_Symbol [Condition [Min | Typ | TST used, this specication is onowc. [Tasr | st - _| ~ | 10.0 | msec | 2. SUBCODE INTERFACE The subcode data (P,Q, R, S, T, U, V, W), can be read from the SBCO pin by inputting a clock to the SCCK pin among agg L] at ‘the data coverted from 14-bit EFM signal to 8-bit symbol, lotr {| When both subcod sync patterns So, S: are detected in the ' coed postion ab ¢ oe sna of tie steee, 2 ome LLLP signal is output from the SCAND pin. H If 8 clock or more are input to the SCCK, the SBCO is placed eee in “L". 3. EFM-PLL CIRCUIT (1) Data alicing/PLL The M65821FP has an analog front-end for incoming HF the M65621FP with a wide capture/lock range. There is no (EFM) signal. Using CMOS-Analog technology, the front-end need to adjust the VCO. LPF is the charge-pump output and comprises an automatic slice level control circuit and EFM: ‘same-time contro! voltage input to the VCO, LPF froms off PLL circuit with internal adjust-free VCO. The block-diagram if HFD goes High. shows the analog frontend. The HF signat is sliced by the IREF is the reference current input used to determine the HF comparator and a DC level is feed back from TLC to current of charge pumps of TLC and LPF, operating point HF through the external CR. If HFD goes High because of of HF comparator and VCO free running frequency. If IREF @ defect an disc, then TLC time off and holds the DC level. is connected to a noisy power supply through a resistor, EFMPLL extracts the EFM clock signal from the HF signal. VCO is modulated and the error-rate increases. Therefore, The PLL circuit has @ phase/frequency detector providing power supply noise at IREF must be held to a minimum. IE Tu LPF, [= O HF COMPARATOR HF SIGNAL O+}+-( HE CHARGE CHARGE | | [CHARGE [LO Lene iP Powe {row | C_] ti HED. O ve voo — FREQUENCY] MITER HF COMPARATOR | FREQUENCY CURRENT nm SOURCE LPF me) Ste i EFM DATA] | EFM GLOOK NONSYNC FRAME FRAME SYNC COUNTER EFM CONTROL UNIT CLOCK DEMODULATOR CIRCUIT Fig. 1 Block diagram of the analog front end ee MB 6249826 0022842 122 Ml MITSUBISHI ears 2-113 a

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR SS (2) Slice level controt (4) Reference current setting sv HF SIGNAL O——| HF ’ cur Mese21FP Pree TLC cme: (RECOMMENDED VALUE) Se uttiooe, AWE J RiREE = 180kQ (Normal speed) Gn 0022 uF FIREF = 150k2 (Double speed) RILc = 33k @ . Vin HF OSVP-P Min A resistor must be connected between the IREF pin and Voo A slice level control circuit is formed by connecting a resistor in order to set the reference current used in determining the and capacitors to the HF (High-frequency signal input) pin current values of the TLC pin and LPF pin, the compatator and TLC (Slice level contro! output) pin. ‘operating current of the slice level control circuit, and the VCO freerun frequency. (8) PLL circuit LPF Mese21FP Feo “| fre t T a (RECOMMENDED VALUE) CLPF = 4700 C1=0.15 uF to LOuF Ri = 2.2kQ Reo = 3.3MQ Since the adjustment-free VCO is built in, the adiustment-free PLL circuit can be formed by connecting a resistor and capacitors to the LPF (Lowass filter) pin. From servo IC : 1 tuo | pep S porns Me5821FP i i — LPF aren PLer : I r (RECOMMENDED VALUE) CLPF = 4709F C)=015 uF to 1.0uF* Rupr = 22k Rep = 3.3MQ The error rate characteristics of defect disc is imploved by . connecting Rep to HFD using dioade. From O.15uF to 1.0uF capacitor is available for Ci. In high speed search such as track count search, the rotation of disc decrease. If this is problem, this problem is improved by using large Cr. (See sec. 5 -(3)) Ss Mi 6249826 0021843 069 MITSUBISHI 2-114 ees

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR 4, EFM DEMODULATOR EFM signal converted to the logic level and clock reproduced The syne circuit has @ system of protecting syne even when from EFM signal are input to the demodulator block, which a syne pulse is missing and preventing syne errors in bit slip is then converted to an Sbit symbol deta. or re-pullin from pulrout, thus maintaining stable syne even This EFM signal demodulation is based on the EFM for disc defects (flaws & stains). conversion table specified in the RED book. The block diagram for this frame syne control is shown in To demodulate EFM signal, the demodulator circuit should be Fig. 2. below. synchronized in frames for EFM signal. EFM-*SYMBOL CONVERSION veo: EOGE EFM TIMING GENERATOR SYNC. . arrtid SIGNAL |GENERATOR SYNC LOCK NON-SYNC SYCLK Fig. 2 Frame sync control unit block diagram In the block diagram above, the conditions of generating To monitor a synchronous condition with a control counter reset signal, “Reset” in the EFM timing generation microcomputer, it is necessary to provide a signel from which unit can be expressed in the following equation. 2 shortperiod missing of sync pattern due to a disc defect, Reset = Syne * Tfs + Sync * Window which occurs even in @ synchronizing state is eliminated. (where : * = Logical product AND += Logical sum OR) In MG5822AFP, this signal is allocated to LOCK/DRD pins. In this equation, Sync, Ts and Window mean a syne signal, When the braking instruction from the microcomputer is not 2 detection signal of syne signal spacing (= 588), and +7C input, the LOCK/DRD pins monitor the synchronizing state window signal respectively. in 1/16period of EFM frame clock, outputting the results. In the synchronizing conditions, Syne and Tfs generate at the If the monitored results are sync, “H” is output, and if they same time, and Sync enters the window center. In this state, are not sync continuosly 8 times, “L” is output.(When the it follows that “H” is output to SYNCLK pin and EFM signal braking instruction is input from the microcomputer, the is synchronizing in frames. LOCK/DRD terminals output a low disc rotation status monitor signal (ORD signal). The details are described later Sycuk in the CLV servo control paragraph.) EFM signal is not in L synchronizing in frames Contents. LOCL/DRO EFM signal is synchronizing in H EFM signal is not L frames Not in @ | synchronizing in 1/16 frames: braking condition EFM signal is synchronizing in 1/16 frames Braking Low disc rotation status monitor signal 8/DRO signal | OR signe! M@™ 6249826 0021844 TTS a MITSUBISHI ae MISES 2-115 a

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR -/—$ mK ee 5. CLV SERVO CONTROL (1) PWM control (2) Low disc rotation control The CLV servo control circuit controls the disc motor with When playback is suspended, disc rotation should be stopped the frequency difference between the clock reproduced from securely. The LOCK/DRD pin monitors the PLL oscillation EFM signal and clock obtained from the standard oscillator, frequency the disc is being braked with an instruction from and the address difference in internal RAM writing. the microcomputer, and outputs “H" if it detects @ frequency The motor control output is transmitted to PWM: — lower than 3/4 of that in normal playback. (deceleration output) and PWM (acceleration output) pins By adjusting the period of @ brake signal with this signlal, in PWM waveform, disc rotation can be stopped. Since the phase is internally compensated. the CLV servo Girouit can be configured by just connecting a driver to the Syne status PWM and PWMz pins outputs. moritor output! 3/4 or less Fig. 3, shows the CLV waveform and its duty. H } frequency In the CIRC composite section, the duty is reset to 0 where LOCK/DRD. the address difference between builtin RAM wrtie and read i exceeds +8 frames, BRAKE In this figure, the point in which the waveform width of acceleration output and deceleration output is equal is shown as dut "0" waveform is used directly or even through and analog signal The PLL oscillation frequency When the disc motor is driven with an analog signal, servo Braking roomate — gain can be set exteray. Tee] When it is driven with a PWM waveform, however, the PWM normal playback waveform cannot adjust the duty from the outside ; therefore, the servo chracteristics are determined with the motor torque or disc turntable, disc retaining angular moment, etc. (3) High speed search In case of high speed search such as track count search, pwme__ PL the disc rotation may unstable in search mode. Because the false lock protection circuit is working in search “Tt mode by long time unlock. The false lock protection circuit can stop to work by using BRAK register in MODO, 2usec |2usec 22.7 usec ~ LOCK/DRO : ORD output H * [raniovcoteration [CK oury puny = Wee = wPunu a rs: “ — | LOCK/DRD : LOCK monitor outout Wewn2 + Wevinat ei = 8 FRAMES LZ \\ Le a 778 FRAME When BRAK register is 1, the false lock protection circuit a stop to work and the disc rotation can improve in search Y H mode, When BCON register is 1 S/S register is 0 and BRAK oe i register is 1, brake function is working. If BCON register is 0 or S/S register is 1. brake function is not working. But when BRAK register is 1, LOCK/DRD output DRD signal. So it is necessary to change BRAK register from 1 to 0, when Fig. 3 CLV waveform search is completed. ss M@ 624948eb 0021845 93] MITSUBISHI 2-116 ae MBS

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR ——_S:.-s $ 6. ERROR CORRECTION (1) Correction ability Both decoders C1, C2 correct dual errors Max. (2) Error monitor output The error status detected at decoding is output to pins interface, no output data is interpolated,and the error status EST1, EST2. of decorder C2 is output to the data (each byte) detected If an error is detected with decoder C1, “H” is output to pin as uncorrectabie. EST: for its frame. and “H” is output to pin EST2 for an If an audio data is selected, the error status is output to erroneous word judged to be uncorrectable with decoder C2 the interpolated word (2 bytes). If a nonaudio data is selected in mode 1 of microcomputer, For detailed timing, refer to “D/A Interface” ‘ 1_ FRAME A 1_ FRAME 1 Lia te PRAME esti t ' FRAME IN WHICH NO ERROR WAS DETECTED FRAME IN WHICH AN ERROR WAS DETECTED: (a) For audio data wock H i EsT2 a ee H i "INTERPOLATED WORD" (b) For non-audio data wock EsT2 vor a ee ERRONEOUS DATA ERRONEOUS OATA "ERRONEOUS DATA” (3) Interpolation The average value is interpolated or the porevious value hold interpolation is carried out, and in other cases, the previous is interpolated for the word that cannot be corrected by value hold is carried out decoder C2, thus preventing noise from generating. However, if the non-audio data is selected in mode 1, If the anterior and posterior words from which an error was 0. interpolation processing is performed. (Refer to detected prove correct after detection, the average value “MICROCOMPUTER INTERFACE”.) wock esT2 AVERAGE VALUE INTERPOLATION PREVIOUS VALUE HOLD AVERAGE VALUE INTERPOLATION a MH 6249626 0021446 373 MITSUBISHI eSBs 2-117 a

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR 7. DIGITAL OUT The digital audio signal formatted according to EIAJ 340 “Digi , oo aun ona Standard CP-340 “Digital Audio Interface” is outputted to PREAMBLE DOTX pin. 16 porx The validity flag is internally set to “1” automatically when ° the interpolated word is transmitted, [tf The user date, which is read in the subcode interface circuit, is transmitted. Channel clock precision can be set from the SENET ON outside so that it is compatible with the validity pitch. _pREGSIONTHALNEL The channel status is set to level Ill in the validity pitch, [ser recisren] mode, and level Il is set autometically when it is not in the 7 ROUT validity pitch mode. CONTROL SUBCODE Q TO W of mode 1 of microcomputer interface. 8 : CHANNEL L AND TOP OF BLOCK ouannce erat M: CHANNEL L EXCEPT TOP OF BLOCK ATUS W: CHANNEL R- USER DATA VALIDITY FLAG t a a OPS ° “ger aer 4en se 16 aT Men ta Sub frame format . 1 SUB FRAME 1 SUB FRAME 1 rl a A FRAME 191 ' FRAME 0 ' FRAME 1 ' Frame format O12 3 4 5 6 7 8 9 1011 12 13 14 15 ol o Fam ateoue 9 jo faxamese | |o[e] [of ]o] Jo] fo] spltelrels elt tlt Ly 32) SOURCE CODING ' | asl From status register CHANNEL CODING | i i | 64} (BIPHASE MARK) a Foliiololtiiioliiolritiolo! | Channel coding (Biphase mark modulation) 112 ALLO 128) When the Dour register is “H", the digital interface outout ‘44! is stopped to prevent from radiation. 160| Chanel status is set as follows. 176] ID1, COPY and EMP data in subcode Q data transfer to the channel status register in digital audio interface, when CRC is OK and subcode synchronization pattern SO and S1 are detected in right position. EST2 flag copy to validity flag. M@® 6249826 0021847 704 MITSUBISHI 2-118 oe iieee

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR $C ANER DIGITAL SIGNAL PROCESSOR 8. THE DIGITAL FILTER 9. DIGITAL DE-EMPHASIS The data of sampling frequency 44.1kHz is converted to M65822AFP has a built-in digital de-emphsis circuit that of sampling frequency 176.4kHz at 4 times over- containing a primary IR filter. When DDEC bit of the status sampling by FIR phase linear digital filter. It is also possible register is in “L", the source emphasis information is to output deta of 18-bit and 20-bit that were computed by detected : if emphasis is resent, the de-emphasis ciruit of SO ‘the digital filter. The digital filter may also pass according to /15() operates automatically. the purposes : a high-precision digital filter is connected When DDEC bit is in “H", the intermal de-emphsis circuit is ‘externally, and this filter is suitable for signal processing that disabled regardless of presence or absence of emphasis handles non-audio data, such as CD-ROM as well. information, and only emphasis information is output from The characteristics in over-sampling are shown in Fig. 4 EMP pin. (When DDEC bit is in “L", emphasis information below. is also output from EMP pin.) ‘The following is the chracteristic chart for the de-emphsis circuit built in the M65822AFP. FREQUENCY CARACTERISTICS 0 y fo) Py tT tT tT TT] [ -10 " -10 es a es a g ps = -50 -50) f\\ WN AMI | re ee ee | -80 80 ~1000-56-20a0 408060 700 88.2 71005 5 10 15 20 Frequency (kHz) Frequency (kHz) PHASE CARACTERISTICS or 180

4 Fay ETT 150) —— |-—

i 120 }— — g-4 oe ccs a ce a -5 -0 — aes a OO a é 6 [| — THERESE fe 2-—t—

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aot_L I TT TT Tt | yo © 10 20 30 40 50 60 70 80 882 0 5 10 15 20 Frequency (kHz) Frequency (kHz) Fig. 4 Characteristic curve of digital filter eee eee sa M@ 6249826 0021848 b40 me

4 MITSUBISHI

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR 10. MUTE CONTROL, (1) Zero cross muting Fade time In the MUTE command is input from the microcomputer, the timing (zoro-cross) at which the highest bit changes from*o” | __L_[ 22880 tol” or “I” to“O" is detected, actuating the mute cirouit, LH | 348mseo J . If zero cross cannot be detected within the specified time, the internal counter counts 34.8msec, forcedly actuating the (4) Control by the attenuate register mute circuit. if the ZCRC register is set to “1”, zero cross is forcedly If the FMUTE register is set at “1” with the FMCNT register muted with the MUTE command regardless of the presence at. “O", the audio data attenuates according to the contents or absence of zero cross. - of attenuate register, which are shown in Table 2. Attenuate register control is carried out in 8 bits (2) Attenuation control - independently for right (R) and left (L) channels according If the ATT register is set to "1", the audio output is to the microcomputer interface mode. transmitted with - 12dB down. As shown in Table 2, the attenuate register is set in 8 bits. However, control up to - 96.3dB is available with internal (3) Automatic fade mute processing. If the FMCNT register is set to “1", and the FMUTE register setting is changed from “0” to “1°, the internal counter operates and the audio data fades in, This date fades out by changing FMUTE register setting from “I” to “0” Two types of fade time can be set by setting the FMTC register. Since “FADE MUTE” operates with the level set by the attenuate register as standard, attention should be paid to the attenuate register condition before operation start. MH 6249826 0022849 587 Ml MITSUBISHI 2-120 oe lees

Table 1. Attenuation control

Table 1. Attenuation control (Continued)

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR 11. DIGITAL SILENCE When SIL/EST bit of the status register is in "L” if the audio Reh silence information and Lch silence information are data meets the following requirements, the computer regards output from RSIL/EST! and LSIL/EST2 pins respectively. If the current condition as silent, and a silence single is output both pins are judged to be silent, “L” is output. from RSIL/EST1 & RSIL/EST2 pins. When SIL/EST bit is in “H”, the pin becomes an error (Silence Conditions) monitor pin for error correction: C1 error and C2 error are (If the sudio data is hexadecimal, and the period of “O000" output from RSIL/EST1 and LSIL/EST2 pins respectively. or “FFFF” continues for at least 200msec, the current When SILC bit is in “L”, silence information is output condition is regarded as silent. However, if “0000” and independently for R & L channels as explained above. “FFFF” are displayed alternately even once within 200msec, When SILC bit is in “H”, silence information is output from it is not regarded as silence.) RSIL/EST1 pin if both Lch and Reh audio data sre placed in the silent state. 12. DAC INTERFACE (1) DAC Interface mode table NON. DUAL- Operation Fs a A Pee it ust DAC sf it inate DAC Ps fe) te fH] Lt _ | 200i single DAC | 4s | Pe ei aval BAC TSbit single DAC [Fs | De orci mods Fs (2) Stereo/Monaural mode selection [EMONO | RMONO | Operation H |e u Hi a MH 6249826 0021853 TOS ml ; MITSUBISHI 2-124 oe iees

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR CCD PLAVER DIGITAL SIGNAL PROCESSOR f cL ys att | is s| |8]s = a i = FI E 1) FA s FI FE eeeedetOTeHs AA 3 se} [e|

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MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR

13 OSCILLATION CIRCUIT

(1) Setf-oscillation clreult An oscillation circuit can be formed by connecting a 8.4872 MHz or 16.9344MHz crystal oscillator and loading to pins X1, Xo. 8.4672 (16.9344MHz) shaped from this oscillator is output to CB46 pin, and 4.2336MHz (8.4872MHz) divided and generated is output to C423 pin. : The oscillation frequency is selected as follows, using CKSEL ‘ pin: CKSEL, 8.4672MHz Normal playback 16.9344MHz mode Double speed Load capacity value | 8.4672MH2 | B00F 16.9344MHz ‘(M65822AFP xo xt a Cc T T ce (2) When external clock Is used 'f an 8.4672MHz or 16.9344MHz clock is present inside the system, the data can be input through the capacitor to pin Xi without using a crystal vibrator. (No capacitor is required if the input level corresponds to 2 logic level.) The selection of a vibrator according to the crystal clock output and CKSEL pin is the same as in self-oscillation. (M65622AFP x Xo 10009F |--0 8.4672 or 16.9344MHz [ External clock | Min. | Max. ] [va | GND | Vo | [Amplitude [iver | =] M@™ 6249826 0021855 840 MITSUBISHI 2-126 oe Mae

MITSUBISHI SOUND PROCESSOR ICs M65821FP CD PLAYER DIGITAL SIGNAL PROCESSOR APPLICATION EXAMPLE Veo! vss [2 EMPHASIS FLAG (2 |eme sock [41] P<] SUBCODE SERIAL INTERFACE {3 |svcux EFFK | Lock /DRD 800 EJ | Felecme PWM1 [36] > SPINDLE MOTOR CONTROL | Fer ref} {8 |mso LRCK2 | Ff cma} > [15] vooz porx 28} [> DIGITALOUT sam ler xO sag? INPUTS HFD x [26} pbb Pe LPF rsic/esti |25} na HE INPUT E>—{ HF LsiL/este|24] {21 | vsse case [22] @@ 6249826 0021856 717 ae ee

Product Information

M65821 specifications and overview.

Summary

CD PLAYER DIGITAL SIGNAL PROCESSOR

Description

CD PLAYER DIGITAL SIGNAL PROCESSOR

Source title M65821 Datasheet(PDF) - Mitsubishi Electric Semiconductor

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