M65762FP

M65762FP MITSUBISHI | Alldatasheet

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MITSUBISHI SEMICONDUCTOR (LSI)

DESCRIPTION

The M65762FP is a compression and decompression LSI conforming to the high efficiency encoding system (QM-Coder) in the International Standard, the JBIG/JPEG (ITU-T Recommenda- tions T.81 and T.82) for coding still images. It also conforms to the International Standard (ITU-T Recommendation T.85) for facsimile. The QM-Coder is an information dependent type which is capable of completely restoring original image data, and is equipped with the learning function to always optimize parameters according to the statistical characteristics of images. The QM-Coder is therefore superior in compression ratio compared with the existing binary coding system (MH/MR/MMR) and can greatly improve the half toning image (dithered half toning image) whose compression ratio is especially poor.

FEATURES

• Completely conforms to the International Standard (ITU-T T.85) for facsimile.
• Achieves encoding/decoding with the arithmetic coder (QM- Coder) conforming to the recommendation of the International Standard JBIG/JPEG.
• Is expected to conform to the International Standard for color facsimile (T.Pallete-colour).
• High speed processing that puts into effect coding and decoding at 40 million pixels per sec maximum.
• Is possible data-through processing without coding and decodin.
• Can select context
• Provides 10 pixel template model for minimum resolution conforming to JBIG and can select 2-line or 3-line template model.
• Built-in typical prediction function
• Capable of coding and decoding by using the typical prediction.
• Since use of the typical prediction does not require the processing of the line (TP line) which is matched the previous line's data, is capable of reducing data and processing time.
• Built-in adaptive template (AT) function
• Is capable of setting AT pixels before 127 pixels on the coding line.
• Since It is possible to change the position of AT pixel in a specified line, is capable of improving compression characteristics even when image characteristic is changed in the middle of the screen.
• Supporting multi-stripe
• When a page consists of more than one stripe, is capable of repeating encoding/decoding process in stripes.
• Built-in load/store function of line memory Supporting multiple planes and multi-stripe function
• Is capable of loading image data for reference line from outside to line memory of the LSI and storing image data from line memory to outside.
• Number of processing lines
• Is capable of issuing the start of processing (temporary stop command) several times to encode/decode any lines more than or equal to 65535 lines.
• Supporting 3-bus interface
• An 8-bit host bus corresponds to the MPU is available to load and store of context table RAM.
• For input/output of binary image data, is capable of performing 32-bit or 16-bit parallel or serial input/output.
• For input/output of coding data, is capable of selecting 32- bit/16-bit/8-bit bus to perform DMA transfer of coding data.
• Is capable of making scale-down for coding and scale-up for decoding.
• Is capable of setting marker code for coding and detecting marker code for decoding.
• Built-in RAM for 4096 bytes for line memory, built-in context table RAM and built-in probability estimation table ROM of 113 status
• +5V single power supply APPLICATION
• OA equipment including facsimile, copier and printer
• Digital and amusement equipment for the purpose of reducing memory

MITSUBISHI SEMICONDUCTOR (LSI) M65762FP PIN CONFIGURATION (TOP VIEW) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 M65762FP Outline144P6Q-A PD0 PD1 PD2 PD3 PD4 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 VDD GND PRDY PTIM PXCK SVID RVID PXCKO PD PD 26 PD 27 PD 28 PD 29 PD 30 PD 31 VDD GND PDRQ PDAK PDRD PDWR V DD GND CD0 CD1 CD2 CD3 V DD GND CD4 CD5 CD6 CD7 GND CDRQ GND VDD CD31 CD30 CD29 CD28 GND VDD CD27 CD26 CD25 CD24 CD23 GND VDD CD22 CD21 CD20 CD19 CD18 CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CDAK CDRD CDWR HD0 HD1 HD2 HD3 HD4 V DD GND HD5 HD6 HD7 TEST0 TEST1 V DD GND MCLK VDD GND RESET HRD HWR HCS HA0 HA1 HA2 HA3 TOUT1 TOUT2 INTR GND VDD VDD GND GND PD5 VDD GND VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD VDD GND VDD VDD

MITSUBISHI SEMICONDUCTOR (LSI) BLOCK DIAGRAM Description on Block Functions (1) Host bus I/F block This bus is used to set command parameters and load the status between the MPU and this block. It is 8-bit bus, This block is also available to load and store of context table RAM via the host bus. (2) Code data I/F block Bus for input/output of coding data. For the bus width, 32- bits, 16-bits or 8-bits can be selected. Image data can also be transferred (in through mode) between the Image data I/F and this block via built-in line memory. FIFO buffer for 16 bytes are provided in the code data I/F block. (3) Image data I/F block The Image data I/F is used for input/output of binary image data. The 32-/16-bit parallel I/F or serial I/F can be selected. Selection of the serial I/F transfers data in units of 1 pixel in synchronization with the line, using the handshake signal (PRDY*, PTIM*). Selection of parallel I/F uses an external DMA controller for DMA transfer (in units of stripe). The image data I/F provides a function for scale-down of length and breadth by 1/2 in coding and a function for scale- up of length and breadth by twice in decoding. (4) Line memory block 4K-byte memory. This block can be set to a maximum of 8192 pixels/line for 3-line template and can be set to a maximum of 10240 pixels/line for 2-line template. A line is used for input/output processing of image data to/from outside and the other lines (2 or 3 lines) are used for encoding/decoding processing. These two processes can be independently carried out in synchronization with each line. The contents of line memory can be loaded or stored via the image data I/F or coding data I/F. PD0-31 PDRQ PDAK* PDRD* PDWR* PRDY* PTIM* PXCK* PXCKO* SVID* RVID* CD0-31 CDRQ CDAK* CDRD* CDWR* RESET* HCS* HA0-3 Pixel data Image data I/F Line memory Context generation Context table RAM Encoding/decoding Probability Estimation Table ROM Host bus I/F Typical prediction Code data I/F Serial I/F Parallel I/F (5) Typical prediction block In the typical prediction mode, comparesthe encoding/ decoding process line agree with the immediately preceding line and generates pseudo-pixel (SLNTP). (6) Context generator By using the 10 pixel template of 2-lines or 3-lines.(including AT pixel) the standard context minimum of JBIG is generated with the resolution. (7) Context table RAM block Corresponds to the 10-bit standard context. This block can initialize, load and store the context table RAM. (8) Coding/decoding block This block performs arithmetic coding and decoding. It contains a ROM which contains a table capable of estimating 113 states and is capable of byte stuffing function ('OO' byte insertion/rejection) and is capable of end marker code control (Marker insertion/detection). 109 110 111 108 132 135 134 133 112 129 (Asterisk "*" indicates negative logic.) HWR* HRD* HD0-7 INTR MCLK

MITSUBISHI SEMICONDUCTOR (LSI) DESCRIPTION PIN (Notes) • Directly connect the input pin having pull-up (see Section 3.3.2 "Pin Function") to Vcc when the pin is not used.

• Directly connect the input pin having pull-down (see Section 3.3.2 "Pin Function" to GND when the pin is not used.
• Connect test input pin TEST 0/1 to GND.
• Leave test output pin TOUT 1/2 open. I/O Pin namePin No. GND PD0 PD1 PD2 PD3 PD4 V DD GND PD5 PD6 PD7 PD8 PD9 V DD GND PD10 PD11 PD12 PD13 PD14 VDD GND PD15 PD16 PD17 PD18 PD19 V DD GND PD20 PD21 PD22 PD23 PD24 V DD GND PD25 PD26 PD27 PD28 V DD GND PD29 PD30 PD31 V DD GND PDRQ PDAK PDRD PDWR V DD GND PRDY PTIM PXCK SVID RVID PXCKO V DD GND CD0 CD1 CD2 CD3 V DD GND CD4 CD5 CD6 CD7 V DD GND CD8 CD9 CD10 CD11 CD12 V DD GND CD13 CD14 CD15 CD16 CD17 V DD GND CD18 CD19 CD20 CD21 CD22 V DD GND CD23 CD24 CD25 CD26 CD27 V DD GND CD28 CD29 CD30 CD31 V DD GND CDRQ CDAK CDRD CDWR INTR V DD GND HD0 HD1 HD2 HD3 HD4 V DD GND HD5 HD6 HD7 TEST0 TEST1 V DD GND MCLK V DD GND RESET HRD HWR HCS V DD GND HA0 HA1 HA2 HA3 TOUT1 TOUT2 V DD Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O Power supply Power supply I/O I/O I/O Power supply Power supply O I I I Power supply Power supply O I I I O O Power supply Power supply I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I/O Power supply Power supply O I I I O Power supply Power supply I/O I/O I/O I/O I/O Power supply Power supply I/O I/O I/O I I Power supply Power supply I Power supply Power supply I I I I Power supply Power supply I I I I O O Power supply 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 I/OPin No. I/OPin No.Pin name Pin name

MITSUBISHI SEMICONDUCTOR (LSI) Description on Pin Functions I I I I I I O I/O O I I I I/O O I I I O I I O I O I I I/F Pin name I/O BUF Function H/W reset signal Chip select signal Address select signal of internal register Write strobe signal Read strobe signal Input/output data bus signal Interrupt request signal Coding data input/output bus signal (CD0-15 is used in 16-bit bus and CD0-7 is used in 8-bit bus.) DMA request signal for coding data (image data) DMA acknowledge signal for coding data (image data) Read strobe signal for coding data (image data) Write strobe signal for coding data (image data) Parallel image data input/output bus (PD0-15 is used in 16-bit bus.) DMA request signal for image data DMA acknowledge signal for image data Read strobe signal for image data Strobe signal for image data 1-line input/output start ready signal for image data 1-line transfer sector signal for image data Transfer clock signal for image data Transfer clock signal for image data (LSI internal loopback output signal of PXCK*) Image data input signal Image data output signal Master clock input signal Test input signal 0/1 (Should be connected to GND when used normally.) Power supply (+5V) Ground S S S UR8 US US US UR8 US US US US US U DS RESET* HCS* HA0-3 HWR* HRD* HD0-7 INTR CD0-31 CDRQ CDAK* CDRD* CDWR PD0-31 PDRQ PDAK* PDRD* PDWR* PRDY* PTIM* PXCK* PXCKO* SVID* RVID* MCLK TEST0, 1 V DD GND ParallelSerial Image data I/F Others Host bus I/F (Asterisk "*" in signal name indicates negative logic.)

• Input buffer for the input pins ("I" and "IO") are set at the TTL level and the options are as follows. (U: Having pull-up resistance, D: Having pull-down resistance, S: Schmitt trigger, R: Through rate control)
• Numbers (4, 8) in the BUF column for the output pins ('O' and 'IO') indicate Io (= 4 or 8 mA). Specifications (1) Package Plastic QFP 144 pins (20 mm*20 mm) (2) Power consumption 5V 120mA (600mW) (3) Maximum clock frequency 40MHz Code data I/F

MITSUBISHI SEMICONDUCTOR (LSI) Coding/decoding of existing product type (M65760/1FP) 1/compression ratio Processing speed (M pixels/sec.) Coding of M65762FP Decoding of M65762FP Coding/decoding of existing product type Coding of M65762FP Decoding of M65762FP Theoretical image Actual image (Legend) Baud rate and dither images Cafeteria and dither images Baud rate, error diffusion image Cafeteria, error diffusion image Average of test charts 1 to 8 of former CCITT Figure 3 Estimated Processing Speed

MITSUBISHI SEMICONDUCTOR (LSI) Register Configuration 1. List of Registers Table 1 List of Registers Address Register name R/W Content - LSI H/W reset - Selects bit width of code data bus (32 bits/16 bits/8 bits). - Selects coding (image) data byte swap on code data bus. - Selects coding (image) data bit swap on code data bus. - Selects image data bit swap on image data bus. - Selects image data I/F (parallel I/F and serial I/F). - Selects bit width of image data bus (32 bits/16 bits).

0 System setting W/R

• Template selection (3-line template/2-line template). - Sets up the AT pixel position (127 max). (When set to 0, selects non-AT (default position).)

1 Parameter setting W/R

• Interrupt enable setting corresponding to each bit position of status register - Indicates pause/restart with marker code detected (at time of decoding)3 Interrupt enable setting - Sets the number of pixels per line. (a maximum of 10240 pixels with 2-line template selected)4, 5 Setting number of pixels W/R W/R - Sets the number of lines to be coded/decoded (1 line or more, a maximum of 65535 lines)6, 7 Setting number of lines W/R - Number of setting the coded/decoded lines (a maximum of 65535 lines)8, 9 Number of processin g lines R - Buffer register that loads/stores context table RAM data from the MPU. (RAM address is automatically incremented each time data is written/read.)Load/store bufferA - Sets the operation mode. (Coding/decoding, image data through, and load/store of line memory) - Selects read-through of head coding data in decoding (0 ~ 3 bytes). - Selects the typical prediction function. - Selects prohibition of line memory initialization. Operation mode settingB - Sets the terminal marker code in encoding (SDNORM/SDRST)Marker code settingC C Marker code reading R - Reads a marker code in decoding. (SDNORM, SDRST, ABORT, others) - Context table RAM initializing processing command - Start/stop command (Coding/decoding, image data through, load/store of the line memory) - Start/stop command of load/store of context table RAM - Selects temporary stop/termination end mode.

2 Command W

• Processing status (in process/end of process) - Ready for reading/writing coding (image) data on code data bus - Detects marker code (SDNORM, SDRST, ABORT, etc.). - Interrupt request status - SC counter overflow error - Processing mode (temporary stop/end of termination)

2 Status R

• Scale down in coding (1/2 scale-down of horizontal and vertical, horizontal OR processing) - Scale-up at time of decoding (scale-up of horizontal and vertical by twice) W/R W/R W/R W

MITSUBISHI SEMICONDUCTOR (LSI) 2. Description on Register (1) System setting register (W/R) (Address: 0) d0 (HR): H/W reset (0: Active status, 1: Reset status) To reset H/W, set this bit to 1 then to 0. The entire LSI including register group and line memory is initialized by writing in this reset. However, context table RAM is not initialized. d1-2 (CB): Selects the bit width of code data bus (d2 = 0, d1 = 0: 8-bit bus (CD0-7), d2 = 0, d1 = 1: 16-bit bus (CD0-15), d2 = 1, d1 = 0: 32-bit bus (CD0-31)) (Note1)Prohibition of setting for d2 = 1, d1 = 1 (Note2)For encoding in 16-/32-bit bus, the last encoding data is output followed by bit byte of '00' (3 bytes maximum) for word alignment of encoding data at the end. d3 (DS): Selects data bit swap of image data bus (0: MSB first, 1: LSB first) See Table 3. SYS_REG: PB PI BX BS DS CB HR d7(MSB) d0(LSB) d4 (BS): Selection of data bit swap of code data bus (0: MSB first, 1: LSB first) See Table 2. d5 (BX): Selection of data byte swap of code data bus (0: low order byte first, 1: high order byte first) See Table 2. (Note) BX is effective only when the host bus selects 16-bit/32-bit bus. d6 (PI): Selection of image data input/output I/F (0: serial I/F, 1: parallel IF) d7 (PB): Selection of bit width of image data bus (0: 32-bit bus (PD0-31), 1: 16-bit bus (PD0-15) See Table 3. Note) PB and DS are effective only when PI = 1. (Note) b0 is image data, given in time series, on the left side of the first encoding data/screen. b31 is image data, given in time series, on the right side of the last encoding data/screen. Table 2 Line up of Coded Data/Image Data in Code Data Bus Bus width (CB) Swap (BX, BS) (16-bits) (8-bits) b8 • • b15 b15 • • b8 b0 • • b7 b7 • • b0 b0 • • b7 b7 • • b0 b8 • • b15 b15 • • b8 b0 • • b7 b7 • • b0 CD31 • • CD24 CD23 • • CD16 CD15 • • CD8 CD7 • • CD0 1(32-bits) b8 • • b15 b15 • • b8 b16 • • b23 b23 • • b16 b0 • • b7 b7 • • b0 b24 • • b31 b31 • • b24 b24 • • b31 b31 • • b24 b0 • • b7 b7 • • b0 b16 • • b23 b23 • • b16 b8 • • b15 b15 • • b8 Order of data in code data bus (CD) d2 d1 d5 d4 Bit width PB=0 PB=1 p0 • • • • p15 p31 • • • • p16 p16 • • • • p31 p15 • • • • p0 Table 3 Order of Image Data on Image Data Parallel Bus p0 is image data on the left side of the screen. p31 is image data on the right side of the screen. Swap DS=0 DS=1 DS=0 DS=1 (2) Parameter setting register (W/R) (Address: 1) d0-4 (AT<0>-AT<4>): Low order 5-bits of AT pixel position (See Figure 2.) d5 (TM): Selection of template (0: 3-line template, 1: 2-line template) d6-7 (AT<5>-AT<6>):High-order 2-bits of AT pixel position (6th/7th bit) (Example) 3-line template, AT = 4 2-line template, AT = 48 (Note) AT pixel position is set (0 to 127) with AT <6:0>. At the default position (AT pixel is not used), set AT = 0. The 2-line template, prohibits AT = 1 to 4 from being set. The 3- line template prohibits AT = 1 to 2 from being set. AT TM AT PARA_REG : d7 d4 d0d5d6 p0 • • • • p15 p15 • • • • p0 d7 d4 d0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0

MITSUBISHI SEMICONDUCTOR (LSI) (3) Command Register (W) (Address: 2) d0 (IC) :Context table RAM initialization start command (1: Start initialization) Setting this bit to 1 starts to initialize context table RAM. When the initialization is completed automatically returns this bit to 0. d1 (JC) :Processing (coding/decoding/through) start/end command (1: Start of processing, 0: End of processing) Setting this bit to 1 starts processing(coding/decoding, image data through and lead/storeof line memory). Before the issuance of this command, concrete operation mode must be set in the operation mode setup register. When the processing for the number of setup lines ends with the end of termination selected this bit automatically returns to 0. (Note)When this JC bit is set to 0 during the coding process (is in progress,) and input of image data is stopped, the coding is stopped (flashed) even if the set lines are not filled. When this bit is set to 0 auring decoding process, and input of encoding data ceases, processing for the number of setup lines is carried out assuming coding data "00" to have been input. In the case of multi-stripe coding, however, process must not be stopped by setting this bit to 0 except for the final stripe. d2 (RC) :Load/store start/end command of context table RAM (1: Start of load/store, 0: End of load/store) Setting this bit to 1 can load context data into context table RAM from outside via a buffer register or can store context data in outside. (See the section for buffer register.) When load/store processing is completed, this bit must be set to 0. d3 (JP) : T em por ar y stop m ode of pr oce ssi ng( c odi ng/ decoding/through)/termination end mode selection (1: Selection of temporary stop, 0: Selection of terminationend) Issuance of processing start command d1 (JC) with this JP bit set to 1 temporarily stops performing the process operation at the completion of processing for the number of setup lines. After that, reissuance of processing start command d1 (JC) restarts processing. (See Section 4.(3).) (4) Status register (R) (Address: 2) d0 (JS) : P r ocessing (initialization/coding/decoding/through) status (0: Processing in progress (temporary stop or initial), 1: Completion of processing) This JS bit is set to 1 in the following cases: when the initialization is complete with the RAM initialization command issued (IC = 1), when all coding data is read completely at time of coding with the start command of termination end processing issued (JC=1, JP=0), and when all image data is read completely at time of image data through and at time of decoding. When the temporary stop processing start command is issued (JC = 1, JP = 1), this JS bit remains to be 0, even if the process for the number of setup lines ends. (However, an interruption occurs at time of temporary stop.) d1 (DS) :Ready for reading/writing coding data (image data case of the through mode) on the code data bus (1: Ready, 0: Read/write disabled) When this bit is set to 1, data can be read/written on the code data bus. (This bit is equivalent to the CDRQ pin.) d2 (MS) :Detects marker code at time of decoding (0: Not detected, 1: Detected) This bit is set to 1 when some marker code is detected at time of decoding. d3 (IS) :Status of interrupt request (INTR pin) (0: Not requested, 1: Requested) d4 (SC) :SC count-overerror at time of coding (0: Normal, 1: Occurrence of SC counter overflow) (Note)The SC counter is a counter for consecutive "FF" data bytes generated in the coding process. Though coding process continues if the SC counter overflows, normal coding data is not output (encoding error). d5 (PS) :Processing (temporary stop/termination end) mode (1: Temporary stop processing mode, 0: Termination end processing mode) This PS bit corresponds to the selection of process temporary stop/termination end of the d3 (JP) bit of command register. (5) Interrupt enable register (W/R) (Address: 3) d0 (JE) : P rocessing (initialization/coding/decoding/through) Temporary stop/termination end interrupt (0: Interrupt mask, 1: Interrupt enable) d1 (DE) :Coding data (image data) read/write ready interrupt (0: Interrupt mask, 1: Interrupt enable) d2 (ME) :Marker code detection interrupt at time of decoding (0: Interrupt mask, 1: Interrupt enable) d3 (SE) :SC count-over error interrupt at time of coding (0: Interrupt mask, 1: Interrupt enable) (Note)Bits d0 to d3 are interrupt enable of bits d0 to d2 and d4 corresponding to the status register. When one of the status bits set to interrupt enable is set to 1, the interrupt request signal (INTR) is asserted (for d0 (JE), an interrupt occurs even at the time of temporary stop). When the status is set to 0 by H/W reset etc., o r when interrupt factor is eliminated by interruption masking, INTR is negated. The status register is not cleared by occurrence of interruption or by R/W of interruption enable register. d7 (MP) :Indication of pause at time of marker code detection (0: Indication of continuation/restart, 1: Indication of temporary pause) If this MP bit is in advance set to 1 in decoding, the decoding temporarily pauses at the time of marker code detected. (When the ME bit is set to 1, an interruption occurs when marker code is detected.) When decoding process is not completed at time of temporary pause of marker detection, the register fo r setting the number of lines can be respecified (See Item (7).) Afterwards, setting this MP bit to 0 restarts the decoding process (the decoding process is carried out for the number of set lines). d7 d0 CMD_REG:

0 JP RC JC IC

STAT_REG : 0 PS SC IS MS DS JS IENB_REG: d7 d0d3 MP 0 SE ME DE JE

(decoded) at time of scale-up (scale-down). multiples of 16 (multiples of 32). lines to be actually coded (decoded).

• When the maximum value (65535) is set before issuance of the processing start command, an arbitrary valuecan be set once in the course of processing.
• When a value except for the maximum value (65535) is set before issuance of the processing start command, and the value requires to be respecified in the course, respecify the maximum value (65535) once and then respecify a desired value. (8) Processing line count register (R) (Address: 8) (Address: 9) d0-7 (LINE_L) :Read out the number of lines actually processed (low byte) (0 to 65535) d0-7 (LINE_H) :Read out the number of lines actually processed (upper byte) The number of processed lines ‡ number of set lines, coding/decoding/through processing stop temporary/end of processing. (Note)The number of lines in this process is cleared to 0 with the processing start command issued. (9) Buffer register (W/R) (Address: A) d0-7 (DWR) :Data for loading/storing context table RAM This register is a buffer for loading data into t h e context table RAM via the host bus or for storing data outside. After issuance of load/store start command of the context table RAM (command register d3 = 1), this register is available to start loading or storing data. Prediction value (MPS) and prediction unmatched probability (LSZ) can be stored in context table RAM for a unit of 1024 contexts in total. Figure 4 and Table 4 provide the address assignment of context table RAM and the data bit array. Since context table RAM is 2-byte data, access is gained alternately in order from low byte to upper byte. Each time two-byte access is gained, the RAM address is automatically incremented (sequential access from address 0). (Note1)Data is not allowed to be loaded and stored at a time. Random access to RAM is not allowed. (Note2)Only 133 types specified by the JBIG international standard (See attached Figure A.2) are allowed to be specified for the LSZ value. (For example, load '5a1d' for initialization.) d7 d0 LSET_REG_L: LSET_REG_H: LSET_L LSET_H LIN_REG_L: LIN_REG_H: d7 d0 LINE_L LINE_H d7 d0 DWR_BUF: DWR

Table 4. Data Bit Array of Context Table RAM Figure 4. Address Assignment of Context Table RAM

(command register d1 (JC) = 1). only in the image data through mode (d1 = 1).

• LIO (d3, d2) = (1, 1) not allowed being set.
• When selection of load/store of image data of line memory, temporary stop (d3 (JP) = 1 of command register) is not allowed to be set.
• When load/store mode of image data is selected, the number of lines to be transferred must be set in the register setting the number of lines.
• The number of lines for image data load to line memory must be 2-line either case of 2-line template or 3-line template. (This is because typical prediction (LNTP) cannot be judged correctly with only a line.) MOD_REG: d7 d0 MODLIOTP LI OB Operation mode (d1, d0) Load/store LIO (d3, d2) Operation mode X , X Coding mode Decoding mode Image data through (image data I/F code data I/F) Image data through (code data I/F image data I/F) Image data load to line memory (Input from image data I/F) Image data load to line memory (input from code data I/F) Image data store of line memory (output to code data I/F) Image data store of line memory (output to image data I/F)

Table 5. Operation Mode List to be read through (not used for decoding process). boundary, this function is used. coding data as the end marker during coding.

Table 6. Initial Values of Registers written value is set in the system setting register.

MITSUBISHI SEMICONDUCTOR (LSI) To 2) SYS_REG: d7 d0 ;H/W reset bit ON0 0 0 0 0 0 0 1 ;H/W reset bit OFF ;Initializes context table RAM ;Process end interrupt enable CMD_REG: IENB_REG: Context table RAM is initialized (0 clear) in this period. The number of clocks required for initialization is as follows: 1024 +a[Clock] (Occurrence of interrupt) Set interrupt disable ;Interrupt disable N Y (Error) ;j = End of processing ;End of initialization SYS_REG: Issue context table RAM initialization command Set interrupt enable – – – – – – – jSTAT_REGRead out status register (check the end of processing) End of initialization command j = 1 ? d7 d0 CMD_REG: IENB_REG: * Period of H/W reset bit set to ON (time from when d0 = "1" is written until d0 = "0" is written) requires 100 ns or more. (Note) Line memory is initialized by H/W reset to prepare the all white (0) data as a reference line to provide for the start of coding/decoding process and to initialize LNTP bit (LNTP = 1) for typical prediction. 4. Register Setting Sequence (1) Initialization sequence of built-in line memory and context table RAM This sequence is used to carry out initialization sequence (0 clear) of context table RAM after the initialization (Note) of the built-in line memory by H/W reset. When the initialization is unnecessary (the contents of the current status table are directly used), this sequence is unnecessary. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H/W reset, context mode set up

MITSUBISHI SEMICONDUCTOR (LSI) (2) Stripe coding/decoding (without change in AT pixel position)/image data through processing sequence SYS_REG: d7 d0 Pb Pi Bx Bs 0 Cb Cb 0 ;Process end interrupt enable CMD_REG: IENB_REG: [Performs coding/decoding processing during this period.]---Inputs/outputs image data and coding data. (Coding/decoding/through processing for a stripe) PARA_REG:Set Parameter (Template, context) Set the number of pixels Set System (Set LSI mode) PEL_REG_L : PEL_REG_H: Set the number of lines Set marker code ((Note)Re quired coding only) Set scale-up/scale-down Processing start command (Coding/decoding/through) Set interrupt enable LSET_REG_L : LSET_REG_H: MSET_REG: CONV_REG: ;aa,aaaaa = AT pixel position ;t = Template selection ;pel_l, pel_h =Number of pixels per 1 line ;lset_l, lset_h =Number of processing lines mset = sets marker code byte (SDNORM = 02h, SDRST = 03h) ;Ve, He = Selection of scale-up during decoding ;Vr, Hr, Ho = Selection of scale-down at time of coding ;Termination end processing (coding/decoding/through) Start command a a t a a a a a pel_l 0 0 lset_l lset_h mset 0 0 0 0 0 0 1 0 pel_h (Note) Set Li = 0 for the head stripe of single stripe or multi-stripe. 0 0 0 HoHrVrHeVe ;mm = operation mode (coding/decoding/through) ;Ob, Ob = Selection of head byte read-through during decoding (0-3) ;Li = Selection of inhibition of line memory initialization (Note) ;Tp = Typical prediction function ON/OFF MOD_REG: Set Operation mode Tp Li ObOb 0 0 m m ;Cb, Cb = Bit width of code data bus ;Bs, Bx = Code data bus bit, byte swap ;Pb, Pi = Bit width of image data bus, I/F selection (Occurrence of interrupt) Set interrupt disable ;Interrupt disable N Y (Error) ;mdet = Read marker code STAT_REG:Read out status register (Check process for end.) j = 1 ? d7 d0 MDET_REG: IENB_REG: mdet End N (Marker not detected) (Error) (Decoding) N (Coding) Y Decoding? End (Marker detection)Y Read marker code ((Note) At time of decoding only) ;j = End of processing ;m = Marker detection ;s = SC counter over error (Error) N (SC counter over) Y 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 m = 1 ? s = 0 ?

MITSUBISHI SEMICONDUCTOR (LSI) (3) Stripe encoding/decoding (with change in AT pixel position) processing sequence ;Process end interrupt enable CMD_REG: IENB_REG: [Performs coding/decoding processing during this period.]---Input/output first image data and coding data. d7 d0 Processing start command (Temporary stop processing) Set interrupt enable ;Temporary stop processing (coding/decoding) Start command 0 0 0 0 1 0 1 0 Set the number of lines LSET_REG_L : LSET_REG_H: ;lset_l,lset_h = Number of processing lines (Note) Set the number of processing lines ranging from processing restart to change of AT pixel position lset_l lset_h ;Process stop interrupt enable CMD_REG: IENB_REG:Set interrupt enable ;Temporary stop processing (encoding/decoding) Start command [Performs encoding/decoding process during this period.]---Inputs/outputs image data and coding data in the course. Repeat this routine (for the number of ATmoves - 1) j=0, p=1; Temporary stop status Set interrupt disable ;Interrupt disableIENB_REG: Read status register ;Set change of AT pixel (a'a',a'a'a'a'a') (Note) Template is not allowed to be changed. Set AT pixel position PARA_REG: a' a' t' a' a' a' a' a' (Occurrence of interruption) (Note) At time of coding in the first processing, (number of lines of input image data) = (value set in the line count set register) +1. During decoding, (number of lines in output image data) = (value set in the line set register) - 1 (Note) During encoding in the course of processing, (number of lines in input image data) = (value set in the line count set register). At time of decoding, (number of lines in output image data) = (value set in the line count set register). Set final AT Final set Set in the course ;Status check Processing start command (Temporary stop processing) SYS_REG: d7 d0 Pb Pi Bx Bs 0 Cb Cb 0 PARA_REG: Set Parameter (Template, context) Set the number of pixels Set System (Set LSI mode) PEL_REG_L : PEL_REG_H: Set the number of lines Set marker code ((Note) Re quired coding only) Set scale-up/scale-down LSET_REG_L : LSET_REG_H: MSET_REG: CONV_REG: ;Cb, Cb = Bit width of code data bus ;Bs, Bx = Code data bus bit, byte swap ;Pb, Pi = Bit width of image data bus, I/F selection ;aa,aaaaa = AT pixel position ;t = Template selection ;pel_l, pel_h = Number of pixels per 1 line ;lset_l, lset_h = Number of processing lines (Note) Set the number of processing lines to position change of AT pixel. mset = sets marker code byte (SDNORM = 02h, SDRST = 03h) ;Ve, He = Selection of scale-up at time of decoding ;Vr, Hr, Ho = Selection of scale-down at time of coding a a t a a a a a pel_l 0 0 lset_l lset_h mset pel_h (Note) Set Li = 0 for single stripe or the head stripe of multi-stripe. 0 0 0 HoHrVrHeVe ;m = operation mode (encoding/decoding) ;Ob, Ob = Selection of head byte read-through during decoding (0-3) ;Li = Selection of inhibition of line memory initialization (Note) ;Tp = Typical prediction function ON/OFF MOD_REG:Set Operation mode Tp Li Ob Ob 0 0 0 m 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1

MITSUBISHI SEMICONDUCTOR (LSI) (Occurrence of interrupt) Set interrupt disable ;Interrupt disable N Y (Error) ;j = End of processing ;m = Marker detection ;s = SC counter over error ;mdet = Read marker code – – – s – m – jSTAT_REG:Read out status register (Check end of processing.) j = 1 ? d7 d0 MDET_REG: IENB_REG: mdet End N(Marker not detected) (Error) (Decoding) N(Encoding) Y Decoding? End (Marker detection)Y Read out marker code ((Note) Decoding only) s = 0 ? (Error) N (SC counter over) Y [Performs coding/decoding processing during this period.] --- Inputs/outputs final image data and coding data. Set number of lines LSET_REG_L : LSET_REG_H: ;lset_l,lset_h = Number of processing lines (Note) Enter the number of processing lines ranging from restart of processing to the final line. lset_l lset_h ;Process stop interrupt enable CMD_REG: IENB_REG: Processing start command (Termination end processing) Set interrupt enable ;Termination end processing (coding/decoding) Start command 0 0 0 0 0 0 1 0 ;Set change in final AT pixel. (Note) Template is not allowed to be changed. SET AT pixel position PARA_REG: a" a" t a" a" a" a" a" (Note) During coding in the final processing, (number of lines in input image data) = (value set in the line count set register) – 1. During decoding, (number of lines in output image data) = (value set in the line count set register) + 1. (4) Load/store processing sequence of the context table RAM This sequence is used to load or store context table RAM. d7 d0 [Stores (loads) the context table RAM during this period. Context RAM data is stored (loaded) via buffer register. Reading (writing) 2 bytes automatically increments the RAM address. (Note) Reading (storing) operation and writing (loading) operation are not allowed to be done at a time. CMD_REG:RAM load/store start command 000000100CMD_REG: ;End of loading/storing RAM Since the operation does not automatically stop, be sure to write the load/store end command. 00000000 ;Starts to load/store context table RAM End of RAM load/store command 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 m = 1 ?

MITSUBISHI SEMICONDUCTOR (LSI) (5) Load/store processing sequence of line memory image data ;Process end interrupt enable CMD_REG: IENB_REG: [Performs loading/storing process during this period] --- Inputs (outputs) image data. (Transfer processing of image data for 2 lines) PARA_REG:Set Parameter (Selection of template) Set number of pixels Set System (Set LSI mode) PEL_REG_L : PEL_REG_H: Set number of lines (= 2) Set scale-up/scale down Processing start command (Load/store into line memory) Set interrupt enable LSET_REG_L : LSET_REG_H: CONV_REG: ;t = Selection of template ;pel_l, pel_h = Number of pixels per line lset_l, lset_h = 2 (Number of processed lines) (Note 2) ;Ve, He = Selection of scale-up during decoding ;Vr, Hr, Ho = Selection of scale-down during coding ;Load/store processing start command of image data pel_l 0 0 lset_l lset_h 0 0 0 0 0 0 1 0 pel_h * 0 0 0 HoHrVrHeVe *Settings of template selection, number of pixels per line, selection of scale-up/scale-down and typical prediction function must meet the settings at time of stripe coding/decoding to be carried out after this. SYS_REG: d7 d0 Pb Pi Bx Bs Ds Cb Cb 0 ;m = Operation mode (selection of through mode) ;Lio, Lio = 01 or 10 (selection of load or store) ;Li = 1 (selection of prohibition of line memory initialization) ;Tp = Typical prediction function ON/OFF (Note 1) MOD_REG:Set Operation mode Tp Li 0 0 LioLio 1 m ;Cb, Cb = Bit width of code data bus ;Ds = Bit swap of image data bus ;Bs, Bx = Code data bus bit, byte swap ;Pb, Pi = Bit width of image data bus, I/F selection (Occurrence of interrupt) Set interruption disable 0 0 0 0 0 0 0 0 ;Interrupt disable N Y (Error) STAT_REG:Read out status register (Check end of processing.) j = 1 ? d7 d0 IENB_REG: End ;j = End of processing– – – – – – – j Note 1) For ON/OFF bit of TP function in the image data processing, the ON/OFF bit of the TP function just before coding/decoding shall be kept. Note 2) In the image data load/store processing, be sure to set the number of transfer lines to "2". (The 1st line is data on the line (final line - 1) of the stripe. The 2nd line is data on the last line of stripe.) When a line stripe is adopted for the first stripe of the page in the image data store processing, and read out line of the first line is outside data of stripe, the all white data must used for replacement or the image data load function must be used in advance to clear line memory. Final line (Final line - 1) line 2nd line 1st line Stripe Head line 0 0 0 0 0 0 0 1

MITSUBISHI SEMICONDUCTOR (LSI) (6) Total sequence of multi-stripe coding/decoding For an image with a page consisting of more than one stripe or (Description) If the end marker of the previous stripe is SDRST, the status must be initialized for coding/decoding the next stripe. Start to carry out the process of next stripe by returning the AT pixel position to the default position after the initialization of built-in line memory and context table RAM. [case 1] If the termination marker of the previous stripe is SDNORM, the status of the previous stripe must be taken over for coding/decoding the next stripe. If the stripe of the same plane is continuously coded/decoded, the AT pixel position takes over the final value of the previous stripe and the process of the next stripe is to start without initializing line (Note 1) Since use of the host bus with 32/16-bit bus during coding adopts word boundary, the end marker code may be followed by the pad bytes ('00') of 1 to 3-byte. These pad bytes must be removed outside. (See Section 2. (7).) (Note 2) When decoding of stripes starts at time of decoding, the head coding data of SDE (stripe data entity) must be first entered. Read-through of head byte is indicated, if necessary. (At time of end of decoding stripes, the head block of coding data may be entered into LSI (FIFO) or may not be arranged in the word boundary. Management is therefore required outside.) (Note 3) The process of inter-stripe marker codes (ATMOVE, NEWLEN, etc.) (insert at time of coding and detection/removal at time of decoding) must be carried out outside. Initialization of built-in memory and context table RAM [Process (1)] 1st stripe coding/decoding processing [process (2) or (3)] Is previous stripe SDNORM? Y (SDRST) End of processing of all stripes? Y N End of page Stripe coding/decoding processing (Indication of line memory initialization: Li = 0, AT pixel = Default position (0)) [Process (2) or (3)] (SDNORM) Multi-stripe coding/decoding Stripe coding/decoding processing (Prohibition of line memory initialization: Li = 1, AT pixel = Previous stripe taken over) [Process (2) or (3)] Repetition of this routine (for the number of stripes - 1) Initialization of line memory and context table RAM [Process (1)] N Stripe coding/decoding processing (Prohibition of line memory initialization: Li = 1, AT pixel = Respecify) [Process (2) or (3)] Loading of image data of line memory, and loading of context table RAM [Processes (4) and (5)] Does the same plane stripe continue? Y(Same plane) N (Difference plane) Storing of image data of line memory and storing of context table RAM [Processes (4) and (5)] [case1] [case2] [case3]

• Single plane, multi-stripe 1 23 4
• Multiple planes and multi-stripe Stripe (Processes in numeric order) Plane 1 Plane 2 Plane 3 (Example) Plane memory and context table RAM to use the status of line memory and context table RAM at the end of previous stripe for the next stripe. [case 2] On the other hand, since the status at the end of pre-stripe status of the same plane must be respecified for the status of line memory and context table RAM, line memory and context table RAM are to be loaded into LSI to respecify the AT pixel position and to start processing the next stripe when alternately coding/decoding stripes of different planes. After coding/decoding of stripe, save line memory and context table RAM for next stripe. [case 3] plane, coding or decoding process must be carried out in units of stripe after initialization.

MITSUBISHI SEMICONDUCTOR (LSI) Timing Chart 1. Host bus I/F CS* RD* WR* Read access Write access 2. Code data I/F (a) For 8-bit bus CDRQ CDAK* CDRD*/CDWR* (Description) CDRQ can be checked for being asserted (H) to assert (L) CDAK*. Asserting (L) CDAK* negates (L) CDRQ. Asserting (L) section of CDRD*/CDWR* must be included in the CDAK* asserting section (L). CDRQ CDAK* CDRD*/CDWR* CD0-15 (b) For 16-bit bus (Note) For 16-bit bus, only the word access (CD0-15) is allowed. CDRQ CDAK* CDRD*/CDWR* CD0-31 (c) For 32-bit bus (Note) For 32-bit bus, only the long word access (CD0-31) is allowed. A0-3 D0-7 CD0-7

MITSUBISHI SEMICONDUCTOR (LSI) 3. Image Data I/F (1) Serial image data I/F PRDY* PTIM* PXCK* PXCKO* SVID*/RVID* (b) 32-bit bus (2) Parallel image data I/F (a) 16-bit bus (Note) The above chart shows a timing for a line (N pixel/line). 1 234 5N (Description) PRDY* can be checked for being asserted (L) to assert (L) PTIM*. Asserting (L) PTIM* negates (H) PRDY*. PXCKO* is an output of having gated PXCK* input with PTIM*. The image data (SVID*/RVID*) is input/output in synchronization with PXCK* or PXCKO*. (Description) PDRQ can be checked for being asserted (H) to assert (L) PDAK*. Asserting (L) PDAK* negates (H) PDRQ. Asserting (L) section of PDRD*/PDWR* must be included in the asserting section (L) of PDAK*. PDRQ PDAK* PDRD* /PDWR* PDRQ PDAK* PDRD* /PDWR* (Note) For 16-bit bus, only the word access (PD0-15) is allowed. (Note) For 32-bit bus, only the long word access (PD0-31) is allowed. PD0-31 PD0-15

MITSUBISHI SEMICONDUCTOR (LSI) [Appendix A.1] JBIG Data Structure B I E ;Bi-level Image Entity B I H ;Bi-level Image Header D L D P X D YD LD M X M Y Order ;lowest resolution layer ;finel resolution layer ;number of bit-planes ;dummy 0 ;horizontal dimmension at highest resolution ;vertical dimmension at highest resolution ;number of lines per stripe at lowest resolution ;maximum horizontal offsets allowed for AT pixel ;maximum vertical offsets allowed for AT pixel ;order byte b7-4;dummy 0 b3 ;resolution-order distinction b2 ;progressive-versus-seqential distinction b1 ;interleaving of multiple bit-planes b0 ;indexed over stripe is in middle Options 1 ;option byte b7 ;dummy 0 b6 ;lowest resolution-layer two line template b5 ;NEWLEN(new vertical dimmension)marker enable b4 ;differential-layer TP enable b3 ;lowest-resolution-layer TP enable b2 ;DP enable b1 ;private DP table b0 ;DP table last is to be reused (it is present only if DPON=1, DPPRIV=1, DPLAST=0) B I D ;bi-level Image Data(( ) x N) ESC ATMOVE Y AT t X t Y ;FFh ;06h ;line in which an AT switch is to be made ;holizontal offset of the AT pixel ;vertical offset of the AT pixel Flloating Marker Segments( a ~ c ) a AT move marker ESC NEWLEN Y D ;FFh ;05h ;new Y D ESC COMMENT L C comment L C ;FFh ;07h ;length in bytes of private comment ;contents of comment SDE ;Stripe Data Entry (Within the frame: LSI support range) abort BID marker ESC ABORT ;FFh ;04h ESC RESERVE ;FFh ;01h b new-length marker c comment marker reserved marker PSCD ;Protected Stripe Coded Data =byte stuffed SCD(Stripe Code Data) ;FFh ;normal terminate(02h) ;/reset "state" for next SDE(03h) ESC SDNORM/SDRST HITOLO SEQ ILEAVE SMID DPTABLE 0/1728 ;private DP table LRLTWO VLENGTH TPDON TPBON DPON DPPRIV DPLAST

MITSUBISHI SEMICONDUCTOR (LSI) [Appendix A.2] JBIG Probability Estimation Table ST LSZ NLPS NMPS SWTCH ST LSZ NLPS NMPS SWTCH 100 101 102 103 104 105 106 107 108 109 110 111 112 101 102 103 104 105 106 107 103 105 108 109 110 111 110 112 112 100 102 103 104 106 107 103 109 107 111 109 111 0x5ald 0x2586 0x1114 0x080b 0x03d8 0x01da 0x00e5 0x006f 0x0036 0x001a 0x000d 0x0006 0x0003 0x0001 0x5a7f 0x3f25 0x2cf2 0x207c 0x17b9 0x1182 0x0cef 0x09a1 0x072f 0x055c 0x0406 0x0303 0x0240 0x01b1 0x0144 0x00f5 0x00b7 0x008a 0x0068 0x004e 0x003b 0x002c 0x5ae1 0x484c 0x3a0d 0x2ef1 0x261f 0x1f33 0x19a8 0x1518 0x1177 0x0e74 0x0bfb 0x09f8 0x0861 0x0706 0x05cd 0x04de 0x040f 0x0363 0x02d4 0x025c 0x01f8 0x01a4 0x0160 0x0125 0x00f6 0x00cb 0x00ab 0x008f 0x5b12 0x4d04 0x412c 0x37d8 0x2fe8 0x293c 0x2379 0x1edf 0x1aa9 0x174e 0x1424 0x119c 0x0f6b 0x0d51 0x0bb6 0x0a40 0x5832 0x4d1c 0x438e 0x3bdd 0x34ee 0x2eae 0x299a 0x2516 0x5570 0x4ca9 0x44d9 0x3e22 0x3824 0x32b4 0x2e17 0x56a8 0x4f46 0x47e5 0x41cf 0x3c3d 0x375e 0x5231 0x4c0f 0x4639 0x415e 0x5627 0x50e7 0x4b85 0x5597 0x504f 0x5a10 0x5522 0x59eb

MITSUBISHI SEMICONDUCTOR (LSI) 1. Host bus I/F RESET* [Appendix B] Timing Characteristics Conditions:VDD =5V –5% C=50pF Ta=0-70°C t1 t2 t3 t5 t6 t7 t11 t12 t13 t15 t16 t17 Output Input t14 2. Code data I/F CDRQ t20 t21 t22 t26 t27 t31 t32 t36 t37 Output Input t24 t34 A0-3 CDAK* CDRD* CD0-31 CDWR* CS* RD* WR* D0-7

MITSUBISHI SEMICONDUCTOR (LSI) Table B. 1 Host Bus I/F Timing Characteristics (Unit: ns) t11 t12 t13 t14 t15 t16 t17 RESET* assert time CS* setup time to RD* assert CS* hold time to RD* negate A0-3 setup time to RD* assert RD* assert time A0-3 hold time to RD* negate D0-7 output determination time to RD* assert D0-7 output hold time to RD* negate CS* setup time to WR* assert CS* hold time to WR* negate A0-3 setup time to WR* assert WR* assert time A0-3 hold time to WR* negate D0-7 input setup time to WR* negate D0-7 input hold time to WR* negate 100 Table B. 2 Timing Characteristics of Code Data Bus I/F t20 t21 t22 t24 t26 t27 t31 t32 t34 t36 t37 CDRQ negate time to CDAK* assert CDAK* setup time to CDRD* assert CDAK* hold time to CDRD* negate CDRD* assert time CD0-31 output determination time to CDRD* assert CD0-31 output hold time to CDRD* negate CDAK* setup time to CDWR* assert CDAK* hold time to CDWR* negate CDWR* assert time CD0-31 input setup time to CDWR* negate CD0-31 input hold time to CDWR* negate Timing conditions Min Typ Max ParameterAbbreviation Timing conditionsParameterAbbreviation Min Typ Max

MITSUBISHI SEMICONDUCTOR (LSI) t50 t45 3. Image data I/F (1) Serial image data I/F (2) Parallel image data I/F PRDY* PDRQ t40 t41 t46 t56 t47 t43 t44 N t48 t42 t57 t60 t61 t62 t66 t67 t71 t72 t77 InputOutput t64 t74 t76 t49 t51 4. Master clock input frequency (LSI operating frequency) MCLK Mx Mh Ml PTIM* PXCK* PXCKO* RVID* SVID* PDAK* PDRD* PDWR* PD0-31

MITSUBISHI SEMICONDUCTOR (LSI) Table B. 3 Timing Characteristics of Image Data I/F (Unit: ns) t40 t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t56 t57 t60 t61 t62 t64 t66 t67 t71 t72 t74 t76 t77 PRDY* negate time to PTIM* assert PTIM* setup time to PXCK* fall PTIM* hold time to PXCK* rise PXCK* high time PXCK* low time PXCK* cycle RVID* output determination time to PXCK* fall RVID* output change time to PXCK* fall RVID* negate time to PTIM* negate PXCKO* delay time to PXCK* RVID* output determination time to PXCKO* fall RVID* output change time to PXCKO* fall SVID* setup time to PXCK* rise SVID* hold time to PXCK* rise PDRQ negate time to PDAK* assert PDAK* setup time to PDRD* assert PDAK* hold time to PDRD* negate PDRD* assert time PD0-31 output determination time to PDRD* assert PD0-31 output hold time to PDRD* negate PDAK* setup time to PDWR* assert PDAK* hold time to PDWR* negate PDWR* assert time PD0-31 input setup time to PDWR* negate PD0-31 input hold time to PDWR* negate Table B. 4 Master Clock Frequencies (Unit: ns) MCLK cycle (Mx) MCLK high level time (Mh) MCLK low level time (Ml) Max frequency 40MHz Parameter Timing conditions Timing conditionsParameterAbbreviation Min Typ Max Min Typ Max