M65761FP MITSUBISHI | Alldatasheet
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MITSUBISHI ICs (LSI) SPECIFICATION OF INTEGRATED CIRCUIT 1. TYPE NO. 2. FUNCTION 3. APPLICATION 4. OUTLINE
4.1 PACKAGE
4.2 OUTLINE DRAWING
2.1 CIRCUIT FUNCTION
2.2 BLOCK DIAGRAM
FAX, PPC etc
100 Pin Plastic Molded Quad Flat Package (Fine Pitch)
[100P6S-A] 5. CIRCUIT DIAGRAM DRAWING 6. PIN DIAGRAM G465181 see cover page of specification QM-Coder 7. OTHER SPECIFICATIONS see the next page (2page) see the third page
MITSUBISHI ICs (LSI) PIN CONFIGURATION (TOP VIEW ) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 M65761FP GND PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 V CC GND PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 V CC PD21 GND PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PDRQ V CC GND PDRD PDWR PDAK RVID PRDY SVID PTIM PXCK XWAIT VCC PD31 GND V CC GND V CC CS MCLK GND V CC WR RD BUS16 DMAAK DMARQ INTR XCLK GND VCC TEST0 TEST1 TOUT1 TOUT2 V CC D15 D14 D13 D12 GND V CC D11 D10 GND V CC GND Outline 100P6S-A PXCKO RESET BHE
MITSUBISHI ICs (LSI) BLOCK DIAGRAM D15 DMARQ DMAAK INTR BUS16 MCLK TEST1 TEST0 PIXEL DATA VCC GND TOUT1,2 Leave TOUT1 and TOUT2 open. PD 0 PD10 PD11 PD21 RESET CS BHE WR RD D12 D11 PD0-11=CX0-11 PD15=PEUPE HOST BUS I/F CONTEXT TABLE RAM LINE MEMORY IMAGE DATA • CONTEXT I/F CONTEXT DATA TABLE RAM PROBABILITY ESTIMATION SWITCH CONTEXT GENERATION TYPICAL PREDICTION –– – – 96 979414 27 40 51 60 70 76 82 881 QM-CODER 13 26 39 50 59 69 75 81 87 93 100 PD22 PD31 PDRQ PDAK PDRD PDWR PRDY (=XRDY) PTIM (=XTIM) PXCK PXCKO SVID (=SPIX) RVID (=RPIX) XCLK XWAIT
MITSUBISHI ICs (LSI) (1) Coding Algorithm
- QM-Coder (JBIG Standard Arithmetic Coding System) (2) Context (i) Built-in Context Mode a) Template Model
- 2 or 3 line 10 pixel template (See Fig9. 1) (This agrees with the template used with the minimum resolution of JBIG) NOTE:The coding efficiency of the 3-line template is better than that of the 2-line template by several %. b) Adaptive Template (AT)
- It is possible to move up to 127pixcels on the coding line. (The position of ATgiven instruction by the MPU) Note:It is possible to improve the coding effeciency against the dither image by the use of AT.
- It is posible to change the position of AT line by line in the middle of coding and decoding. Note:It is not possible to change the template at the time when change the position of the AT pixels. (ii) Extenal Context Mode
- It is possible to input any context up to 12 bits. (It is possible to interface with JBIG Progressive Coding and the Arithmatic Coding of JPEG Option Function) (3) Typical Prediction
- Agreement with the Typical Prediction of the lowest resolution of JBIG. The pseudo-pixcel (SLNTP) is geneated by the symbol LNTPwhich shows whether the coding/decoding process agree with the directly before line.If they agree, the line is not coding/decoding . This makes it possible to shorten the time of process and rejection of the code data. SLNTPy =! ( LNTPy + LNTPy-1 ) (y:line number, LNTPy=1; LNTPy-1=1) (4) Deterministic Prediction
- This LSI is not equipped with the Typical Prediction.However,the DP function is realized when the DP pixels are identified and eliminated by the extenal circuits during the external context mode. (5) Coding Data Format
- The Stripe Data Entity (SDE) (=Stripe coded data with byte stuffing (PSCD) + end marker (SDNORM/ SDRST)) Coding/decoding of one stripe portion os perfformed.In case of the multi-striped (construct the multi stripes) stripes are activated one at a time. (6) Marker Code
- The SDE end marker is supported.(SDNORM=02h, SDRST=03h, ABORT=04h) (During coding the marker code previously set in the register is outputted.During decoding ,the marker code detected by requesting an interrupt to MPU when the marker is detected is read out od register.) (7) Rough Estimate of Coding and Decoding Time(T1:M65761FP as a whole,T2;Processing Time of the arithmetic coding section alone)
- The total number of clocks needed for coding and decoding 1 page (stripe)is calculates roughly using the following equations. - S * ((1 - b) * p * Ltp - Lp) [clock] - S * ((p * Ltp) - Lp)) [clock] 9. CODING SPECIFICATION Fig. 9. 1 Template (X, A) (Top : 3line, Bottom : 2line) Fig. 9. 2 Adaptive template (A) p : Number of pixcels/line b : about 0.3 Lp : Number of lines/page Ltp : Number of TP line /page C : Number of coded data bits/page S= 1: TP exists 0: No TP a : about 10 MAX127 MAX127 X?X XXX X XX X A X?X XXX A X X X X XXX XXXXX A XX XXXX A XXX X
MITSUBISHI ICs (LSI) 10. FUNCTIONAL DESCRIPTION OF PINS Classification Pin name I/O Function Host Bus I/F RESET CS A0-3 BHE WR RD D0-15 DMARQ DMAAK INTR BUS16 PD0-31 PDRQ PDAK PDRD PDWR PRDY PTIM PXCK PXCKO SVID RVID CX0-11 PEUPE SPIX RPIX XCLK XWAIT XRDY XTIM MCLK TEST0-1 Vcc/GND I I I I I I IO O I O I IO O I I I O I I O I O I I I O O I O I I I H/W reset signal Chip select signal Internal register address select signal High-order(D8-15)access signal Write strobe signal Read strobe signal I/O data signal (D0-7 used on 8-bit bus) Code data DMA request signal Code data DMA acknowledge signal Interrupt request signal 8-bit bus (D0-7)and 16-bit bus(D0-15)function select bus. Parallel image I/O bus (PD0-15 used on 16-bit bus) Image data DMA request signal Image data DMA acknowledge signal Image data read strobe signal Image data write strobe signal Image data 1-line I/O start ready signal Image data 1-line transfer section signal Image data transfer clock signal Image data transfer sync clock signal Image data input signal Image data output signal Context input (CX0 can be fed back inside LSI) (=PD0-11) PE RAM update enable (learning function ON/OFF) (=PD15) Coded image data input signal (=SVID) Decoded image data output signal (=RVID) Context data transfer clock signal Context data transfer wait signal Context data 1-stripe I/O start ready signal (=PRDY) Context data 1-stripe transfer section signal (=PTIM) Master clock input signal Test signal (should be connected to GND when normally used). Power supply (+5V)/ground Image data I/F Parallel Serial Context I/F Others BUF S S S US U US US US US US U U U U US US DS Notes:Most of the context I/F signals are used in conjunction with the image data I/F signals. * The input buffers of the input terminals (I and IO) are at TTL level. Options are as follows. (U:with pull-up resistors,D:with pull-down resistors,S:Schmitt trigger) * Numbers (2,4,8) of the BUF column of the output terminals (O and IO) indicate current value. (one of 2,4,or 8mA)
MITSUBISHI ICs (LSI) 11. REGISTER CONFIGURATION 11. 1 List of registers Address Register Name R/W Description
- LSI H/W reset
- Coding/decoding/image data through mode selection
- Context selection(internal context/external context)
- Byte swap ON/OFF of coded/image data on host bus
- Bit swap ON/OFF of coded/image data on host bus
- Image data I/O I/F(parallel I/F,serial I/F)
- Image data bus bit width selection(32bits/16bits)
- Template selection (2-line/3-line template)
- Setting of AT pixel position (up to 127)(IF O is set,AT becomes non-existent (default position))
- Latch input/through input selection in external context input mode
- Context table RAM initialization command
- Coding (decoding,through) start/end command
- Start/stop command for R/W of context table RAM
- Selection of temporary stop and terminating end
- Processing status (in process/end of processing)
- Coded data read/write ready (ready/busy)
- Marker code detection (SDNORM,SDRST,ABORT,others)
- Interrupt request status
- SC counter over flow
- Processing mode (stop temporary/terminating end)
- Interrupt enable setting correspondence to each of bits positions of status register
- Setting the number of pixels on one line (in multiples of 16or32,up to 10240 pixels)
- Setting the number of lines to be coded/decoded(up to 65535 lines)
- Setting the number of coded/decoded lines (up to 65535 lines)
- Buffer for writing coded data/image data/context table RAM data from MPU into LSI (DMA transferable)(RAM address is automatically incremented each time data is written.)
- Buffer for reading coded data/image data/context table RAM data from LSI into MPU (DMA transferable)(RAM address is automatically incremented each time data is read).
- Setting a terminal marker code in coding (SDNORM/SDRST)
- Reading a marker code in decoding (SDNORM,SDRST,ABORT,others)
- Reduction in coding (1/2 reduction in horizontal and vertical directions, horizontal OR processing)
- Magnification during decoding ( · 2 lengthwise and width)
- Select throwing away the leading 1byte of the coded data read when decoding
- Selecting the typical prediction
- Selection of prohibiting line memory initialization Notes:When the 8bit bus is used for the data read/write buffer,use Address A only. Incase of the 16-bit buffer,only the word access is possible. (The byte access is not possible). 4,5 6,7 8,9 A,B A,B C C D System setting Parameter setting Command Status Interrupt enable setting Pixel count setting Line count setting Processed line count Data write buffer Data read buffer Marker code setting Marker code read Scaling R/W R/W W R R/W R/W R/W R W R W R R/W
To make a H/W reset ,set this bit to 1 then to 0. d1-2(MOD) :This sets up the operating modes. NOTE:The internal context should be selected when the image data through mode is used.
- 2 Description of Registers
p0 is the image data on the left-hand on the screen. p31is the image data on the right-hand on the screen. d6 (LC) :Condition of taking in the input from the external context are selected. d7 (C0) : When this bit is set to 1,CX0 is selected. When the default position (when the AT pixels are not used) is used, At is set to 0. Table 11. 2 The coed data and image data line-up on the Host bus Table 11. 3 The image data line-up on the image data parallel bus
MITSUBISHI ICs (LSI) (4) Status Register (R) (address : 2) d0 (JS) :This register indicates the status of processing in initialization,coding,decoding and through. (0:Processing in progress(being initialized),1:End of processing) This JS bit goes to "1"when the initialization is completed as RAM initialization command is issued. (IC=1) This JS bit goes to "1"when all coded data has been read out during coding in case when the process start command of the processing end is issued.(JC=1,JP=0) This JS bit goes to "1" when reading all the image data has been completed during the image data through and decoding. Moreover,this JS bit stays "0" even when the set number of lines have been processed when the command to start processing the process which has been stopped temporarily has been issued (JC=1, JP=1). (However,interrupts are issued during the temporary stops.) d1 (DS) :This is used for read and write ready of coded data.(In case of the through mode,this is used for the image data.)(1:Ready, 0:Reading no possible) It is possible to do R/W of data by the way of the data write/read buffer when this bit is 1. d2 (MS) :This detects the marker code during decoding.(0:not detected, 1:detected) This bit goes to "1" if any marker is detected during decoding. d3 (IS) :This indicates the status of the interrupt request.(0:No request, 1:Request exists) d4(SC) :This shows the SC count over error during coding.(0:Normal, 1:There is a SC counter overflow) NOTE:The SC counter counts the "FF" data bytes which occur duriing coding.Coding continues even when the SC counter overflows.this means correct coding data will not be outputted.(Coding error) d5(PS) :processing modes (Stopped temporary /End of trailer)(1:Process temporaryily stopped, 0:End of processing) This PS bit corresponds to the temporary stop and end of processing of d3 bit (JP) processing of the command register. (3) Command Register (W) (address : 2) d0 (IC) :This command starts initialization of Context Table RAM (1:start initialization) When this bit goes 1,the Context Rable RAM initialization starts.This bit returns to 0 automatically when the initialization is completed. d1 (JC) :Processing (Coding/Decoding/Through) start /end command (1:start processing, 0:end processing) When this bit goes 1,processing(coding/decoding/through)starts. This bit returns to 0 automatically when processing of the number of set lines is finished during the selection of end of termination. And if this JC bit is made 0 and inputting the image data is stopped during the coding porocess,the coding is stopped (flushed) even if the set lines are not filled.Mreover,if this bit made 0 during decoding and no more coded data is coming in,it is assumed that the '00'of the coded data came in and the preset lines have been processed.However,in case of the multi- striped coding ,processing should not end by making this bit "0" except in case of last stripe. d2 (RC) :This command starts and stops R/W of Context Table RAM. (1:R/W start, 0:R/W end) The Context Table RAM is read out or written in by making this bit to "1". When reading/writing is finished,this bit must have "0" on it. d3 (JP) :This selectd temporary stop and the end of termination of coding/decoding/through processing. (1:Temporary stop selected, 0:End of processing selected) When the process start command d1(JC)is issued by making this JP bit to 1,the processing stops temporarily when the set number of lines have been processed. Then, if the process satart command d1(JC) is issued,processing restarts.(See 11.4(3)) STAT_REG : d7 d0
0 PS SC IS MS DS JS
CMD_REG : 0 JP RC JC IC
MITSUBISHI ICs (LSI) (7) Line Number Setting Register (W/R) (Address:6) (Address:7) d0-7 (LSET_L):This sets the number of lines to be processed. (Lower bytes) (1 to 65535, 0 line not used) d0-7 (LSET_H):This sets the number of lines to be processed. (Upper bytes) When reducing(magnification)the actual number of lines to be coded (decoded) should be set.The number of lines (relative number of lines)from the process start command to be issued from now the immediately following temporary stop/end of trailer should be set. This register should be set to the value specified before the process star command is issued. Moreover,this register can be rewritten during processing as long as the following conditions are met:
- If the maximum value, (65535), is set before the process start command is issued,it can be reset once during processing.
- If a value other than maximum value (65535) is set before the process start command is issued and if resetting becomes necessary during processing,the maximum value (65535) has to be reset once and desired value should the reset. d7 d0 LSET_REG_L : LSET_REG_H : LSET_L LSET_H (6) Register used to set the number of pixels (W/R) (address:4) (address:5) d0-7 (PEL_L) :Number of pixels/line is set (Lower byte) d0-5 (PEL_H):Number of pixels/line is set (Upper byte) It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up 10240 pixels maximum when 2-line template is used. The number of pixels actually coded (or decoded)should be set when reducing(or expanding).When the image bus uses 16bits(or 32bits)in parallel I/F,multiples of 16 (or 32) should be set. In case of serial I/F,multiples of 8 should be used. d7 d0 d7 d0 d5 PEL_REG_L : PEL_REG_H : PEL_L PEL_H0 (5) Interrupt Enable Register (W/R) (address : 3) d0 (JE) :Temporary stop/End of trailer interrupt of initialization/coding/decoding/through . (0:interrupt mask, 1:interrupt enable) d1 (DE) :Coded data(Image data)read out/write in ready interrupt. (0:interrupt mask, 1:interrupt enable) d2 (ME) :Marker code detection interrupt during decoding. (0:interrupt mask, 1:interrupt enable) d3 (SE) :SC count over error interrupt during coding.(0:interrupt mask, 1:interrupt enable)) This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding. Processing of coding continues, but the correct coded data is not output. NOTE:Bits,d0-d3,are for interrupt enable of bits d0-d2 and d4 of the Status Register. The interrupt request signal(INTR) is asserted when any one of the status bit set in the interrupt enable (D0(JE)generates interrupts even during the temporary stop),the status goes to "0" due to H/W reset or the INTR signal is negated when the interrupt mask causes factors for interrupt to be lost. Moreever, the status register will not be cleared by the generation of interrupts or the R/W of the interrupt enable register. d7 (MP) :This specified the marker code detection time halt. (0:Continue/restart, 1:temporary halt) Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1"during decoding. (it occures interruption when the marker code is detected, if the ME bit preset to "1".) if decoding is not completed during the temporary halt,it is possible to reset the line number setup register. Next, if this MP bit is set to "0",decoding is restarted(Decoding continues to the line number set.) IENB_REG : d7 d0d3 MP 0 SE ME DE JE
The byte set to this register is outputted as the end marker during coding. d0-7 (MDET):The marker codes detected during decoding are read out. The marker codes detected during decoding read out as is.
- NOTE1:Address A is used with 8bit bus. In case of the 16 bit bus, only the word access is possible.
end marker is issued in order to use it as a word boundary. lower byte becomes valid data regardless of the bus width of the host bus (BUS16).
- NOTE:The number of lines to be processed by this processing is cleared to 0 by the issuance of process start command.
Table 11. 4 Context data line-up
- 3 Initialization of register
Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the system set up registers. Table 11. 5 Initialization values for registers up in the System Setup Register. *d0 and d1 are possible only during decoding. *d2 and d3 are possible only during coding. This reduction is valid only during coding. used) For example, this function is used by the Host 16 bits bus when the leading 1 byte of the input data word is an invalid data. Note :Selecting this function is valid in case of the Host 8 bits bus and the external context mode also. during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1). the H/W reset is written into the external reset terminal or the system set up register.
MITSUBISHI ICs (LSI) 11. 4 Sequence of setting up registers (1) Initialization sequence of the internal line memory and context table RAM This sequence starts with the initialization set up (See Note) of internal line memory by the H/W RESET. It is followed by the initialization of the Context table RAM. (Clear) to 2 SYS_REG: d7 d0 ;H/W reset bit ON0 0 0 0 0 0 0 1 0 0 0 0 C 0 0 0 ;H/W reset bit OFF ;C=Context mode set up ;Context table initialized ;Process ens interrupt enable CMD_REG: IENB_REG: [During this time,the context table RAM is initialized.] The number of clocks needed for initialization is as follows, When the internal text mode is used, 1024 + a [clocks] When the external text mode is used, 4096 + a [clocks] (Interrupt generation) Set up interrupt enable 0 0 0 0 0 0 0 1 ;Interrupt disable N Y (Error) ;j=End of processing ;End of initialization SYS_REG: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Context table RAM Initialization command issued Interrupt enable set up H/W Reset Context mode set up – – – – – – – JSTAT_REGStatus register read out (Check if procesing finished) End of initialization command j = 1 ? d7 d0 CMD_REG: IENB_REG: 0 0 0 0 0 0 0 0 * The ON time for H/W RESET bit (The time from d0="1" is written in to the time when d0="0" is written in)should be 100ns more. Note: Initialization of the line memory by H/W RESET is provided for for the start of coding and decoding by preparing the all white (0) data as a reference line. At the same time,it initializes the LNTP bit to LNTP=1 for the Typical Prediction .
MITSUBISHI ICs (LSI) (2) Coding/decoding of stripes (No change in the AT pixel position)/Image data through processing sequence SYS_REG: d7 d0 b p x s C m m 0 ;Processing end interrupt enable CMD_REG: IENB_REG: [Coding and decoding are performed during this time]– – –I/O of image data and code data is performed. (Coding and decoding of stripe is performed.) PARA_REG:Parameter set up (Template,context) Set up number of pixels System set up (LSI mode set up) PEL_REG_L: PEL_REG_H: Set up number of lines Set up marker code (Note:Coding only) Set up functions Process start command (Coding/decoding/through) Set up interrupt enable LSET_REG_L: LSET_REG_H: MSET_REG: CONV_REG: ;mm=operating mode(Coding/decoding) ;C=context selection(Internal/external) ;s,x=Bit,byte swap ;p,b=Image data I/F, bit width ;aa,aaaaa=AT pixel position ;t=Template selection ;l=Conditions to take in external context ;c=External context CX0 selects ;pel_l,pel_h=Number of pixels per line ;lset_l,lset_h=Number of lines processed ;mset=marker code byte set up (SDNORM=02h,SDRST=03h) ;Ve,He=Select expansion during decoding ;Vr,Hr,Ho=Select reduction during coding ;Ob=Select discarding leading 1 byte during decoding ;Tp=ON/OFF of typical prediction function ;Li=Select prohibiting initialization of line memory ;End of trailer processing (Coding/decoding/through) start command pel_l 0 0 lset_l lset_h mset pel_h * When the external context mode is used,it is not necessary to set the position of AT pixels,number of pixels,number of lines,and expansion,reduction/typical prediction/line memory initialization selection. (They will be invalid) Note:Set Li to "0" when it is the leading stripe of single or multi stripe. * Tp Li Ob Ho Hr Vr He Ve * c/a l/a t a a a a a 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 (Interrupt is generated) Interrupt disable is set up ;Interrupt disable N Y (Error) ;mdet=marker code read out STAT_REG:Status register is read out (Check end of processing) j = 1 ? d7 d0 MDET_REG: IENB_REG: mdet End (Marker not yet detected) (Error) (Decoded) (Coded)N Y Decoded? m=1? End N (Marker detected)Y Marker code read out Note:only for decoding ;j=End of processing ;m=Marker detection ;s=SC counter overflow s = 0 ? (Error) N (SC counter overflow) Y 0 0 0 0 0 0 0 0
MITSUBISHI ICs (LSI) (Interrupt is generated) Interrupt disable is set up ;Interrupt disable ;AT pixel change set up (a'a'a'a'a'a'a') STAT_REG:Status register is read out Set up the last AT d7 d0 PARA_REG: IENB_REG: ;Status check ;j=0,p=1;temporary check Last set up Go to 3 Set up AT pixel position Middle of set up * Template not to be changed Set up number of lines LSET_REG_L: LSET_REG_H: lset_l lset_h ;lset_l,lset_h=Number of lines process Note:Set up the number of lines to be processed from the time processing restarted to the position where next the next AT pixel is changed. to Next page (3) Processing sequence of coding/decoding of stripes (Internal context mode and AT pixel position may change) SYS_REG: d7 d0 b p x s C m m 0 ;Processing stop interrupt enable CMD_REG: IENB_REG: [Coding /decoding go on during this time] – – – I/O of the first image data and code data take place. PARA_REG: Parameter set up (Template,At pixel position) Set up number of pixels System set up (LSI mode set up) PEL_REG_L: PEL_REG_H: Set up number of lines Set up marker code (Note:Coding only) Set up various functions Process start command (Stop processing temporarily) Set up interrupt enable LSET_REG_L: LSET_REG_H: MSET_REG: CONV_REG: ;mm=operating mode(Coding/decoding) ;C=0 Internal context selected ;s,x=Bit and byte swap ;p,b=Image data I/F, bit width ;aa,aaaaa=AT pixel position ;t=Template selection ;pel_l,pel_h=Number of pixels per 1 line ;lset_l,lset_h=Number of lines process Note:The number of lines up to the point where AT pixel position is changed is set. ;mset=marker code byte set up (SDNORM=02h,SDRST=03h) ;Ve,He=Expansion selection for decoding ;Vr,Hr,Ho=Select reduction during coding ;Ob=Select discarding leading 1 byte when coding ;Tp=ON/OFF of typical prediction function ;Li=Select prohibiting initialization of line memory. Note ;Stop processing temporarily (Coding/decoding) pel_l lset_l lset_h mset pel_h Note:Set Li to "0" when the leading stripe of single or multi stripe is used. Tp Li Ob Ho Hr Vr He Ve Note:During the first processing,if it is coding,(the number of lines of the input image data)= (the value set in the register which sets the number of lines)+1 During decoding,(number of lines of the output image data)=(the value set in the register which sets the number of lines)-1 a a t a a a a a 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 a' a' t a' a' a' a' a'
MITSUBISHI ICs (LSI) ;Processing end interrupt enable CMD_REG: IENB_REG: [Coding and decoding are performed during this time] – – – I/O of image data and code data is performed. (Interrupt is generated) Interrupt disable is set up ;Interrupt disable N Y (Error) ;mdet=marker code read out 0 0 0 0 0 0 0 1 STAT_REG:Status register is read out (Check end of processing) j = 1 ? d7 d0 MDET_REG: IENB_REG: mdet Process start command (Temporary stop command) Set up interrupt enable ;Command to restart processing which stopped temporarily (Coding/decoding) End (Marker not yet detected) (Error) (Decoded) (Coded)N Y Decoded? m=1? End N (Marker detected)Y Marker code read out Note:only for decoding ;j=End of processing ;m=Marker detection ;s=SC counter overflow s=0? (Error) N (SC counter overflow) Y (To previous page) This routine is repeated the (AT move -1) timesNote:During the above processing the following is true. During coding, (The number of lines of the input image data) = (Number of lines set in the line number setting register) During decoding, (Number of lines of the output image data) = ( Number of lines set in the line number setting register) 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
MITSUBISHI ICs (LSI) (4) Read out /write in sequence of context table RAM This sequence dies R/W of context table RAM. SYS_REG: d7 d0 [Reading (writing) of Context table RAM continues during this time.] RAM data is outputted (inputted) by way of data read (write) buffer. The RAM address is automatically incremented every time 1 byte is read out (write in) (Note) It I not possible to mix reading and writing. CMD_REG:Start command for R/W of RAM Set context mode ;H/Wreset bit OFF ;C=Context mode set 0 0 0 0 0 1 0 0 This does not end automatically. Be sure to write the end of R/W command. ;Start of R/W context table RAM 54329 87 6 Note:The assignment of address for context table RAM is as follows. Internal context mode:Address 0 to 1023 of (LSB:0, MSB:9) as shown below. External context mode:Address 0 to 4095 of (LSB:CX0, MSB:CS11) 3-line template 2-line template (AT pixel is MSB:9) CMD_REG:End of R/W command of RAM ;End of R/W command of RAM0 0 0 0 0 0 0 0 ?0 1 54329
MITSUBISHI ICs (LSI) (5) Overall sequence of multi-stripe coding/decoding The image whose 1page is composed of multiple stripes must perform (2) or (3) by stripes after the initialization of (1). (Description) If the end marker of the stripe one before is SDNORM, do not initialize the line memory nor the Context table RAM. The AT pixel position will use the last value of the previous stripe and starts processing next stripe. In case of SDRST,initialization takes place first and then the AT pixel position is returned to the default position. Then the processing of the next stripe begins. (Note1) When 16 bit bus is used for the host-bus during coding , in order to use the word boundary, he pad byte ("00") 1byte long tends to follow behind the end marker code of each stripe.This must be eliminated externally. (Note2) When starting decoding of each stripe (during decoding), inputting must start from the leading coded data of SDE (Stripe data entity). If necessary, the leading 1 byte is discarded. (In case when the leading portion of coded data of the next stripe is already inputted in LSI (FIFO) or when it is not lined up with the lead boundary during decoding of each stripe ends,external management is needed. Is the previous stripe SDNORM? Y N (SDRST) All stripes process ended? Y N End of page Stripe coding/decoding (Line memory initialization prohibited:Li=1,AT pixel= the value of previous stripe stripe coding/decoding process (line memory initialization is specified by Li=0, AT pixel =default position(0) [ (2) or (3) is processed] (SDNORM) Initialization of internal line memory and Context table RAM (1) processing multi-stripe coding/decoding [(2)or (3) is processed] This routine is repeated(Number of stripes -1) Internal memory & context table RAM are initialized. (1) processing Coding/decoding of 1st stripe (2) or (3) processing (Note3) Management of marker codes (AT MOVE, NEWLEN, etc) processing (Insertion at the time of coding and detection/removing at the time of decoding) should be done externally.
MITSUBISHI ICs (LSI) 12. ABSOLUTE MAXIMUM RATINGS (Ta=–20 to +70°C unless otherwise noted) 13. RECOMMEND OPERATING CONDITIONS Note : All of the voltage is reference the G ND terminal of the circuit . Maximum value and minimum value are expression of absolute value. Symbol Parameter Conditions Ratings Unit Supply voltage Input voltage Output voltage Ta=25°C When single IC is usedPower dissipation Storage temperature VCC VI VO Tstg Pd V V V mW -0.3 to +7.0 -0.3 to V CC +0.3 0 to VCC -65 to +150 1380 Symbol Parameter Test conditions Unit Limits Min Typ Max Supply voltage GND voltage Input voltage Operating temperature range Output capacitance(against IC) VCC GND Topr VI C L V V V pF 5.55.04.5 VCC0 +70-20
MITSUBISHI ICs (LSI) 14. ELECTRICAL CHARACTERISTICS (Ta=-20 to +70°C, VCC =5V –10% unless otherwise noted) Symbol Parameter Test conditions Limits Min Typ Max Unit "H"input voltage PD<31:0>,A<3:0>, D<15:0>,SVID, BUS16,CS,BHE "L"input voltage "H"input voltage "L"input voltage Positive threshold voltage "H"output voltage D<15:0> IOH =-8mA IOH =8mA IOH =-4mA IOH =4mA IOH =-2mA IOH =2mA "H"Input current "L"Input current VCC =5.5V, VI=5.5V VCC =5.5V, VI=0V "H"output current in OFF state D<15:0> VCC =5.5V, VI=5.5V VCC =5.5V, VI=0V Pull up Resister V CC =5.5V, VI=0V Hysteresis width MCLK,PXCK PD<31:0>,INTR, DMARQ,PDRQ, PRDY,RVID A<3:0>, D<15:0>,RD,WR, MCLK,BHE, RESET,CS PDRD,DMAAK, PDAK,PTIM XWAIT,PDWR, TEST1,TEST0, RD,WR,RESET XCLK,PXCKO Dynamic consumption V CC =5.5V, VI=VCC , GND PD<31:0>,PDRD, PDWR,PDAK, SVID,PTIM, PXCK,XWAIT, BUS16,DMAAK VCC =5.5V, VI=5VPull down Resister TEST1,TEST0 * The value of register is 50kW buffer's value. Negative threshold voltage "L"output voltage "H"output voltage "L"output voltage "H"output voltage "L"output voltage "L"output current in OFF state VIH VIL VIH VIL VT+ VT- VH VOH VOL VOH VOL VOH VOL IIH IIL IOZH IOZL R U R D ICCA V V V V V V V V V V V V V mA mA mA mA kW kW mA 2.0 0.8 0.0 2.4 4.5 0.6 0.2 0.55 VCC -0.8 VCC -0.8 0.55 VCC -0.8 0.55 -1.0 -5.0 1.0 5.0 25* 100* 21* 100* 100
MITSUBISHI ICs (LSI) 15. TIMING CHARACTERISTICS (Ta=-20 to +70°C, VCC =5V –10% unless otherwise noted) Test conditionsSymbol Parameter Limits Min Typ Max Unit 1) Host Bus I/F Test circuit tPZL (RD-D0 to 15) tPZH (RD-D0 to 15) tPLZ (RD-D0 to 15) tPHZ (RD-D0 to 15) t PHL (DMAAK-DMARQ) D0 to 15 output define time for RD assert D0 to 15 output hold time for RD assert DMARQ negate time for DMAAK assert C L=50pF 0 ns ns ns ns ns 2) Image data I/F RVID output define time for the fall of PXCKO RVID negate time for PTIM negate PDRQ negate time for PDAK assert PD0 to 31 output define time for PDRD assert PD0 to 31 hold time for PDRD negate tPLH (PTIM-PRDY) tPHL (PXCK-RVID) tPLH (PXCK-RVID) tPHL (PXCK-PXCKO) tPLH (PXCK-PXCKO) tPHL (PXCKO-RVID) tPLH (PXCKO-RVID) tPLH (PTIM-RVID) tPHL (PDAK-PDRQ) tPZL (PDRD-PD0 to 31) tPZH (PDRD-PD0 to 31) tPLZ (PDRD-PD0 to 31) tPHZ (PDRD-PD0 to 31) Test conditionsSymbol Parameter Limits Min Typ Max Unit Test circuit PRDY negate time for PTIM assert RVID output define time for the fall of PXCK PXCKO delay time for PXCK C L=50pF ns ns ns ns 20 ns 0n s 10 ns 10 ns 15 ns 15 ns 25 ns 25 ns 30 ns
MITSUBISHI ICs (LSI) 3) Context I/F tPLH (XTIM-XRDY) tPLH (XCLK-RPIX) tPHL (XCLK-RPIX) tPLH (MCLK-XCLK) tPHL (MCLK-XCLK) Test conditionsSymbol Parameter Limits Min Typ Max Unit Test circuit XRDY negate time for XTIM assert time RPIX output define time for the fall of XCLK XCLK delay time for MCLK C L=50pF 30 ns 30 ns 30 ns 30 ns 30 ns
MITSUBISHI ICs (LSI) DMAAK hold time for WR negate CS set up time for RD asserttsu(RD-CS) th(RD-CS) tw (RD) tsu(RD-A0 to 3) tsu(RD-BHE) th(RD-A0 to 3) th(RD-BHE) tsu(WR-CS) tsu(WR-A0 to 3) tsu(WR-BHE) th(WR-CS) tw (WR) th(WR-A0 to 3) th(WR-BHE) tsu(WR-D0 to 15) tsu(RD-DMAAK) tsu(WR-DMAAK) th(WR-D0 to 15) th(RD-DMAAK) th(WR-DMAAK) A0 to 3 set up time for RD assert CS hold time for WR negate A0 to 3 set up time for WR assert BHE hold time for RD negate D0 to 15 input set up time for WR negate A0 to 3 hold time for WR negate BHE hold time for WR negate DMAAK set up time for RD assert WR assert time BHE set up time for RD assert CS set up time for WR assert A0 to 3 set up time for WR assert CS hold time for RD negate RD assert time A0 to 3 hold time for RDnegate D0 to 15 input hold time for WR negate DMAAK hold time for RD negate DMAAK set up time for WR assert 16. TIMING CHARACTERISTICS (Ta=-20 to +70°C, VCC =5V –10% unless otherwise noted) Test conditionsSymbol Parameter Limits Min Typ Max Unit 1) Host Bus I/F Test circuit tw (RESET) RESET assert time C L=50pF 100 ns 20 ns 20 ns 20 ns 20 ns 30 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 30 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns
MITSUBISHI ICs (LSI) MCLK high level time(Mh) when used image data I/Ftwi+(MCLK) twi-(MCLK) tsu(PXCK-PTIM) tri(MCLK) tfi(MCLK) th(PXCK-PTIM) tw+ (PXCK) tw-(PXCK) tsu(PXCK-SVID) th(PXCK-SVID) tc(PXCK) tsu(PDRD-PDAK) th(PDRD-PDAK) tw (PDRD) tsu(PDWR-PDAK) tw (PDWR) th(PDWR-PD0 to 31) th(PDWR-PDAK) tsu(PDWR-PD0 to 31) MCLK rising time when used image data I/F PXCK period SVID set up time for the fall of PXCK PXCK high time PDAK set up time for PDWR assert PDAK hold time for PDRD negate PDRD assert time PDWR assert time PDAK set up time for PDRD assert MCLK falling time when used image data I/F PXCK low time SVID set up time for the fall of PXCK MCLK low level time(Ml) when used image data I/F PTIM set up time for the fall of PXCK PTIM hold time for the rise of PXCK PDAK hold time for PDWR negate PD0 to 31 input set up time for PDWR negate PD0 to 31 input hold time for PDWR negate Test conditionsSymbol Parameter Limits Min Typ Max Unit 2) Image Data I/F Test circuit tci(MCLK) MCLK period(Mx) when used image data I/F C L=50pF 50 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 50 ns 10 ns 10 ns 20 ns 20 ns 30 ns 20 ns 20 ns 20 ns 20 ns 20 ns
MITSUBISHI ICs (LSI) MCLK high level time(Mh) when used context I/Ftwc+(MCLK) twc-(MCLK) tsu(MCLK-XTIM) trc(MCLK) tfc(MCLK) th(XCLK-XTIM) tw+ (XCLK) tw-(XCLK) th(XCLK-XWAIT) tsul(XCLK-CX0 to 11) tc(XCLK) tsul(XCLK-PEUPE) tsul(XCLK-SPIX) thl(XCLK-CX0 to 11) thl(XCLK-PEUPE) tsut(XCLK-CX0 to 11) tht(XCLK-CX0 to 11) thl(XCLK-SPIX) tsut(XCLK-SPIX) MCLK rising time when used context I/F XCLK period XWAIT negate time for the rise of XCLK XCLK high time MCLK falling time when used context I/F XCLK low time CX0 to 11 set up time for the rise of XCLK MCLK low level time(Ml) when used context I/F XTIM assert time for the rise of MCLK XTIM negate time for the rise of XCLK Test conditionsSymbol Parameter Limits Min Typ Max Unit 3) Context I/F Test circuit t cc(MCLK) MCLK period(Mx) when used context I/F C L=50pF 100 ns 40 ns 40 ns 20 ns 20 ns 20 ns 20 ns Mh ns Ml ns Mx ns 0n s 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 70 ns 70 ns 20 ns tk(XCLK-PEUPE) tht(XCLK-SPIX) 20 ns ns PEUPE set up time for the rise of XCLK SPIX set up time for the rise of XCLK CX0 to 11 hold time for the rise of XCLK PEUPE hold time for the rise of XCLK SPIX hold time for the rise of XCLK CX0 to 11 set up time for the rise of XCLK SPIX set up time for the rise of XCLK CX0 to 11 hold time for the rise of XCLK SPIX hold time for the rise of XCLK PEUPE input define time for the rise of XCLK
MITSUBISHI ICs (LSI) 17. TEST CIRCUIT Input Master clock M C LK Parameter Open SW1 SW2 (1) characteristic of pulse generation (PG) (10% to 90%) tr=3ns, tf=3ns (2) Capacitance CL includes stray wiring capacitance and probe input capacitance. 90% 90% 10% 10% Open Close Open CloseOpen Close Open CloseOpen VCC PG DUT O utput V CC R L=1kW SW1 R L=1kW SW2 C L G ND50W tPLH , tPHL tPLZ tPHZ tPZL tPZH tri(M C LK) trc(MCLK) tfi(M C LK) tfc(MCLK) twi-(M C LK) twc-(MCLK) twi+(M C LK) twc+(MCLK) tci(M C LK) tcc(MCLK)
MITSUBISHI ICs (LSI) HOST BUS I/F (1) MPU access RE SET tw (RESET) tsu (RD-CS) tsu (RD-A0 to 3) tw (RD ) tsu (RD-BHE) th (RD-A0 to 3) th (RD-BHE) tsu (WR-A0 to 3) tsu (WR-BHE) th (WR-A0 to 3) th (WR-BHE) tsu (WR-CS) th (WR-CS) th (RD-CS) tw (WR ) tsu (WR-D0 to 15) th (WR-D0 to 15) Input tPLZ (RD-D0 to 15) 10% tPHZ (RD-D0 to 15)90% 50% 50% tPZL (RD-D0 to 15) tPZH (RD-D0 to 15) A0 to 3 CS D0 to 15 BHE RD WR D0 to 15 50% tPHL (DMAAK-DMARQ) tsu (RD-DMAAK) tw (RD ) th (RD-DMAAK) tsu (WR-DMAAK) tw (WR ) th (WR-DMAAK) th (WR-D0 to 15) tsu (WR-D0 to 15) Input tPLZ (RD-D0 to 15) 50% 50% 10% 90% tPHZ (RD-D0 to 15) tPZL (RD-D0 to 15) tPZH (RD-D0 to 15) D0 to 15 RD WR D0 to 15 DMAAK DMAR Q (2) DMA access
MITSUBISHI ICs (LSI) IMAGE DATA I/F (1) Serial image data I/F PRDY tPLH (PTIM-PRDY) 50% tsu (PXCK-PTIM) tc(PX C K) tw+ (PX C K) tw-(PX C K) th (PXCK-PTIM) tPLH (PX C K-RX C KO) tPLH (PX C KO -RVID) tPHL (PXCK-RXCKO) tPHL (PX C KO -RVID) tPHL (PX C K-RVID) 50% 50% tPLH (PXCK-RVID) 50% tPLH (PTIM-RVID) th (PXCK-SVID) tsu (PXCK-SVID) PTIM PX C K PX C KO PVID SVID (2) Pallarell Image Data PDR Q tPHL (PDAK-PDRQ) 50% PDAK PDRD PDWR PD0 to 31 tsu (PDRD-PDAK) t w (PDRD ) th (PDRD-PDAK) tw (PDWR ) th (PDWR-PDAK) tsu (PDWR-PDAK) tPLZ (PDRD-PD0 to 31) 10% tPHZ (PDRD-PD0 to 31) 50% 50% 90% tPZL (PDRD-PD0 to 31) tPZH (PDRD-PD0 to 31) tsu (PDWR-PD0 to 31) Input th (PDWR-PD0 to 31)
MITSUBISHI ICs (LSI) CONTEXT I/F (1) Latch input mode XRDY tPLH (XTIM-XRDY) 50% XTIM M C LK XC LK C X0 to 11 XWAIT PEUPE SPIX RPIX tsu (MCLK-XTIM) tPHL (MCLK-XCLK) tPLH (MCLK-XCLK) th (XCLK-XWAIT) th (XCLK-XTIM) tc(XC LK) tw- (XCLK) tw+ (XCLK) thl (XCLK-CX0 to 11) thl (XCLK-PEUPE) t hl (XCLK-SPIX) tsul (XCLK-CX0 to 11) tsul (XCLK-PEUPE) t sul (XCLK-SPIX) tPHL (XCLK-SPIX) 50% tPLH (XCLK-SPIX) 50%
MITSUBISHI ICs (LSI) (2) Through input mode XRDY tPLH (XTIM-XRDY) 50% tsu (MCLK-XTIM) tPHL (MCLK-XCLK) tPLH (MCLK-XCLK) tc(XC LK) tw- (XCLK) tw+ (XCLK) th (XCLK-XWAIT) th (XCLK-XTIM) XTIM M C LK XWAIT XC LK C X0 to 11 SPIX PEUPE RPIX tsut (XCLK-SPIX) tsut (XCLK-CX0 to 11) tht (XCLK-SPIX) tht (XCLK-CX0 to 11) tk (XCLK-PEUPE) tPLH (XCLK-RPIX) 50% tPHL (XCLK-RPIX) 50%