M65677FP MITSUBISHI | Alldatasheet
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MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER
DESCRIPTION
The M65677FP encodes CCIR601 or CCIR656 format Y/Cb/Cr data into analog NTSC and PAL video signals, including Digital Signal Processing functions such as Closed Caption encoding, Overlay OSD, Anti Video Copy Processing (Note1) e.t.c. It also includes peripheral processing function such as 10bit DAC e.t.c., so that low cost and compact system can be realized.
FEATURES
Macrovision’s video anti copy process Rev 7.01 supported (Note1) Overlay CGMS signal on line 20/283 for 525/60 (Note3) Generate CRCC for CGMS Signal Overlay WSS signal on line 23 for 625/50 (Note4) Color adjustment (TINT/color control) NTSC, B/G PAL or MPAL Video Outputs Component Y/C Video (S-Video) and CVBS or Y/U/V Outputs Supporting CCIR601 and CCIR656 format data Closed Caption Manager on line 21/284 for NTSC Generate ODD parity for Closed Caption Manager H/V Sync and Composite generating Overlay Digital OSD Supporting Y/Cb/Cr 4:4:4 Over sampling Filter 2ch 10bit DAC and 3ch 6dB Amp (Note2) 3.3V I/O interface I C Bus Interface for Controls Power down mode Note (Note1): This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. The use of Macrovision Corporation's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-par-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. (Note2): 6dB Amp max. output is 1.0V P-P (Note3): Copy Generation Management System-A (IEC1880) (Note4): Wide Screen Signaling (ETS300 294) APPLICATION DVB, DVD , Digital CATV, Video CD PIN CONFIGURATION (TOP VIEW) Ycomp N.C. DV DD1 DV SS1 X out X in DV SS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DV DD2 N.C. N.C. DV DD1 TEST SCL SDA ACK RESET Master/slave OSD2 OSD1 OSD0 OSDCK DV SS1 DV DD1 DV DD2 Yref Cref DAY AV SS1 AV DD1 DAC Ccomp C in N.C Y in AV DD2 Y AV SS2 CVBS N.C. C DV SS2 PXCLK DVA SEL HD VD VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DV SS2 M65677FP Outline 64P6N-A NC : NO CONNECTION
MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER BLOCK DIAGRAM Y U V Y Cb Y HD VD VD [9:0] PXD [7:0] Input Interface OSDCK OSD2 OSD1 OSD0 C ref Y ref DAY Cb Cr Sync Processing OSD Interface Anti Copy Processing serial interface Closed Caption Y/Cb/Cr Y/U/V DAC LPF BPF DAC Cin Yin Y C CVBS AV SS2 AV DD2 CGMS/WSS Manager Master AVss1 Clamp bias DVdd2(X2) Y Manager 6dB 6dB 6dB DVdd1(X2) DVss2(X2) DVss1(X2) TEST RESET Cr DAC Y/C MIX AVdd1 C/V /Slave ACK SDA SCL ENCODE Y/U OSD Control I/F CCIR601 or 656 Pixel Data from MPEG decoder From/To MPEG decoder From micro controler Video output
MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITION (Ta=25 C, DV DD =AV DD =3.3V, DV SS =AV SS =0V, unless otherwise noted) Symbol Parameter Limits UnitMin. Typ. Max. V DD Supply voltage -0.3 4.5 V V I Digital input voltage -0.3 V DD +0.3 V V O Digital output voltage -0.3 V DD +0.3 V T a Operating temperature -20 +25 +75 C T stg Storage temperature -40 +125 C Symbol Parameter Test conditions Limits UnitMin. Typ. Max. Supply DV DDX Digital supply voltage 3.0 3.3 3.6 V AV DDX Analog supply voltage 3.15 3.3 3.45 V DI DD Digital current consumption 0 45 mA AI DD Analog current consumption 0 55 mA Digital input V IL Input voltage DV DD =3.0V 0 0.8 V V IH DV DD =3.6V 2.5 3.6 V I IL IL Input leakage current DV DD =3.0V, V I =0V or V I =3.6V m A C I Input capacitance f=1MHz, V DD =0V 7 15 pF Digital output V OL Output voltage DV DD =3.3V, I O m A 0.05 V V OH 3.25 V C O Output capacitance f=1MHz, V DD =0V 7 15 pF I C bus I O Output current DV DD =3.0V, V IL =0.4V 4.0 mA I OZ Output leakage current (off) DV DD =3.6V, V I =0V or V I =3.6V m A D/A converter Res Resolution 10 Bit INL Integral non-linearity error
2.0 LSB
DNL Differential non-linearity error
1.0 LSB
Maximum output amplitude 1.5 V P-P 6-dB amplifier R bias Bias resistor 7.5 10.0 11.5 k W G V_YC Output gain (Y/C) 5.50 6.00 6.50 dB G V_CV Output gain (CVBS) 5.10 6.00 6.85 dB DR in Input dynamic range 0.8 V P-P DR out Output dynamic range 1.6 V P-P Iyich Yin clamp charge current -12 -26 -50 m A Iyids Yin clamp discharge current 0.26 0.65 1.80 m A Ryicl Yin clamp discharge current 20 0.65 70 – Vyicl Yin input clamp voltage 0.45 0.50 0.55 V Vyocl Y output clamp voltage 0.40 0.50 0.60 V Vcvcl CVBS output clamp voltage 0.30 0.50 0.70 V Vcin Cin input bias voltage 0.95 1.00 1.05 V Vcob C output bias voltage 0.90 1.00 1.10 V Iamp Output current 1.00 mA Ryicl= -Iyich Iyids
MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER DESCRIPTION OF PIN Pin No. Pin name Type Function 1D V SS2 Supply Digital ground for the I/O. 2 PXCLK O Reference clock for input pixel data. The clock frequency is 27.0MHz. 3D V A SEL I I C slave address setting. "Low" is for the address of 40h, "High" is for the address of 42h. 4 HD I/O Horizontal sync signal input or output. It is an input and output in the slave and master mode, respectively. 5 VD I/O Vertical sync input or output. Or OddEven signal output. It is an input and output in the slave and master mode, respectively.
6 VD9
Video data outputs. In the Y/U/V output mode, the output is the 10-bit digital luma signal with a composite sync. VD9 is MSB and VD0 is LSB.
7 VD8
8 VD7
9 VD6
10 VD5
11 VD4
12 VD3
13 VD2
14 VD1
15 VD0
Supply Digital ground for the I/O. 17 DV DD2 Supply Digital supply for the I/O. 18 DV DD1 Supply Digital supply for the internal logic. 19 DV SS1 Supply Digital ground for the internal logic. 20 OSDCK O The reference clock for an external OSD microcontroller. The frequency is 13.5MHz or 6.25MHz, alternated by the I C bus control.
21 OSD0
I The color look-up table address input. MSB and LSB is OSD2 and OSD0, respectively.22 OSD1
23 OSD2
24 Master/Slave I
Synchronizing mode selection. "Low" is for the slave mode. "High" is for the master mode. 25 RESET I Initializing reset. "LOW" is active. 26 ACK O Acknowledge line (Open drain output). 27 SDA I/O Serial data line/Acknowledge line (Open drain output). 28 SCL I Serial clock line. 29 TEST I For testing. It should be grounded during an actual use. 30 DV DD1 Supply Digital supply for the internal logic. 31 N.C. No connection. 32 N.C. No connection. 33 C O The analog chroma output from a 6dB amplifier. The output amplitude is 1.0V P-P (typ.), while the input is 0.5V P-P 34 N.C. No connection. 35 CVBS O The analog composite video signal from a 6dB amplifier. The output amplitude is 1.24V P-P (typ.). 36 AV SS2 Supply Analog ground for 6dB amplifiers. 37 Y O The analog luma output from a 6dB amplifier. The output amplitude is 1.2V P-P (typ.), while input is 0.6V P-P 38 AV DD2 Supply Analog supply for 6dB amplifiers. 39 Yin I The analog luma input from an external LPF . This input has bias circuit. The signal must input via a capacitor. 40 N.C. No connection. 41 Cin I The analog chroma input from an external LPF . This input has bias circuit. The signal must input via a capacitor.
MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER DESCRIPTION OF PIN (cont.) Pin No. Pin name Type Function 42 Ccomp I Phase compensation for chroma or V output DAC. It should be connected to the analog ground via a capacitor.
43 DAC O
Chroma or V signal output. The DAC output should be connected to the analog supply via a load resistor (R L The output amplitude is set up by reference resistor (Rref) and RL. 44 AV DD1 Supply Analog supply for DACs. 45 AV SS1 Supply Analog ground for DACs.
46 DAY O
Luma or U signal output. It should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. 47 Cref I A reference current source for chroma or V signal output DAC. It should be connected to the analog supply via a reference resistor (Rref). 48 Yref I A reference current source for Y or U DAC. It should be connected to the analog supply via a reference resistor (Rref). 49 Ycomp I Phase compensation for Y or U DAC. It should be connected to the analog ground via a capacitor. 50 N.C. No connection. 51 DV DD1 Supply Digital supply for the internal logic. 52 DV SS1 Supply Digital ground for the internal logic. 53 Xout O System clock output. It must be in no connection except for a connection to a X'tal oscillator. 54 Xin I System clock input. The clock frequency is only 27.0MHz. 55 DV SS2 Supply Digital ground for the I/O.
56 PXD7
I Pixel data inputs. The acceptable video data are;
- multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV, defined in CCIR Rec656
- multiplexed video data (Y/Cb/Cr) defined in CCIR Rec601 MSB and LSB is PXD7 and PXD0, respectively.
57 PXD6
58 PXD5
59 PXD4
60 PXD3
61 PXD2
62 PXD1
63 PXD0
DD2 Supply Digital supply for the I/O.
MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER APPLICATION EXAMPLE (CCIR656 I/F , Y/C/CVBS Output Mode) 0.1m 0.1m 10k 10k 27MHz 47m 0.01m 47m 0.01m 2.2m 200 0.1m 2.2m 2.2m 0.1m 200 0.1m 220m 220m X in X out DV DD DV SS DVA SEL Master/Slave TEST Filter Stage Filter Stage 75W Driver 47m 0.01m Y C CVBS Digital NTSC/PAL Encoder M65677FP VD(9:0) PXD(7:0) PXCLK HD VD AV DD AVss Ccomp Ycomp Cref Yref DAC C in DAY Y in Y C CVBS RESET OSD(2:0) OSDCK SDA SCL ACK 47m 0.01m VDD VSS R/G/B OSC1 OSD micro computer M35041 HD VD CS RESET SIN SCK LRCIN DIN XTI BCKIN BD Audio DAC Lch Rch Audio out (L) Audio out (R) SCL SDA/ACK RESET AO0 AO1 AO2 AO3 LRCLK DOCLK DACCLK ACLKO ACLKI 27MHz XO 16M SDRAM PXCLK VSS VDD CLK in PXD BCLK BDEN BDER BDREQ 8BD RCLK BDEN BDER BDREQ Chanel Decoder Host CPU 3.3k CS RESET SIN SCK : 3.3V Power Supply (for Digital/Analog) MPEG2 System/ Video/Audio Decoder M65773FP Units Resistance : W Capacitance : F HSYNC VSYNC : 5.0V Power Supply (for Analog) 3.3k