M65667FP MITSUBISHI | Alldatasheet
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MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. PIN CONFIGURATION (TOP VIEW) NC TEST8 Y-PIP TEST9 Yin TESTEN Cin AVss (ana) AVss3 (VCXO) VCXO out VCXO in FILTER BIAS AVdd3 (VCXO) AVdd2 (m) AVdd2 (m) NC VD/CSYNC/TEST6 HD/TEST5 SWM/TEST4 MCK fsc/TEST3 BGP (m)/TEST2 DVdd2 (ram) DVss2 (ram) CLK DATA ACK CSYNC (s)/TEST1 SCK BGP (s)/TEST0 NC C-PIP AVdd4 (da) AVdd4 (da) AVdd4 (da) C-PIPin AVss4 (da) AVss4 (da) Y-PIPin ADJ-Ysub Yout-sub ADJ-Csub Cout-sub DVss3 DVdd3 LOCK/TEST7 NC Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVss2 (m) AVdd1 (s) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) AVss1 (s) RESET DVss1 DVdd1 NC M65667FP Outline 64P6N-A NC : NO CONNECTION
DESCRIPTION
The M65667FP is a NTSC PIP (Picture in Picture) signal processing LSI, whose sub and main-picture inputs are composite and Y/C separated signals, respectively. The built-in field memory (96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP system low cost and small size.
FEATURES
Built-in 96k-bit field memory (sub-picture data storage) Internal V-chip data slicer (for sub-picture) Vertical filter for sub-picture (Y signal ) Single sub-picture (selectable picture size : 1/9 , 1/16) Sub-picture processing sepecification (1/9 size / 1/16 size) : Quantization bits Y , B-Y , R-Y : 6bits Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y , R-Y) Vertical lines 69/ 52 lines Frame (sub-picture) on/off Built-in analog circuits : Two 8-bit A/D converters (main and sub-picture signals) Two 8-bit D/A converters (Y and C sub-picture signals) Sync-tip-clump, VCXO, Analog switch ... etc. I C BUS control (parallel/serial control) : PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off (programmable luma level), PIP position (4 corners fixed position), Picture freeze , Y delay adjustment, Chroma level, Tint, Black level, Contrast ... etc. APPLICATION NTSC color TV RECOMMENDED OPERATING CONDITION C DD 0.7 to V DD V DD 0.3V 4mA (MAX) NOTICE: Connect a 0.1 m F or larger capacitor between V DD and V SS pins. 1 : Include pin capacitance (7pF)
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. BLOCK DIAGRAM A/D 8bit RAM 96Kbits Back Porch Clamp Sync tip Clamp Yin Y- PIP C- PIP BiasVin(m) Vin(s) I2CDATA CLK ACK Vdd / Vss for test Y/C SEP (LPF,BPF) Luma Clamp Demod Tint Timing Gen (Decode) Delay VCXO Burst Data Sampling Level Detect Vert-filter MUX RAM(1H) AFCSync Sep Demux MIX Delay B-Y R-Y Delay Y B-Y R-Y B-Y R-Y Yout-sub Phase Select HPLL 4fsc HD VCXO Driver Phase Detect BIAS FILTER SWMG /TEST7 Lock/Free-run via I2C Timing Gen (Memory Cont) VD /CSYNC /TEST6 Y C HD /TEST5 fsc ( I2C ) 4fsc VCXO in Encode VCXO out Y- PIPin C- PIPin RESET Vrt(m) Vrb(m) Vrt(m) Vrb(m) ADJ-Ysub ADJ-Csub Cout-sub Cin SCK CSYNC(s) /TEST1 BGP(s) /TEST0 MCK BGP(m) /TEST2 fsc /TEST3 SWM /TEST4 LPF &MPY Delay I/F V-chip data slicer A/D 8bit Bias Bias Sync tip Clamp D/A 8bit D/A 8bit
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. DESCRIPTION OF PIN Pin No. Name I/O Function Remarks
1 Vin (m) I Chroma signal input (main-picture)
2 Vrt (m) O A/D Vref+ (main-picture)
3 Vrb (m) O A/D Vref- (main-picture)
4 AVss2 (m) GND Connect to analog GND
5 AVss2 (m) GND Connect to analog GND
6 AVdd1 (s) Vdd Connect to analog power supply
7 AVdd1 (s) Vdd Connect to analog power supply
8 Vin (s) I Composite video signal input (sub-picture)
9 Vrt (s) O A/D Vref+ (sub-picture)
10 Vrb (s) O A/D Vref- (sub-picture)
11 AVss1 (s) GND Connect to analog GND
12 AVss1 (s) GND Connect to analog GND
13 RESET I Power on reset input signal ("L" reset)
W to V DD ,10 m F to GND
14 DVss1 GND Connect to digital GND
15 DVdd1 Vdd Connect to digital power supply
BGP(s)/TEST0 (I/)O For test non connect
19 SCK I For test (connect to digital GND) connect to GND
CSYNC(s)/TEST1 I(/O) For test (connect to digital GND) pull down 15k W
21 ACK O I
C bus-data/Acknowledge output signal
22 DATA I I
23 CLK I I
24 DVss2(ram) GND Connect to digital GND
25 DVdd2(ram) Vdd Connect to digital power supply
BGP(m)/TEST2 (I/)O For test non connect 27 fsc/TEST3 I(/O) For test (pull down to digital GND by resistor 15k W ) pull down 15k W
28 MCK I For test (connect to digital GND) connect to GND
29 SWM/TEST4 (I/)O For test non connect
30 HD/TEST5 I(/O) Horizontal sync input signal (Positive going edge is used)
31 VD/CSYNC
/TEST6 I(/O) Vertical sync input signal (active "H") 32 NC 33 NC SWMG/TEST7 I(/O) Enable input signal to display sub picture ("H" enable) pull up 15k W
35 DVdd3 Vdd Connect to digital power supply
36 DVss3 GND Connect to digital GND
37 Cout-sub O D/A output signal (Chroma signal of sub-picture)
38 ADJ-Csub I D/A adjust for chroma signal (sub-picture)
39 Y out-sub O D/A output signal (Luma signal of sub-picture)
40 ADJ-Ysub I D/A adjust for luma signal (sub-picture)
41 Y -PIPin I PIP luma signal re-input
42 AVss4 (da) GND Connects to analog GND
43 AVss4 (da) GND Connects to analog GND
44 C-PIPin I PIP chroma signal re-input
45 AVdd4 (da) Vdd Connect to analog power supply
46 AVdd4 (da) Vdd Connect to analog power supply
47 AVdd4 (da) Vdd Connect to analog power supply
48 C-PIP O PIP chroma signal output
50 TEST8 I For test (connect to analog GND) pull up 15k
W
51 Y -PIP O PIP luma signal output
52 TEST9 I For test (connect to analog GND) connect to GND
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. ABSOLUTE MAXIMUM RATINGS SS =0V) 1: Output current per output terminal. But P d limits all current. DESCRIPTION OF PIN (cont.) Pin No. Name I/O Function Remarks
53 Yin I Luma input signal (main-picture)
54 TESTEN I For test (connect to analog GND) connect to GND
55 Cin I Chroma input signal (main-picture)
56 AVss (ana) GND Connect to analog GND
57 AVss3
(VCXO) GND Connects to analog GND
58 VCXO out O VCXO output signal
59 VCXO in I VCXO input signal
60 FILTER I Filter
61 BIAS O Bias
62 AVdd3
(VCXO) Vdd Connect to analog power supply
63 AVdd2 (m) Vdd Connect to analog power supply
64 AVdd2 (m) Vdd Connect to analog power supply
Symbol Parameter Limits UnitMin. Max. V DD3 Supply voltage (3.3V) -0.3 4.6 V V I Input voltage -0.3 V DD3 +0.3 V V O Output voltage -0.3 V DD3 +0.3 V I O Output current I OL =20 I OH =-26 mA P d Power dissipation 1400 mW T opr Operating temperature -20 75 C T stg Storage temperature -50 125 C
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. DC CHARACTERISTICS (Ta=25 C, unless otherwise noted, V SS =0V) TYPICAL CHARACTERISTICS Symbol Parameter Test conditions Limits UnitMin. Typ. Max. V IL Input voltage (CMOS interface) LV DD =2.7V 0 0.81 V V IH HV DD =3.6V 2.52 3.6 V V T Input voltage schmitt trigger (CMOS interface) V DD =3.3V 0.5 1.65 V V T + + 1.4 2.4 V V H Hysteresis 0.3 1.2 V V OL Output voltage L V DD =3.3V, I O m A 0.05 V V OH H 3.25 V I OL Output current LV DD =3.0V, V OL =0.4V 4 mA I OH HV DD =3.0V, V OH =2.6V -4 mA I IH Input current LV DD =3.6V, V I =0V -1 m A I IL HV DD =3.6V, V I =3.6V -1 - 1 mA IOZL Output leakage current LV DD =3.6V, VO =0V -1 - 1 mA IOZH HV DD =3.6V, VO =3.6V -1 - 1 mA C I Input pin capacitance f=1MHz, VDD =0V - 7 15 pF C O Output pin capacitance - 7 15 pF C IO Bidirectional pin capacitance - 7 15 pF IDD Operating current 3.3V supply -- 140 mA THERMAL DERATING (MAXIMUM RATING) AMBIENT TEMPERATURE Ta ( °C) 0 25 75 125 400 1200 2000 100 1600 POWER DISSIPATION P d (mW) 800 1280
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. APPLICATION EXAMPLE Analog GND Digital +3.3V Digital GND Analog +3.3V Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust. And then mix both signals for sub-picture input video signal. Ana. power supply power supply Units Resistance : W Capacitance : F 103 10m 103 360150p 103 10m PIP Chroma signal output Sub-picture displaying on/off Dig Ana. 104 470 Ana. 68p Ana. 104 103 15kAna. PIP Luma signal output Luma signal input Chroma input signal 104 104 10m 103 Ana. Ana. 100k 10m 103104 103 10m 103 Composite video input signal (sub-picture) Ana. 103103 10m 103 104 Dig Vertical sync input signal (main-picture) Horizontal sync input signal (main-picture) 51 14p 103 3.3m 100k 470k 330104 I2C BUS Clock input signal SCL SDA Dig5V 12k 47k I2C BUS DATA input /output signal 100 100 10k Dig5V 12k 47k 100 10k 10m 15k 103 Dig 560 330 SYNC SEP CIRCUIT (OPTIONAL) (main-picture) (main-picture) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 M65667FP
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. PIP TV SYSTEM BLOCK DIAGRAM (BASIC) Composite Video Signal Y/C Separated Video Signal Y C Y C Y C CV Y C Y C M65667FP BLPLL B-LD Y/C Separation PIP Signal Processing Video Signal Processing Deflection Unit Yoke HD VD (Driving Method and Operating Specification for Serial Interface Data) (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is 'H' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) 1. The byte format during data setting to M65667FP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h). 2. The byte format during data reading from M65667FP are shown as follows. Before data reading from M65667FP , whose internal address need to be set by the data reading/transmitting. After the data reading/ transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h).
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. (The examples of serial byte transmission format) (1) The writing operation of the setting data (AAh) into M65667FP internal address of 00h (2) The writing operation of the setting data (FFh, 80h, EEh) into M65667FP internal address of 04h to 06h (3) The reading operation of the setting data from M65667FP internal address of 00h Transmission Activation Confirmation of bus free (DATA='H') is applied on CLk for the release of output state no S 24h A 00h A AAh A D E yes S : Operation of serial transmission start A : Acknowledge detection D : Dummy clock feed for the release of acknowledge output state E : Operation of serial transmission completion Transmission Activation Confirmation of bus free (DATA='H') is applied on CLk for the release of output state no S 24h A 04h A FFh yes A 80h A EEh ADE Transmission Activation Confirmation of bus free (DATA='H') is applied on CLk for the release of output state no S 24h A 00h A yes 25h A $$h A’ A’ : Bus free operation by the master (micro processor) DE S
MITSUBISHI ICs (TV) M65667FP PICTURE-IN-PICTURE SIGNAL PROCESSING PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. (4) The reading operation of the setting data from M65667FP internal address of 04h to 06h TIMING DIAGRAM Transmission Activation Confirmation of bus free (DATA='H') is applied on CLk for the release of output state no S 24h A 04h A yes 25h A SSh A’’ A’’ : Output ‘L’ operation by the master (micro processor) DE S A’’ A’SSh SSh 123456 7 891 CLK DATA Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) ACK Detec. Bit7 (MSB) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Bit7 (MSB) ACK _ Acknowledge ACK _ Readout data