M65665SP

M65665SP MITSUBISHI | Alldatasheet

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Technical content

• I nternal V-chip data slicer ( f or sub-picture) * Vertical f ilter f or sub-picture ( Y s ignal ) * Base band comb f ilter (2 Line) * Single sub-picture ( selectable picture si ze : 1/9 , 1/16 ) * Sub-picture processing speci f ication ( 1/9 , 1/16 si ze) : Quanti zation bits Y, B-Y, R -Y : 7 bits Hori zontal sampling 229 pixels ( Y), 57 pixels (B- Y, R- Y) Ver tical lines 69 / 52 lines * F rame ( sub-picture ) on/o ff * Built-in analog circuits : Two 8-bit A/D con v erter (f or sub-picture signal) Three 8-bi t D/ A conv erters ( f or Y, U and V o f sub-picture) * IIC BUS control ( parallel/serial con trol) : PIP on/o ff , F rame on/o ff ( programmable luma lev el), Sub-pi cture size ( 1/9, 1/16 ), PIP position ( f ree position ), Picture f reeze , Y delay adjustm ent, Chroma le v el, Tint, Black le v el, NTSC, PAL-M, PAL-N color TV Input v oltage (C MOS interf ace) " H" ----- VDD x 0.7 ~ VDD V NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pin s. *1 : Include pin capacitance ( 7 pF )

DESCRIPTION

The M65665SP/FP is a PIP (Picture in Picture) signal processing LSI, whose sub-picture input is composite signal or component signals( Y/C or Y/U/ V) f or NTSC, PAL-M, and PAL-N. The built-in f ield memory (168k-bit RAM) , V-chip data slicer and analog circuitries lead the high quality PIP s y stem low cost and small si ze. Block diagram & Application examples Shown next pages PIN CONFIGURATION (TOP VIEW) Outline 42 Pin S DIP Package (M65665SP) Outline 0.8mm pit ch 42 Pin SOP Pac kage (M65665FP)

FEATURES

RECOMME NDED OPERATING CONDITIONS 16 27 21 22 AVss (ad) Vrb Vrt CVBSin (ad) AVdd (ad) AVdd (vcxo) BIAS Filter X'tal(NT) X'tal(P-M) X'tal(P-N) AVss (vcxo) VD HD TESTEN CSYNCS RESET SWMG OSD_SEL TEST5 SDATA FSC BGPM SCK DVss DVdd SWM SCLK BGPS Cin(ad) Vin(ad) Uin(ad) V(B)OUT OSD_GIN U(G)OUT OSD_RIN Y(R)OUT VddDA AGndDA VZ OSD_BIN Yin(ad) MITSUBISHI ELECTRIC PICTURE-IN-PICTURE SIGNAL PROCESSING

PICTURE-IN-PICTURE SIGNAL PROCESSING BLOCK DIAGRAM MITSUBISHI ELECTRIC

(VSS=0V) (*1) Output current per ou tput terminal. But Pd limits all current. Sym bol Parameter Conditions Limits Unit Min. Max. VDD3 Supply v oltage (3.3V) -0.3 4.2 V VI Input v oltage(except 5V input) -0.3 VDD3+0.3 V VO Output v oltage -0.3 VDD3+0.3 V IO Output current (*1) IOL = 4 mAIOH = -4 PD Power dissipation mW Topr Operating te mperature -10 70 deg. Tstg Storage temperature -50 125 deg. ABSOLUTE MAXIMUM RATINGS 1200- TYPICAL CHARAC TERISTICS 0 25 50 75 100 125 400 800 THERMAL DERATING (MAXIMUM RATING) 1200 1600 2000 AMBIENT TEMPERATURE Ta (deg.) VI Input v oltage(5V input) -0.3 V5.25 MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

(VSS=0V) DC CH ARACTERISTICS Sym bol Parameter Condition Limits Unit Min. Ty p. Max. VIL Input v oltage L VDD = 2.7V 0 - 0.81 V VIH (3.3V C MOS interf ace) H VDD = 3.6V 2.52 - 3.6 VT- Input v oltage schmitt - 0.8 - 1.65 VT+ (5.0V C MOS interf ace) + VDD = 3.3V 1.4 - 2.7 V VH Hysteresis 0.3 - 1.2 VOL CMOS output v oltage L VDD = 3.3V, |I O| = 1µA - - 0.05 V VOH H 3.25 - - IOL CMOS output current L VDD = 3.3V, V OL = 0.4V 2 - - IOH H VDD = 3.3V, V OH = 2.6V - - -2 mA -IOZL Output leakage current L VDD = 3.6V, V O = 0V -10 - 10 µA IOZH H VDD = 3.6V, V O = 3.6V -10 - 10 CI Input pin capacitance - 7 15 CO Output pin capacitance f = 1MHz, VDD = 0V - 7 15 pF CIO Bidirectional pin capacitance - 7 15 IDD Operating current 3.3V supply mA- - (Ta = 25 deg. unless other wise noted) 140 IIH Input current L VDD = 3.6V, V I = 0V -10 - 10 µA IIL H VDD = 3.6V, V I = 3.6V -10 - 10 IIH Input current L VDD = 3.6V, V I = 0V -100 - 10 µA IIL H VDD = 3.6V, V I = 3.6V -10 - 10 (3.3V C MOS interf ace) (5.0V C MOS interf ace) MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

Pin No. Name I/O Function Remarks SWM SDATA SCLK DVdd1 DVss1 BGPS SCK BGPM FSC TEST5 OSD_SEL SWMG RESET CSYNCS AVss (ADC) VRB VRT VIN (ADC) CIN AVdd (ADC) AVdd (VCXO) BIAS FILTER X'tal (N TSC) X'tal (PAL- M) X'tal (PAL- N) AVss (VCXO) HD VD TESTEN VOUT VZ UOUT OSDBIN YOUT AVdd (DAC) AVss (sub) I2C SDA input/output I2C SCL input Vdd f or digital part Vss f or digital part Test output Test input Test output Test input Test input Output OSD select Power on reset input Sub picture external C-s y nc input Vss f or internal ADC Low lev el ref erence v oltage output o f ADC High lev el ref erence v oltage output o f ADC Sub picture V input of ADC Sub picture C input of ADC Vdd f or internal ADC Vdd f or VCXO VXCO bias v oltage connection VCXO f ilter v oltage connection X'tal o f N TSC c onnection X'tal o f PAL-M connection X'tal o f PAL-N c onnection Vss f or VCXO Main picture HD input MAIN picture VD input Test input Sub picture V or B ou tput Sub picture U or G output Sub picture Y or R output Vdd f or DAC Vss f or DAC OSD input of B Voltage ref erence output o f D AC PIP s witch output connect to G ND connect to G ND connect to Vdd CMOS output CMOS I/O(5V) *1 CMOS output CMOS input CMOS output CMOS input CMOS input CMOS input CMOS input CMOS input CMOS input Analog CMOS input(5V)*1 CMOS input(5V)*1 CMOS input Analog Analog Analog Analog Analog Vdd Analog Vdd Analog Analog Analog Analog Analog Vss Analog Analog Analog Analog Analog CMOS input(5V)*1 *1 ) (5V)means 5V I/F torelant connect to G ND Digital Vdd Digital Vss Analog Vss Analog Vdd Analog Vss Analog connect to G ND UIN (ADC) Sub picture U input of ADCAnalog CVBSIN Sub picture CVBS input o f ADCAnalog YIN (ADC) Sub picture Y input of ADCAnalog Analog OSDGIN OSD input of G OSDRIN OSD input of R MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

BASIC APPLICATION E XAMPLE Ana. Analog GND Digi tal +3.3V power supply Digi tal GND Analog +3.3V power supply Dig. PIP Y or R output IIC BUS Clock input IIC BUS DATA input /output PIP U or G output PIP V or B output Main VD input Main HD input PIP SW output Sub C(Y/C) input < NTSC onl y application example > < NTSC / PAL-M / PAL-N application example > 1627 2122 0.01µ 0.01µ 0.01µ 0.01µ 0.22µ 0.033µ 0.22µ 10µ X1 : 14.31818MHz 10K 12K (3.3V recommended) 3.3V 0.66V(max) 1.0V(max) 12~36p (3.3V recommended) 0.7V (typ) 0.7V (typ) 3.3V 15 pin input when CSYNC of sub picture is fed from external Sub V input Sub U input Sub Y(YUV) input Sub CVBS and Y(Y/C) input 0.1µ OSD R input OSD G input PIP Y or R output IIC BUS Clock inputPIP U or G output PIP V or B output Main VD input Main HD input PIP SW output Sub C(Y/C) input 1627 2122 0.01µ 0.01µ 0.01µ 0.01µ 0.22µ 0.033µ 0.22µ 10µ X1 : 14.31818MHz X2 : 14.30244MHz X3 : 14.328MHz 10K 12K (3.3V recommended) 3.3V 0.66V(max) 1.0V(max) 12~36p (3.3V recommended) 0.7V (typ) 0.7V (typ) 3.3V 15 pin input when CSYNC of sub picture is fed from external OSD B input OSD selection input Sub V input Sub U input Sub Y(YUV) input Sub CVBS and Y(Y/C) input 0.1µ X212~36p 0X3 12~36p IIC BUS DATA input /output 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 3.3V 2 pin input level MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

M65665SP/FP TV SYSTEM BLOCK DIAGRAM <BASIC > Y U Y U M65665SP/FP PIP Signal Processing Video Signal Processing Yoke HD VD V V Matrix R G B Def lection Unit Composite Video Signal Y/C Separated Video Signal Y C Y C Y C M65665SP/FP Y/C Separation Video Signal Processing Yoke HD VD R G B Def lection UnitR G B PIP Signal Processing SWM SWM OSD_RGB Y U V Y/U/ V Component Video Signal CV/Y Composite Video Signal Y/C Separated Video Signal Y C Y C Y C Y/C Separation Y U V CV/Y Y/U/ V Component Video Signal MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

Internal register in f ormation (preliminary) 00h <7> DISP Sub picture display : [ 0] off , [1] on <6> SIZE_V Sub picture v ertical si ze : [ 0] 1/9, [1] 1/16 <5> SIZE_H Sub picture horizontal si ze : [ 0] 1/9, [1] 1/16 <4> WEN Sub picture : [ 0] Still, [1] Mov ing <3> BGC Back ground display : [ 0] off , [1] on <2> BGCS Sub picture mute : [0] o ff , [ 1] on <1> FREE_RUN VCXO oscilation : [0] Lock, [1] Free run <0> RVS HD/ VD input sy nchronous mode selection : [0] s y nc., [1] as y nc. 01h <7:0> VXA<7:0> Sub picture v ertical position 02h <7:0> HXA<7:0> Sub picture horizontal position 03h <7> KILLER Sub picture color killer : [0] enable, [1] disable <6:0> U_DAC <6:0> Sub picture U or G DAC output amplitude control 04h <5:0> TINT<5:0> Sub picture tint control 05h <7> GRC Frame displa y : [ 0] off , [ 1] on <6:0> CONTRAST<6:0> Sub picture Y or R D AC output amplitude control 06h EXT_SC_SEL<1:0> Sub picture C-Sy nc sep. input selection : [0] Digital, [1] int. Auto slice [2] external (18 pin), [3] Int. analog 07h <7:6> <5:0> BG_START<5:0> Sub picture BGP position setting 08h <3:0> YD L<3:0> Sub picture Y/C delay adjust 09h <7:4> ADJ<3:0> Main/Sub s witch dela y control 0Ah DECODE Sub picture color decoder reset : [1] reset 0Bh <7:5> BGBY<2:0> Back ground U le v el setting <4:0> Y_OFFSE T<4:0> Sub picture Y bright control 0Ch <6:4> BGRY <2:0> Back ground V lev el setting <3:0> BGY<3:0> Back ground Y lev el setting 0Dh <7> VCHIP_ONLY V-chip decode mode : [0] o ff , [1] on <3:0> 0Eh 0Fh <7:4> SYNC_DELA Y<1:0> Sub picture sy nc.delay control <3> C_GAIN_SEL Sub picture chroma : [0] x1, [1] x2 <2> WDOF_KILLER_ON AFCBI TSEL Sub picture AFC t ime constant : [0] x2, [1] x1<6> <7> BITSEL Sub picture Y c lamp time constant : [0] x2, [1] x1 sym bol remarks <7> <6> YU VN_RGB_SEL <5:4> <3:0> HT<3:0> Sub picture display timing adjust <7:6> INPUT_SEL<1:0> Sub picture input s election : [0] YC, [ 1] N.A., [2]CVBS, [3] YUV <7:4> PEDESTU<3:0> Sub picture V pedestal lev el (2's c omp)PEDESTV<3:0> Sub picture U pedestal le v el (2's c omp) <5:0> ACC_LEVEL<5:0> Sub picture color decoder a mplitude <7> UV_FIL TER_OFF <6> SET_ACC Address 0Dh, 0Eh setting mode : [0] def ault, [ 1] enable to set <5:4> SYSTEM_MODE<1:0> Sy stem : [0]N TSC , [ 1]PAL-M, [2]PAL-N, [3] N.A. SET_SIZE Address 11h - 14h setting mode : [0] def ault, [ 1] enable to set<3> SET_VCHIP Address 15h - 17h setting mode : [0] def ault , [1] enable to set<2> <1:0> <7> AUTO_ENABLE Sy stem automatic judgment : [0] o ff , [ 1] on <6> BURST_CLOCK_MODE VCXO mode selection : [0] 1H based, [1] 2H based <5> <4> INV_WFF Inv ert s ub picture f ield def inition : [ 0] normal, [1] in v ert <3> INV_RFF Inv ert m ain picture f ield def inition : [ 0] normal, [1] in v ert <2> VMODE Vertical displa y m odewhen PAL-N input : [0] normal, [1] wide <1> PIP output mode selection : [0] YU V, [ 1] RGB bit address Reset val.1/9 ex. 0 0 0 0 0 0 20h 20h 32h 32h 00h 00h 0 0 Ah 0Eh 0h 0h Ch 0 0 0h 0h 0Fh 0h 0h PALN_DISABLE Main picture PAL-N : [ 0] enable, [ 1] disable <0> RFF _FIX AUTO_RFF _FIX Automatic 50/60H z Judgment : [0] enable, [ 1] disable Main picture f ield f ix : [0] not f ix, [1] f ix Sub picture U, V output f ilter : [0]on, [1]o ff 15h <1> EDGE_RES 0h 0h <0> CVF 0h 0h Internal chro ma comb f ilter : [ 0] on : [1] off Sub picture killer on when its v ert. s y nc lost : [0] on, [1] o ff f or test : 0 set only DCONT<1:0> Sub picture sy nc sep.threshold setting (analog/digital) YU V_COL<3:0> Sub picture color control parameter when YU V input MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

Internal register in f ormation (continuing) (preliminary) 11h <6:0> HY A<6:0> Sub picture horizontal displa y pixel 12h <7:0> VYA<7:0> Sub picture v ertical displa y line number 13h <7:2> HX<5:0> Sub picture horizontal capture position (coarse) <1:0> HP<1:0> Sub picture horizontal capture position ( f ine) 14h <7> <5:0> VXS<5:0> Sub picture sample start line 15h <7> - <6> PLUS <5> - <4:0> LINE_NU M<4:0> Data slicer line selection 16h <7:0> STB_DLY<7:0> Data slicer start bit detection parameter 17h <7:0> L_LEVEL<7:0> Data slicer data slice parameter 18h HPFOFF Sub picture Y output HPF : [0]on, [1]o ff 19h PINOE <7:6> MVC<1:0> Sub picture C-sy nc input mask period : 1Ah <7:6> NO_BST_LEVEL 1Bh 1Ch 1Dh <7:0> PINOE<7:0> 1Eh <7:0> - 1Fh <7:6> SYSTEM_STATE<1:0> <2> MAIN_BW Test use; Al way s '1' when 10h<5:4> = "00" (Read only)<1> <0> WDOF Sub picture V sy nc is : [0] present, [1] not present (Read onl y) 20h <7:6> - - <4> EDS_ACK2 EDS data f lag of ev en f ield : [ 0] no EDS, [1] EDS (Read onl y) <3> EDS_ACK1 EDS data f lag of odd f ield : [ 0] no EDS, [1] EDS (Read onl y) <2> SIGNAL_OK Test use (Read onl y) <1> READ_REQB Read request of ev en f ield : [0] no, [1] requesting (Read onl y) <0> READ_REQA Read request of odd f ield : [0] no, [1] requesting (Read onl y) 21h <7:0> PDB<15:8> Ev en f ield Sliced data upper 8 bit ( Read only) 22h <7:0> PDB<7:0> Ev en f ield Sliced data lo wer 8 bit (Read only) 23h <7:0> PDA<15:8> Odd f ield Sliced data upper 8 bit ( Read only) 24h <7:0> PDA<7:0> Odd f ield Sliced data lo wer 8 bit (Read only) RDOF Main picture V sy nc is : [0] present, [1] not present (Read onl y) f or test f or test : 0 set only f or test f or test f or test : 0 set only f or test : 0 set only <7:0> <4> <7> EDGE_ON Frame data independen t c ontrol : [0] disable, [1] enable <6:4> BGBY_EDGE<2:0> Frame data independen t B-Y data setting <3:0> BGY_EDGE<3:0> Frame data independen t Y data setting <7:5> BGRY _EDGE<2:0> Frame data independen t R -Y data setting <4> <3:0> FREE_RUN_ADJ <3:0> Frequency adjustm ent control when f ree run mode (2's comp) <7> SUB_PALM_JDGE<7:0> <3:0> BW_DET_LEVEL HADJ <3:0> <5> <4> <3> MAIN_PALN SUB_UNLOCK SUB_PALN <5> NOISE<1:0> WDOF Sub picture v ertical s y nc detection (Read onl y) Color state : [0] N TSC, [ 1] PAL-M, [2] PAL-N, [3]N.A.(Read onl y) Main is : [ 0] not PAL-N, [1] PAL-N (Read onl y) VCXO is : [0] Lock, [1] Unlock (Read onl y) Sub is : [ 0] not PAL-N, [1] PAL-N (Read onl y) 10h <7:6> <5:4> <3:0> PALRY <3:0> Threshold control of ident judgment of sub picture decoder Parameter setting f or PAL-M judgment No assignment Test use (Read onl y) Reset val. 1/9 ex.sym bol remarksbitaddress 00h 00h Sub picture V or B DAC output amplitude control Parameter setting f or PAL-M judgment 32h 11h 40h 82h 37h 44h 1Eh 29h E6h CROSS_SEL Sub picture read mode : [0] pixel based, [1] H based EXPORT<1:0> Ext. port (7 pin) : [0]"0" output, [1]"1" output [2or3] Sub BGP <5> INV_UV Inv ert U, V output v alue : [0] normal, [1] in v ert0h 0h AFC_OFF Sub picture AFC : [ 0] on, [1] o ff BW det. threshold setting : [0] o ff , [ 1] 16mV, [2] 32mV, [3] 64mV MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

Driv ing Method and Operating Spe cif ication f or Serial Interf ace Data (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is 'H' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) a. The byte format during data setting to M65665FP are shown as follows. In rig ht after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. b. The byte format during data reading from M65665FP are shown as follows. Before data reading from M65665FP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. The relation of input signal 32-pin ( Main-HD) and 33-pin ( Main-VD) is sho wn below 32-pin input (Main-HD) 33-pin input (Main-VD) [Even to Odd] +10u sec-10usec +21.75u sec +41.75u sec 33-pin input (Main-VD) [Odd to Even] +53.5u sec 20us 20us20us20us20us20us 20us 37.5us 20us 20us 20us 20us 20us 4H 1H end of ve rtical equali zation pul se VD input VD input prohibition time of changing 33-pin signal MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

<The examples of serial byte transmission format> (1) The writing opera tion of the setting data (AAh) into M65665 FP internal addre ss of 00h Transmi ssion Activation Confirmation of bu s free (DATA='H') is applied on CLk for the relea se of output state no S 24h A 00h A AAh A D E yes S : Ope ration of serial transmi ssion start A : Acknowledge detection D : Dumm y clock feed fo r the relea se of acknowledge output state E : Ope ration of serial transmi ssion completion (2) The writing opera tion of the setting data (FFh, 80h, EEh) into M65665 FP internal addre ss of 04h ~ 06h Transmi ssion Activation Confirmation of bu s free (DATA='H') is applied on CLk for the relea se of output state no yes S 24h A 04h A FFh A D E80hA A EEh (3) The reading opera tion of the setting data from M65665FP internal addre ss of 00h Transmi ssion Activation Confirmation of bu s free (DATA='H') is applied on CLk for the relea se of output state no yes S 24h A 00h A 25h AD E S $$h A' A' : Bus free operation by the master (micro proce ss or) MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

(4) The reading opera tion of the setting data from M65665FP internal addre ss of 04h ~ 06h Transmi ssion Activation Confirmation of bu s free (DATA='H') is applied on CLk for the relea se of output state no yes S 24h A 04h A A"25h AD E S $$h $$h A" $$h A' A" : Output 'L' operation by the master (micro proce ss or) <Timing Diagram> 1 2 3 4 5 6 7 8 9 1 SCL (4 pin) SDA (3 pin) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) ACK Detec. Bit7 (MSB) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Bit7 (MSB) ACK (2 pin) ACK (Read data) (2 pin) SDA (Read da ta) (3 pin) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Bit7 (MSB) MITSUBISHI ELECTRIC PICTURE-IN-PICTURE

SDIP42-P-600-1.78 Weight(g) JEDEC Code 4.1 Alloy 42/Cu Alloy 42P4B Plastic 42pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° –1 5 ° – – 5.5 e 42 22 211 E c e1 A2 A1 bb1 b2e L A SEATING PLANE D DETAILED DIAGRAM OF PACKAGE OUTLINE

SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42/Cu Alloy 42P2R-A Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .35 0 .05 0 .13 0 .317 .2 8 .6311 .3 0 .27 1 .0 2 .4 0 .15 0 .517 .4 8 .8 0 .9311 .5 0 .765 1 .4311 .4 2 .5 0 .2 0 .717 .6 8 .2312 .7 0 .15 0 b2 –. 5 0– 0° –1 0 ° e 42 22 211 HE E D be y F A A2 A1 L c e b2 Recommended Mount Pad Detail F

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