M65608E_14 ATMEL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 16

Technical content

Features

  • Operating Voltage: 5V
  • Access Time: 30, 45 ns
  • Very Low Power Consumption – Active: 600 mW (Max) – Standby: 1 µW (Typ)
  • Wide Temperature Range: -55⋅C to +125⋅C
  • 400 Mils Width Packages: FP32 and SB32
  • TTL Compatible Inputs and Outputs
  • Asynchronous
  • No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2@125°C
  • Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
  • QML Q and V with SMD 5962-89598
  • ESCC with Specification 9301/047

Description

The M65608E is a very low power CMOS static RAM organized as 131072 x 8 bits. Utilizing an array of six transistors (6 T) memory cells, the M65608E combines an extremely low standby supply current (Typic al value = 0.2 µA) with a fast access time at 30 ns over the full military temperature range. The high stability of the 6T cell pro- vides excellent protection against soft errors due to noise. The M65608E is processed according to the me thods of the latest revision of the MIL PRF 38535 or ESCC 9000. Rad. Tolerant 128Kx8, 5-Volt Very Low Power CMOS SRAM M65608E

4151P–AERO–11/12 M65608E Block Diagram Pin Configuration 32-lead DIL side-brazed 400 MILS 32-lead Flatpack 400 MILS I/O0 A12 A14 A16 NC I/O5 I/O6 I/O7 A10 A11 A13 CS2 VCC OE CS1 GND I/O2 I/O1 I/O3 I/O4 WE A15

Table 1. Pin Names Table 2. Truth Table Note: L = low, H = high, X = H or L, Z = high impedance.

4151P–AERO–11/12 M65608E

Electrical Characteristics

Recommended DC Operating Conditions Capacitance Note: Guaranteed but not tested. Electrostatic Discharge Voltage *NOTE: Stresses beyond those listed under "Abso- lute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. Operating Voltage Operating Temperature 5V + 10% -55 ⋅C to + 125⋅C Parameter Description Minimum Typical Maximum Unit VCC Supply voltage 4.5 5.0 5.5 V GND Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.5 0.0 0.8 V VIH Input high voltage 2.2 – VCC + 0.5 V Parameter Description Minimum Typical Maximum Unit Cin(Note:) Input low voltage ––8 p F Cout(Note:) Output high voltage ––8 p F

4151P–AERO–11/12 M65608E DC Parameters DC Test Conditions TA = -55°C to + 125°C; Vss = 0V; VCC = 4.5V to 5.5V Consumption Symbol Description Minimum Typical Maximum Unit IIX (1) 1. GND < Vin < VCC, GND < Vout < VCC Output Disabled. Input leakage current -1 – 1 µA IOZ(1) Output leakage current -1 – 1 µA VOL (2) 2. VCC min. IOL = 8 mA Output low voltage –– 0 . 4 V VOH (3) 3. VCC min. IOH = -4 mA. Output high voltage 2.4 – – V Symbol Description 65608E-30 65608E-45 Unit Value ICCSB (1) 1. CS1 > VIH or CS2 < VIL and CS1 < VIL. Standby supply current 2 2 mA max ICCSB1 (2) Standby supply current 300 300 µA max ICCOP (3) 3. F = 1/TAVAV, Iout = 0 mA, W E = OE = VIH, Vin = GND or VCC, VCC max. Dynamic operating current 110 100 mA max

4151P–AERO–11/12 M65608E AC Parameters AC Test Conditions AC Test Loads Waveforms Figure 1 Figure 2 Figure 3

4151P–AERO–11/12 M65608E Data Retention Mode Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and sup- ply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retent ion chip select CS1 must be held high within VCC to VCC -0.2V or, chip select CS2 must be held down within GND to GND +0.2V. 2. Output Enable (OE ) should be held high to keep the RAM outputs high impedance, mini- mizing power dissipation. 3. During power up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation volt- ages (4.5V). Timing Data Retention Characteristics Notes: 1. TAVAV = Read Cycle Time 2. CS1 = VCC or CS2 = CS1 = GND, Vin = GND/VCC, this parameter is only tested at VCC = 2V. 3. Parameters guaranteed but not tested Parameter Description Minimum Typical TA = 25 ⋅C Maximum Unit VCCDR V CC for data retention 2.0 – – V TCDR Chip deselect to data retention time 0.0 – – ns TR Operation recovery time TAVAV(1) –– n s ICCDR1 Data retention current at 2.0V –0 . 1 1 5 0 µ A ICCDR2(2) Data retention current at 3.0V –0 . 2 2 0 0 µ A

4151P–AERO–11/12 M65608E Write Cycle Note: 1. Parameters guaranteed, not te sted, with output loading 5 pF. Write Cycle 1 WE Controlled, OE High During Write Symbol Parameter 65608-30 65608-45 Unit Value TAVAW Write cycle time 30 45 ns min TAVWL Address set-up time 00n s m i n TAVWH Address valid to end of write 22 35 ns min TDVWH Data set-up time 18 20 ns min TE1LWH CS1 low to write end 22 35 ns min TE2HWH CS2 high to write end 22 35 ns min TWLQZ Write low to high Z (1) 81 5n s m a x TWLWH Write pulse width 22 35 ns min TWHAX Address hold from to end of write 00n s m i n TWHDX Data hold time 00n s m i n TWHQX Write high to low Z (1) 00n s m i n

4151P–AERO–11/12 M65608E Write Cycle 2 WE Controlled, OE Low Write Cycle 3 CS1 or CS2 Controlled Note: The internal write time of the me mory is defined by the overlap of CS1 Low and CS2 High and WE Low. Both signals must be actived to initiate a write and either signal can terminate a write by going inactived. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. Data out is high impedance if OE = VIH.

4151P–AERO–11/12 M65608E Read Cycle Note: 1. Parameters Guaranteed, not tested, with output loading 5 pF. Symbol Parameter 65608-30 65608-45 Unit Value TAVAV Read cycle time 30 45 ns min TAVQV Address access time 30 45 ns max TAVQX Address valid to low Z (1) 55 n s m i n TE1LQV Chip-select1 access time 30 45 ns max TE1LQX CS1 low to low Z(1) 33 n s m i n TE1HQZ CS1 high to high Z(1) 15 20 ns max TE2HQV Chip-select2 access time 30 45 ns max TE2HQX CS2 high to low Z (1) 33 n s m i n TE2LQZ CS2 low to high Z (1) 15 20 ns max TGLQV Output Enable access time 12 15 ns max TGLQX OE low to low Z(1) 00 n s m i n TGHQZ OE high to high Z(1) 81 5 n s m a x

4151P–AERO–11/12 M65608E Read Cycle 1 Address Controlled (CS1= OE Low, CS2=WE High) Read Cycle 2 CS1 Controlled (CS2=WE High) Read Cycle 3 CS2 Controlled (WE High, CS1 Low)

4151P–AERO–11/12 M65608E

Ordering Information

Note: 1. Contact Atmel for availability. Part Number Temperature Range Speed Package Flow MMC9-65608EV-30-E(1) 25⋅°C 30 ns SB32.4 Engineering Samples MMDJ-65608EV-30-E 25⋅°C 30 ns FP32.4 Engineering Samples 5962-8959847QZC -55⋅ to +125⋅°C 30 ns SB32.4 QML Q 5962-8959847QTC -55⋅ to +125⋅°C 30 ns FP32.4 QML Q 5962-8959818MZC -55⋅ to +125⋅°C 45 ns SB32.4 QML Q 5962-8959818MTC -55⋅ to +125⋅°C 45 ns FP32.4 QML Q 5962-8959847VZC -55⋅ to +125⋅°C 30 ns SB32.4 QML V 5962-8959847VTC -55⋅ to +125⋅°C 30 ns FP32.4 QML V 5962-8959818VZC -55⋅ to +125⋅°C 45 ns SB32.4 QML V 5962-8959818VTC -55⋅ to +125⋅°C 45 ns FP32.4 QML V 930104703 -55⋅ to +125⋅°C 30 ns SB32.4 ESCC 930104704 -55⋅ to +125⋅°C 30 ns FP32.4 ESCC 930104701 -55⋅ to +125⋅°C 45 ns SB32.4 ESCC 930104702 -55⋅ to +125⋅°C 45 ns FP32.4 ESCC MM065608EV-30-E 25⋅°C 30 ns Die Engineering Samples 5962-8959847Q6A -55⋅ to +125⋅°C 30 ns Die QML Q 5962-8959847V6A -55⋅ to +125⋅°C 30 ns Die QML V

4151P–AERO–11/12 M65608E Package Drawings 32-lead Flat Pack 400 Mils MM Min Max INCH Min Max A D 2.16 2.66 0.41 0.47 A DD1 H E E1LL e c BRAZE Q SS 1 b 0.13 20.63 21.03 20.11 20.27 c0 . 0 8 0 . 1 8 9.70 9.86 E 10.26 10.56 6.96 7.26 8.26 9.02 b0 . 3 8 0.48 0.70 MM Min Max INCH Min Max e L H Q S 1.19 1.35 e1 18.92 19.18 6.995 8.495 25.6 26.2 0.68 0.84 1.14 0.13 0.76 1.02 T T 0.08 T U U 1.27 0.085 0.105 0.016 .018 0.005 0.812 0.828 0.792 0.798 0.003 0.007 0.382 0.388 0.404 0.416 0.274 0.286 0.325 0.355 0.015 0.019 0.027 0.047 0.053 0.745 0.755 0.275 0.334 1.007 1.031 0.027 0.033 0.045 0.005 0.030 0.040 0.003 0.05 INDEX MARK =1.27x15 =0.05x15 R 0.76 0.030

4151P–AERO–11/12 M65608E Package Drawings 32-lead Side Braze 400 Mils

4151P–AERO–11/12 M65608E Document Revision History Changes from Rev. L to Rev. M 1. Change in “Consumption” on page 5. ICCOP. Changes from Rev. M to Rev. N 1. Update of footnotes under “Data Retention Characteristics” table 2. Update of Absolute Maximum Ratings section Changes from Rev. N to Rev. O 1. Update of “Ordering Information” section 2. Correction of typo erros in the note of “Write Cycle 3” section 3. Addition of headlines in pictures of “Read Cycle” section 4. Update of features section 5. Correction of typo error in the write si gnal, in the pin configuration section : W replaced by WE Changes from Rev. O to Rev. P 1. 32-lead Flat Pack package drawing updated on page 13. An index mark is now printed on the top lid to identify the pin n° 1.

4151P–AERO–11/12 Headquarters International Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza

77 Mody Road Tsimshatsui

Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309

78054 Saint-Quentin-en-

9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support aero@nto.atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection w ith Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING , BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON- INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LI ABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGE S (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and rese rves the right to make changes to specifi cations and product descriptions at any time without notice. Atmel does not make any commitment to update the informa tion contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not inte nded, authorized, or warranted for use as components in appli cations intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, and others are regi stered trademarks or trademarks of Atmel Corpora- tion or its subsidiaries. Other terms and pr oduct names may be trademarks of others.