M65580MAP MITSUBISHI | Alldatasheet

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Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes.

Description

The M65580MAP-XXXFP are semiconductor integrated circuits designed with CMOS silicon gate technology for NTSC television system, include 8bit MCU( M37272MA core) with a closed caption decoder and circuits needed for TV baseband signals(Video and Chroma) processor and Deflection in a chip. PCB area and EMI noise can be reduced by one chip and 80QFP, and internal connection of OSD signals. And it can realize a adjustment free system by built-in MCU and get a high performance adaptive YC separation by 1 line memory. The above technology makes its performance more stable and better. Feature

  • Y/C processor : 8bit Input, 10bit Output digital processing
  • Deflection processor : optimized system by conventional analog and digital mixed solution
  • ADC&DAC : 8bit high speed video ADC & 10bit high speed video DAC [MCU Block] MCU(single microcomputer) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass-production. And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O. It has a OSD, data slicer , and I C-BUS interface. So it is very useful for a channel selection system for NTSC TV with a closed caption decoder. [ASIC Block] ASIC block consists of the following blocks. (1) Analog frontend block ; Analog SW(2 CVBS(TV&EXT) inputs, Y/C signals to one signal, 2 channels 8 bit high speed video ADCs, and ACC amplifiers (2) Video and Chroma block ; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including sharpness, YNR, a high performance blackstretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit. (3) Deflection block ; A high performance sync separation by analog and digital mixed solution (4) Analog backend block ; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit. Application NTSC TV with a closed caption decoder PIN CONFIGURATION (TOP VIEW) M65580MAP-XXXFP NECK PROTECTOR HVCO F/B V-RAMP OUT AFC1 FILTER X-RAY PROTECT X-TAL CHROMA APC FILTER VDD(VCXO) B OUT VSS(OUTPUT) G OUT VDD(OUTPUT) R OUT VZ OUT TV IN VRB P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/AD3 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2 P25/AD5 HLF VHOLD CV IN CN VSS X IN X OUT P00/PWM0 P50/HSYNC IN/OUT P51/VSYNC P52/R P53/OUT1 P30/G P31/B P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 SCL HALF TONE OSD(B) IN OSD(G) IN FAST BLK OSD(R) IN V-PULSE OUT VSS(DEF) VDD(DEF) FBP IN H OUT SDA VSS VSS(DIGITAL) P16/AD2/TIM2 P15/AD1/INT3/FSCIN P20/SCLK/AD6 P21/SOUT/AD7 P22/SIN/AD8 RESETB P26/FSCIN/XCIN P27/XCOUT VCC FILT VDD(INPUT) Y SW OUT SYNC SEP IN RESETB(ASIC) CLK OUT VDD(DIGITAL) OSD CLK C IN VRT Y IN VSS(INPUT) EXT IN

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Block Diagram(Whole) 19 21 25 23 42 41 37 44 43 40 35 34 38 3933 VZ OUT Vss(OUTPUT) Vdd(OUTPUT) X-ray Protect Vss(Digital) Vdd(Digital) TV IN C IN Y IN EXT IN RESET B OUT G OUT R OUT SIGNAL PROCESSOR CLK(fsc) OUT

45 SDA

18 Y SW OUT

OSD(B) IN OSD(G) IN OSD(R) IN FAST BLK OSD H-SYNC FAST BLK OSD(R) OUT OSD(G) OUT OSD(B) OUT CV IN HLF VHOLD SCL SDA P12/SCL2 I/O PORT 63 64 65 66 67 68 69 71 72 73 74 4 770

8 P21/S OUT/AD7

78 CNVss

2 FILT

Vss(DEF) Vdd(DEF) Vrt Vrb Vss(Input) Vdd(Input) Vdd(VCXO) HVCO F/B 3bit Digital OSD HALF TONE VD HD FAST BLK Intelligent Monitor OSD HALF TONE VD HD FAST BLK P14/SDA2 P24/TIM2 P23/TIM3 P07/INT1 P06/INT2/AD4 P05/AD3 P04/PWM4 P03/PWM3 P02/PWM2 P01/PWM1 P00/PWM0 P22/S IN/AD8 P27/XCOUT P25/AD5 To TV IN of ASIC2in1 Tuner EEPROM CCD CVBS/YC inputRGB OUT

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Absolute maximum ratings VDD (MCU) Pd Kt Topr Tstg Supply voltage (MCU) Power dissipation Thermal derating Operating temperature Storage temperature V mW1460 14.6 -20 to 65 -40 to 125 -0.3 to 6.0 Symbol Parameter Ratings Unit VDD (ASIC5V) Supply voltage (ASIC5V) Supply voltage (ASIC3.3V) Input Voltage (MCU) Analog output current -30 V V mA VI (MCU) VO (MCU) IOH (MCU) IOL1 (MCU) IOL2 (MCU) VID (ASIC) IOUT (ASIC) Output Voltage (MCU) Circuit current (MCU) Circuit current (P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53) Circuit current (P11-P14) Digital input voltage -0.3 to 6.0 -0.3 to 4.0 -0.3 to Vcc+0.3 -0.3 to Vcc+0.3 V mA mA 0 to 1 (See note 1) mA V V -0.3 to Vcc+0.3 All voltage are based on Vss.Output transistors are cut off. Conditions 0 to 2 (See note 2) 0 to 6 (See note 2) VDD (ASIC3.3V) mW/ ˚C Recommended operating condition (Ta=-20 to 65 ˚C, unless otherwise noted) Supply voltage (MCU) (See note 3) Symbol Parameter Limits Unit V V P51, RESETB, XIN V V Min. Typ. Max. 4.75 5.0 5.25 V Supply voltage (Digital) 4.75 5.0 5.25 Supply voltage (Input) 3.13 3.3 3.47 Supply voltage (Output) Supply voltage (VCXO) 3.13 3.3 3.47 4.75 5.0 5.25 Supply voltage (DEF) V4.75 5.0 5.25 High Input voltage P00-P07, P10-P16, P20-P27, P50, Vcc V0.8Vcc High Input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-Bus) Vcc V0.7Vcc 0.4Vcc V0 (When using I2C-Bus) Low Input voltage SCL1, SCL2, SDA1, SDA2 0.3Vcc V0 0.2Vcc V0 1 mA VDD (Input) VDD (Digital) VDD (MCU) VDD (Output) VDD (VCXO) VDD (DEF) VIH1 (MCU) VIH2 (MCU) VIL1 (MCU) Low Input voltage P00-P07, P10-P16, P20-P27 VIL2 (MCU) VIL3 (MCU) Low Input voltage (See note 4) P50, P51, RESETB, XIN, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK High average output current (See note 1) P10-P16, P20-P27, P30, P31, P52, P53 IOH (MCU) High Input voltage RESETB, FBP IN, HALF TONE, Vcc V0.8VccVIH3 (ASIC) OSD(R/G/B) IN, FAST BLK VIL4 (ASIC) Low Input voltage RESETB, FBP IN, HALF TONE, 0.2Vcc V0 OSD(R/G/B) IN, FAST BLK

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. 0.88 1.0 0.5 1.5 1.46 2.0 65 7550250 100 125 150 AMBIENT TEMPERATURE Ta (˚C) THERMAL DERATING (MAXIMUM RATING) Thermal derating Symbol Parameter Limits Unit MHz Min. Typ. Max. Oscillation frequency (for CPU operation) XIN 7.9 8.0 8.1 Input frequency TIM2, TIM3, INT1, INT2, INT3 100 kHz 400 2.5 V1.5 f(XIN) (MCU) fhs1 (MCU) VI (MCU) Input amplitude video signal CVIN IOL1 (MCU) 2 mALow average output current (See note 2) P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53 IOL2 (MCU) Low average output current (See note 2) P11-P14 6 mA (See note 5) kHzOscillation frequency (for sub-clock operation) XCIN 29 32 35f(XCIN) (MCU) MHzOscillation frequency (for OSD standard clock) FSCIN 3.58FSC IN (MCU) fhs2 (MCU) Input frequency SCLK MHz1 Input frequency SCL1, SCL2 kHzfhs3 (MCU) 2.0 Note 1: The total current that flows out the MCU must be 20mA or less. 2: The total input current to MCU (IOL1 +IOL2 ) must be 30mA or less. 3: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8MHz. 4: Pin name in each parameter is described pin names. (1) Dedicated pins: dedicated pin name. (2) Double-/Triple-function ports. When the same limits: I/O port name. When the limits of function except ports are different from I/O port limits; function pin name. 5: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-Bus interface ports. P20-P22 have the hysteresis when these pins are used as serial I/O pins.POWER DISSIPATION Pd (W)

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. [MCU Block(M37272MA)] MCU(single microcomputers) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass- production. And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O. It has a OSD, data slicer , and I C-BUS interface, so it is very useful for a channel selection system for NTSC TV with a closed caption decoder.

Features

  • Memory size (ROM correction memory:64bytes included) (at 8 MHz oscillation frequency)
  • Multi-master I (at Vcc=5.5V, 8MHz oscillation frequency, OSD on, and Data slicer on)
  • Closed caption data slicer
  • OSD function Kinds of characters 254 kinds Character display area CC mode : 16x26 dots OSD mode : 16x20 dots Kinds of character sizes CC mode : 1 kind OSD mode : 8 kinds Kinds of character colors 8 colors(R,G,B) (coloring unit: a character) Kinds of background colors CC mode : 1 kind(black) OSD mode : 8 kinds(possible to select color in character unit) Display position horizontal : 128 levels Vertical : 512 levels Attribute CC mode : smooth italic, underline, flash, automatic solid space OSD mode : border(black) Kinds of raster colors 8 kinds Smooth roll-up Window function

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. CVBS(TV/EXT) signals or Y/C signals input to this IC are converted to 8 bit digital signal by 2 channels high speed video ADCs. These signals are input to digital section to obtain high performance R/G/B signals. First, CVBS signals are separated to high quality Y/C signals by 2 dimensional adaptive YC separation circuit, and then Y/C signals are converted to R-Y&B-Y signals by digital chroma decoder, after that, to R/G/B signals by RGB matrix circuit. These signals are mixed with OSD signals come from MCU block, are converted to analog R/G/B signals by 3 channel 10 bit high speed video DACs. In deflection block, to get a better Horizontal & Vertical signals, a conventional analog solution by analog CMOS technology is used. ASIC block consists of the followings blocks. (1) Analog frontend block ; Analog SW(2 CVBS(TV&EXT) inputs, Y/C signals to one signal), 2 channels 8 bit high speed video ADCs , and ACC amplifiers (2) Video and Chroma block ; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including sharpness, YNR, a high performance blackstretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit. (3) Deflection block ; A high performance sync separation by analog and digital mixed solution (4) Analog backend block ; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit. [Video/Chroma Block]

  • Built-in 1 Video SW for TV/EXT signal input
  • 2 additional pins for S(Y/C) input
  • YUV input signal available ( T.B.D )
  • 2 channel 8 bit Video ADCs for CVBS(TV&EXT) or Y/C signal inputs
  • Built-in adaptive 2 line comb filter(2DYCS) => Few dot crawl&crosscolor, and clear color transition
  • Built-in a high performance Blackstretch => Dynamic & detailed picture
  • Digital Luminance delay circuit => stable Y/C timing adjustment
  • Built-in VCXO circuit(4fsc)
  • High resolution R/G/B output => Built-in 10bit high speed Video DACs
  • Internal connection of 8 color digital OSD ( R/G/B, F.B, H.T )
  • Reference CLK output for tuner (fsc or 4MHz)
  • Built-in YNR ( about fsc±1MHz)
  • Gamma correction(for R/G/B signals) [Deflection Block]
  • Analog(conventional) sync separation => Better performance by abundant experience
  • Double AFC Circuit => Stable Horizontal scanning
  • Built-in Horizontal reference Oscillator => No ceramic resonator and Adjustment free
  • HD and VD pulse by Countdown => Stable HD&VD
  • Built-in digital Vramp generator [List of main I C bus controllable Items]
  • Chip : Power-down mode
  • Analog Input Stage : CVBS/Y&C Input SW
  • Luminance Processing : Sharpness, Blackstretch
  • Chroma Processing : Color, Tint, Killer level
  • RGB Matrix : ACL, OSD Input Level, Contrast, Brightness
  • Analog Output Stage : Drive adj.(R/G/B), Cutoff adj.(R/G/B)
  • Deflection Block : H-Phase, V-size, V-shift, V-Linearity [ASIC Block]

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. ASIC Block Detailed Diagram

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Function and Outline of ASIC Block Chip Power down mode : 3 modes [ PD0 & PD1 & PD2 ] Service SW : stop of Vertical(Vramp) output ( For cutoff adjustment ) Analog Block

  • Input stage => CVBS&Y/C input signals Input level (CVBS) : 1.23Vp-p (173IRE) @max. / 1.0Vp-p @typ. Input level (Y/C) : Y:1.00Vp-p (140IRE) @typ./ C:0.7Vp-p @typ.
  • Output stage => RGB output signals Output level : 0.7 Vp-p (typ.) Drive(R&G&B) : -3 to +4 dB by 7bit (White Balance) Cutoff(R&G&B) : 0.5 V by 9bit (Start lighting point) Digital Block
  • 2DYCS Adaptive YC separation by using of 1H line memory and original algorithm
  • Luminance processing Contrast : 0 to 200 LSB by 7bit Brightness : -20 to 20 LSB by 8bit (Pedestal DC level) Sharpness : 0 to 3 dB by 5bit (by 0, 70, 140, 210ns) Delay adjustment : 0 to 210 ns by 2bit(70ns step) to Chroma signal Blackstretch : 3 selectable stretch point [ Stretch areas ( 0 to 25/30/40IRE ), Through areas ( 25/30/40IRE ~ ) ] 4 selectable blackstretch curves ( 1/4, 2/4, 3/4, 4/4)
  • Chroma processing Tint : -45 to 45 degree by 7bit => about 0.7 degree : Variable demodulator (R-Y) axis (-22.5 to +22.5 degree by 6bit => about 0.7 degree) Color : 0 to 200 % by 7bit
  • RGB matrix : Matrix(R-Y signal) ratio selectable (12/8, 13/8, 14/8) ACL : Automatic Contrast Limiter by MCU port(ADC) and I C bus EXT/RGB : clip to 7LSB @ data < 0Fh BlueBack : ON/OFF selectable Mute : ON/OFF of R/G/B output Neck Protector : R/G/B output to zero( no signal) Deflection Block
  • Horizontal Output AFC2 phase : +5 to -5µs by 5bit Hold => Shut down : fh@Hold-down : in about 16.5KHz => fh@Shutdown : H-STOP AFC1 gain : Normal/High selectable for VTR skew
  • Vertical Output V position : 0 to 16 H by 3 bit => 2H unit(connected with BLK) V size : 1.4 to 2.6 V by 7bit Linearity : 0 to 30 % by 7bit

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Application Examples 0.1u Video det out (1.23Vp-p) 0.1u 0.1u 0.1u 0.1u 560 0.1u +200V FBT ACL In 0.1u DY to H DRIVE 0.1u H-Pulse Out SDA SCL 10K 10K EXT In (1.23Vp-p) Y In (1.00Vp-p) C In (0.70Vp-p) FBP in 1.5K 1.5K 1.5K Reset 7480 76777879 6569 6566676870717273 25 29282726 30 35 3634333231 40393837 39 40 CLK-2 Out CLK(fsc) Out Vdd(Dig) Vss(Dig) Sync Sep. In CVBS(x2) Out Vdd(Input) TV in MCU Analog Block ASIC Reset In P22/Sin/AD8 P21/Sout/AD7 P20/SCLK/AD6 P15/AD1/INT3 Reset In P26/FSCin P27/Xcout VCC Vss(Input) EXT in Vrt Vss FILT Digital Block P16/AD2/TIM2 (Int. Mon. In/Out) R(OSD) in F.B in SDA SCL G(OSD) in B(OSD) in P51/Vsync Vdd(Def) Vss(Def.) P52/Rout P53/OUT1 P30/Gout P31/Bout VD out P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 H.T in P50/Hsync In/out H OUT P00/PWM0 Yin FBP IN NECK PRO 7475 3.3V FBT REG 3.3V REG REG 3.3V SW REG REG 150V POWER ON H 15p15p 470p 0.1u 0.1u 470p 0.01u 470p 0.1u 0.01u

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes.

Electrical characteristics

ICC50 5.0V supply current - - 3,14, 33,42 102 116 130 mA Supply of MCU, Digital, VCXO and Deflection ICC33 3.3V supply current - - 18, 29 47 56 65 mA Supply of A/D and D/A VIDEO Standard conditions of video character - - - - - - - 2AGTV Video SW output level (TV input) 26 SG.A 18 1.5 1.7 1.9 Vpp 2AGEV Video SW output level (External input) 20 SG.A 18 1.5 1.7 1.9 Vpp Vtyp Video standard output 26 SG.A 28,30, 32 590 740 890 mV pp FBY Video frequency characteristics 26 SG.B 28,30, 32 -3 0 3 dB f=5MHz Y/C1 Y/C separation function 126 SG.E 28,30, 32 - -30 -20 dB feb=fec=fsc Y/C2 Y/C separation function 226 SG.E 28,30, 32 -3 0 3 dB feb=fsc, fec=fsc±1/2fH Y/C3 Y/C separation function 326 SG.E 28,30, 32 - -30 -20 dB feb=fsc, fec=fsc±fH YDL0 Y total delay time 26 SG.A 28,30, 32 2.4 3.0 3.6 µsec YDL1 Y delay time 1 26 SG.A 28,30, 32 50 70 90 nsec YDL1=measure – YDL0 YDL2 Y delay time 2 26 SG.A 28,30, 32 50 70 90 nsec YDL2=measure – YDL1 YDL3 Y delay time 3 26 SG.A 28,30, 32 50 70 90 nsec YDL3=measure – YDL2 GTnor Video tone control characteristic 1 26 SG.B 28,30, 32 640 800 960 mV f=2.5MHz GTmax Video tone control characteristic 2 26 SG.B 28,30, 32 1 2.5 4 dB f=2.5MHz GTmin Video tone control characteristic 3 26 SG.B 28,30, 32 -7 -4 -1 dB f=2.5MHz BLS Black stretch characteristic 26 SG.D 28,30, 32 20 50 80 mV Vy=0.18V, 45H=80h(BLS ON) / 00h(BLS OFF) HT Half Tone function 26 SG.A 28,30, 32 -9 -6 -3 dB Symbol Parameter Input signal Pins SG Test point Limits Min. Max.Typ. Unit Remarks (Ta=25ºC, Vdd=5.0V, 3.3V)

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Standard condition of chroma parameter - - - - - - - 5DH=03h Chroma standard output (R-Y) 26 SG.E 28 155 180 205 mV feb=fec+50kHz Chroma standard output (B-Y) 26 SG.E 32 275 310 345 mV ACC characteristic 1 26 SG.E 28 -3 0 3 dB Veb, Vec : +6dB of typical input level ACC characteristic 2 26 SG.E 28 -3 0 3 dB Killer operation input level26 SG.E 28 -40 -35 -30 dB Color residual at Killer on26 SG.E 28 - -40 -28 dB APC pull-in range (upper)26 SG.E 28 400 - - Hz APC pull-in range (lower)26 SG.E 28 - - -400 Hz Demodulated output ratio26 SG.E 28,32 0.47 0.57 0.67 - Demodulation phase angle 26 SG.F 28,32 85 90 95 deg Color control characteristic 1 26 SG.E 28 160 200 240 % Color control characteristic 2 26 SG.E 28 - 0 10 % TINT control characteristic 1 26 SG.F 28,32 30 45 60 deg TINT control characteristic 2 26 SG.F 28,32 -60 -45 -30 deg CLK output frequency 26 SG.C 15 3.578 3.579 3.580 MHz CLK output amplitude 26 SG.C 15 350 500 650 mV pp CnorB ACC1 APCL DEMR VikN APCU ACC2 KillP Vclk TC2 Fclk Ccon 2 TC1 DEMP Ccon 1 CnorR feb=fec+50kHz Veb, Vec : -20dB of typical input level Veb, Vec : variable feb=fec : variable feb=fec+50kHz feb=fec : variable Veb = 0mV feb=fec+50kHz feb=fec+50kHz Symbol Test point SGPins Input signalParameter Limits Min. Typ. Max. Unit Remarks CHROMA

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Limits Min. Typ. Max. RGB Standard condition of RGB parameter - - - - - - - VPED Output Pedestal voltage 26 SG.D 28,30, 32 2.7 3.0 3.3 V Vy = 0.0V MTXRB Matrix ratio R/B 26 SG.H 28,32 0.74 0.92 1.10 - MTXGB Matrix ratio G/B 26 SG.H 30,32 0.24 0.33 0.42 - GYmax Contrast control characteristic 1 26 SG.D 28,30, 32 160 200 240 % Vy =0.286V GYmin Contrast control characteristic 2 26 SG.D 28,30, 32 - 0 10 % Vy =0.286V GYEclip Contrast control characteristic 5 48,49, 51 SG.G 28,30, 32 250 300 350 mV Lum max Brightness control characteristic 2 26 SG.D 28,30, 32 100 150 200 mV Lum min Brightness control characteristic 3 26 SG.D 28,30, 32 -200 -150 -100 mV Vy =0.286V D(R)1 R Drive control D(G)1 G Drive control D(B)1 B Drive control D(R)2 R Drive control D(G)2 G Drive control D(B)2 B Drive control C(R)1 R Cut off control characteristic 1 26 SG.D 28 210 260 310 mV Vy =0.286V C(G)1 G Cut off control characteristic 1 26 SG.D 30 210 260 310 mV Vy =0.286V C(B)1 B Cut off control characteristic 1 26 SG.D 32 210 260 310 mV Vy =0.286V C(R)2 R Cut off control characteristic 2 26 SG.D 28 -310 -260 -210 mV Vy =0.286V C(G)2 G Cut off control characteristic 2 26 SG.D 30 -310 -260 -210 mV Vy =0.286V C(B)2 B Cut off control characteristic 2 26 SG.D 32 -310 -260 -210 mV Vy =0.286V OSD(R) OSD (R) output level 51 SG.G 28 500 600 700 mV pp OSD(G) OSD (G) output level 49 SG.G 30 500 600 700 mV pp OSD(B) OSD (B) output level 48 SG.G 32 500 600 700 mV pp SOSD1 OSD speed characteristic 48,49, 51 SG.G 28,30, 32 - 100 200 nsec SOSD2 OSD speed characteristic 48,49, 51 SG.G 28,30, 32 - 100 200 nsec OFF(R) Offset voltage between R and OSD(R) - - - -50 0 50 mV Difference at pedestal level OFF(G) Offset voltage between G and OSD(G) - - - -50 0 50 mV Difference at pedestal level OFF(B) Offset voltage between B and OSD(B) - - - -50 0 50 mV Difference at pedestal level NECK Neck protector function threshold voltage 26 SG.A 40 1.0 1.3 1.6 V while monitoring at pins 28, 30, 32 Symbol Test point SGPins Input signalParameter RemarksUnit

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. DEF Standard condition of defrection parameter - - - - - - - fH1 Horizontal free-running frequency 1 - - 44 15.53 15.73 15.93 kHz fH2 Horizontal free-running frequency 2 - - 44 13.72 14.32 14.92 kHz fH3 Horizontal free-running frequency 3 - - 44 17.25 17.85 18.45 kHz FPHU Horizontal pull-in range (upper) 17 SG.I 44 250 500 - Hz Vary frequency of input signal. FPHL Horizontal pull-in range (lower) 17 SG.I 44 - -500 -250 Hz Vary frequency of input signal. HPV Horizontal pulse amplitude26 SG.A 44 4.0 4.5 5.0 V HPTW Horizontal pulse width 26 SG.A 44 19.3 22.3 25.3 µsec HPD Horizontal pulse duty cycle 26 SG.A 44 30 35 40 % HPT1 Horizontal pulse timing 126 SG.A 44 8.7 10.7 12.7 µsec HPT2 Horizontal pulse timing 226 SG.A 44 2.2 4.2 6.2 µsec HPT3 Horizontal pulse timing variable range 26 SG.A 44 4.5 6.5 8.5 µsec HPT2 – HPT1 HDOWN Hold down function threshold voltage 26 SG.A 36 3.0 3.1 3.2 V while monitoring at pin 44 SDOWN Shut down function threshold voltage 26 SG.A 36 3.3 3.5 3.7 V while monitoring at pin 44 fV Vertical free-running frequency - - 38 55 60 65 Hz SVC Service mode function - - 38 2.5 2.8 3.1 V FPVU Vertical pull-in frequency (upper) 17 SG.J 38 - - 63 Hz Vary frequency of input signal. FPVL Vertical pull-in frequency (lower) 17 SG.J 38 57 - - Hz Vary frequency of input signal. VRsi 1 Vertical ramp size 26 SG.A 38 2.1 2.5 2.9 Vpp VRsc 1 Vertical ramp size control range 1 26 SG.A 38 20 27 35 % VRsc 2 Vertical ramp size control range 2 26 SG.A 38 -35 -27 -20 % VLin 1 Vertical ramp Linearity control range 1 26 SG.A 38 -5 0 5 % VLin 2 Vertical ramp Linearity control range 2 26 SG.A 38 19 24 29 % VRpo 1 Vertical ramp position control range 1 26 SG.A 38 0 50 200 µsec VRpo 2 Vertical ramp position control range 2 26 SG.A 38 790 940 1090 µsec (Measured value) – (Vrpo 1) VW Vertical pulse width 26 SG.A 52 0.35 0.53 0.65 msec VBLKW Vertical blanking width 26 SG.A 28,30, 32 1.52 1.64 1.76 msec WVSS Minimum vertical sync detection width 26 SG.A 11 13 18 23 µsec Symbol Parameter Input signal SGPins Test point Max.Typ.Min. Limits RemarksUnit

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Electrical characteristics (MCU part) (Vcc=5V±10%, Vss = 0V, f(XIN)=8MHz, Ta=–20˚C to 65˚C, unless otherwise noted) Max. 200 100 0.4 0.4 0.6 HIGH output voltage LOW output voltage LOW output voltage P1 1–P14 Hysteresis (See note 1) LOW input leak current I 2C-BUS • BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) Symbol Parameter Test conditions W ait mode System operation Power source current Test circuit Min. 2.4 Limits Typ. 0.5 Unit mA mA V V V µA µA µA HIGH input leak current P00–P07, P10–P16, P20–P27, P50, P51, RESET RESET, P50–P51, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK , SCL1, SCL2, SDA1, SDA2 P00–P07, P10–P16, P20–P27, P50, P51, RESET P00–P07, P10, P15, P16, P20–P27, P30, P31, P52, P53 P10–P16, P20–P27, P30, P31, P52, P53 µA VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32 kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32 kHz, Low-power dissipation mode set VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 8 MHz OSD OFF Data slicer OFF OSD ON VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 5.0 V IOL = 3 mA IOL = 6 mA VCC = 4.5 V VCC = 4.5 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V ICC VOH VOL IIZH IIZL VT+ – VT– R BS Notes 1: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins. 2: Connect 0.1µF or more capacitor externally between the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.1µF or more capacitor externally between the pins VCC –CNV SS . 3: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 4: Pin names in each parameter is described as bellow. 130 1.3 (1) Dedicated pin: dedicated pin names. (2) Double-/triple-function ports

  • When the same limits: I/O port name.
  • When the limits of functions except ports are different from I/O port limits: function pin name.

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. A6 A5 A4 A3 A2 A1 A0 R/W 1 0 1 1 1 0 1 1/0 DATA HEX BIN D7 D6 D5 D4 D3 D2 D1 D0 INITIAL H Stop 00H 00000000 0 0 0 0 0 0 1 0 02H X-ray Enable YUV input Y/C input EXT input TV input Y/C through 01H 00000001 0 0 0 0 1 0 0 0 08H Ped Clamp 02H 00000010 0 0 0 0 1 0 0 0 08H Shrapness Gain (Front) 04H 00000100 V1 V0 V1 V0 V0 V0 V0 V0 A0H Shrapness Gain (Rear) 05H 00000101 V1 V0 V1 V0 V0 V0 V0 V0 A0H (not asigned) YNR SW 06H 00000110 V0 V0 V0 V0 V0 V0 V0 V0 00H 07H 00000111 V0 V0 V0 V1 V0 V1 V0 V1 15H (not asigned) Tint Control 08H 00001000 V0 V0 V1 V0 V1 V0 V0 V1 29H (not asigned) Color Control 09H 00001001 V0 V0 V1 V0 V1 V0 V0 V0 28H (not asigned) Contrast Control 0AH 00001010 V0 V0 V1 V1 V1 V0 V1 V1 3BH 0BH 00001011 V0 V0 V0 V1 V1 V1 V1 V0 1EH 0CH 00001100 V1 V0 V0 V1 V1 V1 V1 V0 5EH 0DH 00001101 V0 V0 V0 V1 V1 V1 V1 V0 0EH 0EH 00001110 V1 V0 V0 V0 V0 V0 V0 V0 80H (not asigned) H Free AFC1 Gain 0FH 00001111 0 0 0 0 1 0 0 0 08H (for evaluation) 2D Y/C 10H 00010000 0 0 0 0 0 0 0 0 00H (not asigned)Black Stre. SW 11H 00010001 V0 V1 V0 V0 V0 V0 V0 V0 40H RGB Mute 12H 00010010 1 0 0 0 0 0 0 0 80H Service SW 13H 00010011 0 0 0 1 0 0 0 0 10H V-Blanking Stop 14H 00010100 0 1 0 0 0 0 0 0 40H V-Ramp Invert 15H 00010101 1 1 1 1 1 1 1 1 FFH 16H 00010110 00H CutOff(R) MSB 17H 00010111 00H 18H 00011000 00H CutOff(G) MSB 19H 00011001 00H 1AH 00011010 00H CutOff(B) MSB 1BH 00011011 00H 1CH 00011100 0 0 0 0 0 0 0 0 00H I/M(D) Enable 1DH 00011101 0 0 0 0 0 0 0 0 00H 01010001 0 0 0 0 0 0 0 0 00H NOTE: V0 / V1 ==> V- LATCH BIT D7 D6 D5 D4 D3 D2 D1 D0 60H 01100000 KILLER H COINCI V COINCI B_W IIC_STILL MV_180 DET NZ K_MONI 61H 01100001 62H 01100010 B2 ROM MSB 63H 01100011 SUB ADDRESS SUB ADDRESS (for evaluation) (for evaluation) Hold Down Level (not asigned) Intelligent Monitor (Analog) (not asigned) Intelligent Monitor (Digital) H VCO Adjust B2 ROM (not asigned) C Gain (not asigned)BLKDETV Gamma Control(inhibited) V-Ramp Linearity V-Ramp Size V-Shift Drive (B) Cut Off (B) Cut Off (R) Drive (R) Cut Off (G) Drive (G) H Phase Control (not asigned) RGB Matrix Ratio OSD Level (G) OSD Comp OSD Level (B) Brightness Control (not asigned) Sharpness Limitter Level Half Tone OSD Level (R) Sharpness Delay (Rear) Sharpness Delay (Front) Y DL Time Adj. YNR Limitter Level Power Down Mode(not asigned) (for evaluation) Sync-tip ClampVRT Voltage(not asigned) I C Bus Table SLAVE ADDRESS= BAH(WRITE), BBH(READ) WRITE TABLE(input bytes) READ TABLE(output bytes) 51H (inhibited) V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Bus function WRITE FUNCTION BIT SUB ADD DATA DISCRIPTION INITIAL NOTE H STOP 1 00H D0 Horizontal output switch (0: H OUT, 1: H STOP) 0 Power Down 2 00H D1-D2 Power down mode control (0: normal, 1: PD0, 2: PD1, 3: PD2) 01 Input Video SW 4 01H D3-D6 Video SW Selector (1: TV, 2: EXT, 4: Y/C input, 9: YUV input) 0001 X-ray Enable 1 01H D7 X-ray protect function switch (0: X-ray Protect OFF, 1: X-ray Protect ON)0 Y/C through 1 01H D2 Y/C separation input switch (0: Y/C Sep ON, 1: Y/C Sep. through) 0 Sync-tip Clamp 3 02H D0-D2 Sync-tip clamp switch (0: Clamp ON, 1: TV clamp OFF, 2: EXT clamp OFF, 4: Y clamp OFF)000 Ped Clamp 1 02H D7 Pedestal clamp switch (0: Pedestal clamp OFF, 1: Pedestal clamp ON) 0 VRT Voltage 2 02H D3-D4 Reference voltage adjustment for A/D 01 Sharpness Gain (Front) 6 04H D0-D5 Over-shoot gain control by 6bit 100000 V Latch Sharpness Delay (Front) 2 04H D6-D7 Over-shoot width control (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns) 10 V Latch Sharpness Gain (Rear) 6 05H D0-D5 Pre-shoot gain control by 6bit 100000 V Latch Sharpness Delay (Rear) 2 05H D6-D7 Pre-shoot width control (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns) 10 V Latch YNR SW 7 06H D4 YNR control switch (0: YNR OFF, 1: YNR ON) 0 V Latch YNR Limiter Level 1 06H D0-D3 YNR limiter level control 0000 V Latch Y DL Time Adj. 2 06H D5-D6 Delay time adjustment of luminance signal (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns)00 V Latch Sharpness Limiter Level 6 07H D0-D5 Maximum level control of sharpness 010101 V Latch Tint Control 7 08H D0-D6 Tint Control by 7bit 0101001 V Latch Color Control 7 09H D0-D6 Color Saturation control by 7bit 0101000 V Latch Contrast Control 7 0AH D0-D6 Contrast control by 7bit 0111011 V Latch OSD Level (R) 6 0BH D0-D5 Digital OSD (R) level adjustment by 6bit 011110 V Latch Half Tone 2 0BH D6-D7 Setting of Half Tone mode 00 V Latch OSD Level (G) 6 0CH D0-D5 Digital OSD (G) level adjustment by 6bit 011110 V Latch RGB Matrix Ratio 2 0CH D6-D7 RGB Matrix ratio control 10 V Latch OSD Level (B) 6 0DH D0-D5 Digital OSD (B) level adjustment by 6bit 011110 V Latch OSD Comp 2 0DH D6-D7 Digital OSD threshold voltage control of input signal 00 V Latch Brightness Control 8 0EH D0-D7 Brightness control by 8bit 10000000 V Latch AFC2 H Phase 5 0FH D0-D4 Horizontal phase adjustment by 5bit 01000 AFC1 Gain 1 0FH D5 Horizontal AFC gain switch (0: Low, 1: High) 0 H-free 1 0FH D6 Horizontal forced free-running mode switch (0: OFF, 1: Forced Free-running)0 2D Y/C 1 10H D4 Y/C separation mode switch (0: Y/C Sep ON, 1: Y/C Sep. through) 0 Black Stretch SW 1 11H D6 Black Stretch function ON/OFF switch (0: OFF, 1: ON) 0 Gamma Control 1 12H D0-D3 RGB gamma threshold control (0:Gamma OFF) 0000 RGB Mute 1 12H D7 RGB signal mute ON/OFF switch (0: Mute 1: RGB output) 1 Hold Down Level 3 13H D0-D2 Hold Down level adjustment by 3bit 000 V Shift 3 13H D4-D6 V RAMP start timing adjustment 2Line/Step 001 Service SW 1 13H D3 Service mode switch (0: Vertical output ON, 1: Vertical output OFF) 0 V-Ramp Size 7 14H D0-D6 V-Ramp amplitude adjustment by 7bit 1000000 Test 1 14H D7 No use for customer (Test mode) 0 V-Ramp Linearity 7 15H D0-D6 V-Ramp linearity adjustment by 7bit 1111111 V-Ramp Invert 1 15H D7 V-Ramp polarity switch 1 Cut Off(R) 9 16H D0-D7 R OUT pedestal level adjustment by 9bit 00000000 17H D7 0 Drive(R) 7 17H D0-D6 R OUT amplitude adjustment by 7bit 0000000 Cut Off(G) 9 18H D0-D7 G OUT pedestal level adjustment by 9bit 00000000 19H D7 0 Drive(G) 7 19H D0-D6 G OUT amplitude adjustment by 7bit 0000000 Cut Off(B) 9 1AH D0-D7 B OUT pedestal level adjustment by 9bit 00000000 1BH D7 0 Drive(B) 7 1BH D0-D6 B OUT amplitude adjustment by 7bit 0000000 Intelligent Monitor (Analog)4 1CH D0-D3 Intelligent Monitor (Analog) mode selector 0000 Intelligent Monitor (Digital)5 1DH D0-D4 Intelligent Monitor (Digital) mode selector 00000 Intelligent Monitor(D) Enable1 1DH D5 Intelligent Monitor (Digital) function switch (0: OFF, 1: ON) 0 H VCO Adj. 8 51H D0-D7 H VCO free-running frequency adjustment by 8bit 00000000 Read K_MONI 1 60H D0 Color/Killer condition (1: color output, 0: Killer (color off) ) DET_NZ 1 60H D1 Noise Killer det. output (1: Noise Killer ON) MV_180 1 60H D2 Reversed Burst signal (all reversed) det. output (1: Reversed Burst) IIC_STILL 1 60H D3 VCR Still mode det. output (1: Still mode) B_W 1 60H D4 PLL Killer (Chroma) det. output (1: PLL Killer ON) V COINCI 1 60H D5 Vertical Coincidence det. output (1: V Coincident) H COINCI 1 60H D6 Horizontal Coincidence det. output (1: H Coincident) KILLER 1 60H D7 C-processor Killer det. output (1: C-pro Killer ON) B2ROM 9 61H D0-D7 B2ROM output 62H D7 C Gain 2 62H D0-D1 ACC amplifier status BLKDETV 4 63H D4-D7 Black det. output of Black Stretch circuit V Latch V Latch V Latch V Latch V Latch V Latch

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. M65580MAP I 2C bus Standard data Sub address data Sub address data Sub address data 00h 00 30h 20 50h 00 01h 08 31h 05 51h 00 02h 08 32h 04 52h 00 03h 21 33h 81 53h 35 04h C0 34h 8D 54h 22 05h C0 35h 63 55h 94 06h 00 36h 79 56h 14 07h 15 37h 50 57h A6 08h 40 38h 55 58h 00 09h 40 39h 25 59h A6 0Ah 40 3Ah 21 5Ah 00 0Bh 1E 3Bh 19 5Bh 00 0Ch 9E 3Ch B3 5Ch 00 0Dh 1E 3Dh 0F 5Dh 80 0Eh 80 3Eh 06 0Fh 10 3Fh 08 10h 10 40h 00 11h 4A 41h 01 12h 8D 42h C0 13h 00 43h 04 14h 40 44h 64 15h 40 45h 3D 16h 00 46h 15 17h C0 47h 00 18h 00 48h 83 19h C0 49h 00 1Ah 00 4Ah A0 1Bh C0 4Bh 00 1Ch 00 4Ch 15 1Dh 00 4Dh 01 4Eh 6E 4Fh 38

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins DESCRIPTION OF PIN Vss (MCU)1 Power source for MCU. Y FILT2 Vcc (MCU)3 5.0V ± 5% Power source for MCU. P27/XCOUT74 4 P26/FSCIN/ XCIN Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Y 6 Y C A RESETB6 VOL = 0V : Reset state VOH = 5V : Release from Reset state CMOS INPUT Impedance>100k P22/SIN/AD87 P21/SOUT/AD88 P20/SCLK/AD69 P16/AD2/TIM211 CMOS IN/OUT 1 Impedance>100k (input) Impedance 250 (output) Intelligent monitor output (Analog/Digital) C A Y CMOS IN/OUT 1 Impedance>100k (input) Impedance 250 (output) Vss (Digital)12 0V P15/AD1/ INT3/FSCIN Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins OSD CLK Y C A CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) Vdd (Digital)14 Impedance 400 ESD PROTECT CLK OUT15 15 RESET16 Y C.Sync IN17 Sync Sep. input Impedance=N.A. ESD PROTECT CMOS INPUT Impedance>100k VIL = 0V : Reset state VIH = 5V : Release from Reset state 5.0V ± 5% Power source for Digital block. DC 2.5V Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins CVBS OUT18 Impedance 150 3.3V ± 5% Vdd (Input)19 Power source for A/D etc. Impedance=N.A.EXT(CVBS) IN Vss (Input)21 Power source for A/D etc. TV(CVBS) IN 22Y IN 26 26 VRT23 VRB25 Impedance>5023 Impedance 7.5k C IN24 DC : 0.55V (sync) AC : 1.75Vp-p (typ.) DC : 1.7V (VRT) 0.5V (VRB) DC : 1.0V AC : 0.286Vp-p (burst) DC : 0.5V (sync) AC : 1.0Vp-p (typ.) Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Impedance 400 VZ OUT27 Impedance 1k28 3.3V ± 5% Vdd (Output)29 Power source for D/A etc. G OUT30 R OUT28 B OUT32 Vss (Output)31 Power source for D/A etc. APC Filter34 5.0V ± 5% Vdd (VCXO)33 Power source for VCXO etc. Impedance=N.A. (Additional filter on PCB board) DC : 2.05V DC : 3V (blanking) DC 2.9V Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Impedance 1kX'tal35 Impedance>100k X-ray Protector36 ESD PROTECT AFC1 Filter37 Impedance 400 V RAMP OUT38 38 2.5Vp-p (typ.) Impedance 5k 40Neck Protector40

3939 HVCO F/B

Impedance=N.A. (Additional filter on PCB board) DC 3.0V Impedance=N.A. (Additional filter on PCB board) DC 2.5V 0.0-3.0 : Normal 3.2-3.3 : Hold down 3.7-5.0 : Shut down 0.0-1.0 : RGB off 1.6-3.0 : Normal 4.0-5.0 : Test mode Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Vss (DEF)41 Power source for Deflection block. Vdd (DEF)42 Power source for Deflection block. 5.0V ± 5% Y C A FBP IN43 Y C A H OUT44 CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) VOL : 0V VOH : 5V Y s C A CMOS IN/OUT 2 Impedance>100k (input) Impedance<100 (output) SDA45 VIL = 0V : RGB output VIH = 5V : Blanking VIL : 0V VIH : 5V Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Y C A Y s CMOS Schmitt IN Y C A CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) OSD(G) IN49 OSD(B) IN48 OSD(R) IN51 Half Tone IN47 SCL46 Y C A CMOS IN/OUT 1 Fast BLK IN50 Impedance>100k (input) Impedance<100 (output) RGB output Half tone on V IL : 0V V IH : 5V VIL = 0V : VIH = 5V : VIL : 0V VIH : 5V VIL = 0V : RGB output VIH = 5V : OSD output Impedance>100k Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins V sync OUT52 H sync OUT53 Y C A Y C A Y 54P51/VSYNC54 CMOS INPUT Impedance>100k Y C A CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output)P52/R55 P53/OUT156 P30/G57 P31/B58 P10/OUT259 VOL : 0V VOH : 5V CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) VOL : 0V VOH : 5V Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Y C AP11/SCL160 P12/SCL261 P13/SDA162 P14/SDA263 CMOS IN/OUT 1 Impedance>100k (input) Impedance 250 (output) Y P00/PWM064 P01/PWM165 P02/PWM266 P03/PWM367 CMOS IN/OUT Impedance>100k (input) Impedance 250 (output) P04/PWM468 Y P05/AD369 P06/INT2/AD470 CMOS IN/OUT Impedance>100k (input) Impedance 250 (output) Y P07/INT171 CMOS IN/OUT Impedance>100k (input) Impedance 250 (output) Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins Y C A CMOS IN/OUT 1 Impedance>100k (input) Impedance<100 (output) P23/TIM372 P24/TIM273 Y C A P25/AD574 CMOS IN/OUT 1 Impedance>100k (input) Impedance 250 (output) HLF75 76VHOLD76 CV IN77 77 Impedance=N.A. (Additional filter on PCB board) Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. Pin No. Peripheral circuit of pins CN VSS78 CMOS IN/OUT Impedance>100k (input) Impedance 250 (output) X IN79 X OUT80 Name Note

Mitsubishi Semiconductor <Digital IC> Digital Video/Chroma/Deflection +MCU Preliminary Note : This is not a final specification. Some of information in this document are subject to changes. MEMORY MAP 000016 00C0 16 00FF16 087F16 SFR1 area FFFF 16 080016 Interrupt vector area Special page OSD RAM (128 bytes) (note) Zero page 020016 020F16 SFR2 area Not used 030016 00BF 16 010016 01FF16 05BF 16 600016 ROM (40K bytes) 1000016 1FFFF 16 ROM correction function Vector 1: addresses 030016 Vector 2: addresses 032016 032016 FF0016 FFDE 16 1140016 13BFF 16 OSD ROM (10K bytes) Not used Mask ROM version RAM (1152 bytes) Not used Not used Not used Not used