M64898GP

M64898GP MITSUBISHI | Alldatasheet

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MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC

DESCRIPTION

The M64898GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR /PC. It contains the prescaler with operating up to1.3GHz,4 band drivers and DC-DC converter for Tuning voltage.

FEATURES

Built-in DC-DC converter for Tuning voltage 4 integrated PNP band drivers (Io=30mA, Vsat=0.2V typ@V CC1 to 10V ) Built-in prescaler with input amplifier (max=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X’tal 4MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64892/M64893 Automatick switching of tuning step according to the number of data bits (62.5kHz at 18bits , 32.25kHz at 19bits) Built-in Power on reset system Small Package(SSOP) APPLICATION PC, TV, VCR tuners PIN CONFIGURATION (TOP VIEW) RECOMMENDED OPERATING CONDITION CC1 =4.5 to 5.5V V CC2 CC1 to 10V CC1 =5V V CC2 CC1 Xin ENA DATA CLK LD/ftest CONT Vin Vtu CRYSTALPRESCALER GND SUPPLY SUPPLY BAND OUTPUTS BS4 BS3 BS2 BS1 INPUT fin GND VCC1 VOLTAGE 1 VOLTAGE 2 VCC2 Outline 20P2E-A SWITCHING ENABLE INPUT LD/ftest fREF FILTER INPUT TUNING OUTPUT 165 156 147 138 129 1110 M64898GP DC-DCSUPPLY VOLTAGE PEACK CURRENT DETECT VDC lpk OUTPUT +B SUPPLY SWE SWITCHING OUTPUT VOLTAGE SWITCHING OSCILLATOR DATA INPUT CLOCK INPUT BLOCK DIAGRAM GND CNT VCC2 BS4 BS3 BS2 BS1 Power On Reset AMP 1/32,1/33 OSC f REF DIVIDER SELECTER LATCH LATCH 15bit PROGRAMMABLE DIVIDER PHASE DETECTOR CHARGE PUMP BAIS / BAND SWITCH DRIVER LOCK DETECTOR LATCH 18/19-bit SHIFT REGISTER CONTROL CP TEST OS DIV. Vreg S R Q 7654 2 153 109 ENA CLK fin Xin DATA VCC1 VDC lpk SWE Vtu Vin LD/ftest

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION OF PIN ABSOLUTE MAXIMUM RATINGS (Ta=-20 C to +75 C, unless otherwise noted) Pin No. Symbol Pin name Function 1 f in Prescaler input Input for the VCO frequency. 2 GND GND Ground to 0V. CC1 Power supply voltage 1 Power supply voltage terminal. 5.0V 0.5V CC2 Power supply voltage 2 Power supply for band switching, Vcc to 10V

5 BS4

PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF .

6 BS3

7 BS2

8 BS1

9 VDC

DC-DC power supply voltage terminal. 5.0V 0.5V

10 Ipk

When potential difference with VDC terminal becomes more than 0.33V by current limiting detector of DC-DC converter, the listing rises with off. 11 SWE Switching output DC-DC converter oscillator output. 12 +B Power supply voltage Power supply voltage for turning voltage. 13 Vtu Tuning output This supplies the tuning voltage. Vin Filter input (Charge pump output) This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (f REF ), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active.

15 LD/ftest Lock detect /Test port

Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" level or unlock. In control byte data input, the programmabule freq. divider output and reference freq. output is selected by the test mode.

16 CONT f

Set up reference frequency divider ratio. In "L" level, set it up in 1/640(19Bit) in setting "opening" in 1/1024(19Bit) or 1/512 (18Bit). 17 CLOCK Clock input Data is read into the shift register when the clock signal falls. 18 DATA Data input Input for band SW and programmable freq. divider set up.

19 ENABLE Enable input

This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the enable signal after the 18th signal of the clock signal falls or when the 19th pulse of the clock signal falls.

20 X in This is connected to

the crystal oscillator.4.0MHz crystal oscillator is connected. Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 6.0 V V CC2 Supply voltage 2 Pin4 10.8 V V I Input voltage Not to exceed Vcc 6.0 V V O Output voltage f REF output 6.0 V V BSOFF Voltage applied when the band output is OFF 10.8 V I BSON Band output current per 1 band output circuit 40.0 mA t BSON ON the time when the band output is ON 40mA per 1 band output circuit 3circuits are pn at same time, 10 sec P d Power dissipation Ta=75 C 255 mW T opr Operating temperature -20 to +75 C T stg Storage temperature -40 to +125 C

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC RECOMMENDED OPERATING CONDITIONS (Ta=-20 C to +75 C, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

(Ta=-20 C to +75 C, unless otherwise noted, Vcc =5.0V, Vcc =9.0V) The typical values are at V CC1 =5.0V, V CC2 =9.0V, Ta=+25 Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 4.5 to 5.5 V V CC2 Supply voltage 2 Pin4 V CC1 to 10.0 V f opr1 Operating frequency (1) Crystal oscillation circuit 4.0 V f opr2 Operating frequency (2) 80 to 1300 MHz Band output current 5 to 8 Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. I BDL 0 to 30 mA Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. V IH Input terminals “H” input voltage 17 to 19 3.0 V CC1 +0.3 V V IL1 “L ” input voltage 15 0.4 V V IL2 “L ” input voltage 17 to 19 1.5 V I IH “H” input current 17 to 19 V CC1 =5.5V, Vi=4.0V m A I IL1 “L ” input current 15 V CC1 =5.5V, Vi=0V -50 -80 m A I IL2 “L ” input current 17, 19 V CC1 =5.5V, Vi=0.5V -6 -10 m A I IL3 “L ” input current 18 V CC1 =5.5V, Vi=0.5V -18 -30 m A V OH Lock output “H” output voltage 16 V CC1 =5.5V 5.0 V V OL “L ” output voltage 16 V CC1 =5.5V 0.3 0.5 V V BS Band SW Output voltage 5 to 8 V CC2 I olk1 Leak current 5 to 8 V CC2 =9V, Band SW is OFF Vo=0V -10 m A V toH Tuning output Output voltage “H” 13 +B=31V 30.5 V V toL Output voltage “L ” 13 +B=31V 0.2 0.4 V I cpo Charge pump “H” output current 14 V CC1 =5.0V, Vo=2.5V 270 370 m A I cpLK Leak current 14 V CC1 =5.0V, Vo=2.5V - - – 50 nA I CC1 Supply current 1 3 V CC1 =5.5V 20 30 mA I CC2A Supply current 2 4 circuits OFF 4 V CC2 =9V 0.3 mA I CC2B 1 circuits ON, Output open 4V CC2 =9V 4.0 6.0 mA I CC2C Output current 30mA 4 V CC2 =9V, Io=-30mA 34.0 36.0 mA DC-DC Converter I CCdc Supply current (action) 9 V CC1 =5.5V - 1.3 3.0 mA Vdo Output voltage 12 V CC1 =5.5V 28 31 35 V fOSC OSC frequency 11 V CC1 =5.5V - 571 - kHz Vipk Current limit detect voltage 10 V CC1 =5.5V - 330 - mV

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V) Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. fopr Prescaler operating frequency 1 VCC1 =4.5 to 5.5V Vin=Vinmin to Vinmax 80 - 1300 MHz Vin Operating input voltage 1 VCC1 =4.5 to 5.5V 80 to 100MHz -24 - 4 dBm100 to 950MHz -27 - 4 950 to 1300MHz -15 - 4 tPWC Clock pulse width 17 V CC1 =4.5 to 5.5V 1 -- m s tSU (D) Data setup time 18 V CC1 =4.5 to 5.5V 2 -- m s tH (D) Data hold time 18 V CC1 =4.5 to 5.5V 1 -- m s tSU (E) Enable setup time 18 V CC1 =4.5 to 5.5V 3 -- m s tH (E) Enable hold time 18 V CC1 =4.5 to 5.5V 3 -- m s tINT Enable data interval time 19, 18 V CC1 =4.5 to 5.5V 1 -- m s tr Rise time 17, 18, 19VCC1 =4.5 to 5.5V -- 1 ms tf Fall time 17, 18, 19VCC1 =4.5 to 5.5V -- 1 ms tBT Next enable prohibit time 19 V CC1 =4.5 to 5.5V 5 -- m s tBCL Next clock prohibit time 17, 19 V CC1 =4.5 to 5.5V 5 -- m s

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC METHOD OF SETTING DATA The programmable divider ratio uses 15bits. Setting up the band switching output uses 4bits. The test mode data uses 8bits. The total bits used is 27bits. Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal. The programmable counter data is read into the latch by the fall of the enable signal after the 18th pulse of the clock signal or the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 18th pulse of the enable signal, only the band SW data is updated and other data is ignored. Automatic judgment facility comes being it, and, as for Shift resister, CONT terminal rises by 18/19 bits at the time of "L". At the time of data of 18 bits, M9 bit of Programable divider is done reset of, and it is established in reference frequency divider ratio 1/512. At the time of 19 bits,reference frequency divider ratio is established in 1/1024. When reference frequency divider ratio was established in 1/640 by 19 bits at the time of "opening" CONT terminal, and it became "L" before 19 pulse enable signal, only band SW data are renewed, and other data are ignored. BS4 BS3 BS2 BS1 2 8 27 26 25 24 23 22 21 20 24 23 22 21 20 ENA DATA CLK BAND SW DATA READ INTO LATCH M COUNTER DIVIDER RATIO SETTING S COUNTER DIVIDER RATIO SETTING READ INTO LATCH M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 (1) Transfer of the 18th bit data (CONT terminal is "L" ) Data is latched by the fall of the enable signal after the 18th clock signal. At this time, the divider of the 1/512 of the reference frequency is used. (2) Transfer of the 19th bit data (CONT terminal is "L" or "open") The data is latched at the 19th pulse of the clock signal. Reference frequency divider ratio is established in 1/1024 in case of "L" CONT terminal at this time. Reference frequency divider ratio is established in 1/640 in case of "opening" CONT terminal. Invalid the clock signal after 19th pulse. Notice) When CONT terminal is "L", to change reference frequency, set up as ENA in "L" after 19th pulse of clock signal by all means. BS4 BS3 BS2 BS1 2 8 27 26 25 24 23 22 21 20 24 23 22 21 20 ENA DATA CLK BAND SW DATA READ INTO LATCH M COUNTER DIVIDER RATIO SETTING S COUNTER DIVIDER RATIO SETTING READ INTO LATCH M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0M9

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC HOW TO SET THE DIVIDING RATIO OF THE PROGRAMMABLE DIVIDER (1) Transfer of the 18th bit data (CONT terminal is "L" ) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 • (32M+S) M : 9 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32£M £511 0£S£31 Therefore, the range of divider N is 8,192 to 131,064. The tuning frequency f VCO is given in the following equations. fVCO =fREF ·N =7.8125·8·(32M+S) =62.5·(32M+S) [kHz] Therefore, the tuning frequency range is 64MHz to 1023.9375MHz. (2) Transfer of the 19th bit data (CONT terminal is "L" ) Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 • (32M+S) M : 10 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32£M £1023 0£S£31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency f VCO is given in the following equations. fVCO =fREF ·N =3.90625·8·(32M+S) =31.25·(32M+S) [kHz] Therefore, the tuning frequency range is 32MHz to 1023.96875 MHz. (3) Transfer of the 19th bit data (CONT terminal is "open") Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 • (32M+S) M : 10 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32£M £1023 0£S£31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency f VCO is given in the following equations. fVCO =fREF ·N =6.25·8·(32M+S) =50.0·(32M+S) [kHz] But, the tuning frequency range is 51.2MHz to 1300MHz from the maxmum prescaler operating frequency. (2) Test Mode Bit Set Up X :Random, 0 or 1.normal "0" T0, T1,&T2 :Set up test modes RSa, Rsa :Set the frequency divider of the reference frequency OS :Set up the tuning amplifier TEST MODE DATA SET UP METHOD The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls. (1) When transferring 3-wire 27 bit data ENA T2 T1 T0 RSa RSb 0S TEST DATA SETTING CLK XXBAND SW DATA M COUNTER DIVIDER RATIO SETTING S COUNTER DIVIDER RATIO SETTING 1 19 20 27 READ INTO LATCH

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC Setting up for the test mode Set up for the reference Frequency divider ratio Set up the tuning amplifier Power on reset operation (Initial state the power is turned ON) BS4 to BS1 : OFF Charge pump : High impedance Tuning amplifier : OFF Charge pump current : 270mA * Frequency divider ratio : 1/1024 Lock detect : H * Charge pump current is replaced by 70mA when locks it by automatic change facility. T2 T1 T0 Charge pump 12 pin output Mode 0 0 X Normal operation LD Normal operation 0 1 X High impedance LD Test mode 1 1 0 Sink LD Test mode 1 1 1 Source LD Test mode 1 0 0 High impedance f REF Test mode 1 0 1 High impedance f1/N Test mode RSa RSb Divider ratio 1 1 1/512 0 1 1/1024 X 0 1/640 OS Tuning voltage output Mode

0 ON Normal

1 OFF Test

CRYSTAL OSCILLATOR CONNECTION DIAGRAM ENABLE VIH VIL VIH VIH VIL VIL DATA CLOCK tr tf 90% 1.5V 10% tINT 1.5V 10% 90% tr tf 90% 10% tINT 90% 10% tH(E) tftr 10% 90% 10% 90% tH(D) tSU(E) tSU(D) tPWC 1.5V tBT tBCL 18pF 4MHz Crystal oscillator characteristics Actual resistance : less then 300 W Load capacitance : 20pF

MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC APPLICATION EXAMPLE POWER ON 1000pF 4-BAND TUNER UHF VHF V CC1 to 9V +5V 1000pF 1387654 4MHz IF AGC 18pF 100pF 680pF 0.1 m F 56k 56k OSC DIVIDER LOCK DETECTORSWALLOW COUNTER MAIN COUNTER BAND DRIVER 1/8 1/33 PHASE DETECTOR CHARGE PUMP 11 4 BIAS CIRCUITRESET 22k AMP SELEC- S R Q + - Vreg 10 119 1.5 m F MCU CLKDATA ENA LD/ftest 17 18 18/19 bit 0.01 m F 0.1 m F m H m H +B BS4 BS3 BS2 BS1 LO VT AFT AGCIF M64898GP SHIFT RESISTER DATA LATCH TER Units Resistance : W Capacitance : F BUILT-IN PLL TUNER Note) Filter constant is Add a capacitor to stabilize for reference. the filter circuit. V CC1 =5V