M64897GP

M64897GP MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC

DESCRIPTION

The M64897GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR/PC using I C BUS control. It contains the prescaler with operating up to1.3GHz, 4 band drivers and DC-DC converter for Tuning voltage.

FEATURES

Built-in DC-DC converter for Tuning voltage 4 integrated PNP band drivers (Io=30mA, Vsat=0.2V typ@Vcc1 to 10V) Built-in prescaler with input amplifier (f max=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X’tal 4MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64894 Built-in Power on reset system Small Package (SSOP) APPLICATION PC, TV, VCR tuners PIN CONFIGURATION (TOP VIEW) RECOMMENDED OPERATING CONDITION CC1 =4.5 to 5.5V V CC2 CC1 to 10V CC1 =5V V CC2 CC1 Xin ADS SDA SCL LD/ftest ADC Vin Vtu CRYSTAL PRESCALER GND SUPPLY SUPPLY BAND OUTPUTS BS4 BS3 BS2 BS1 INPUT fin GND VCC1 VOLTAGE 1 VOLTAGE 2 VCC2 Outline 20P2E-A SWITCHING CHIP ADDRESS INPUT OSCILLATOR DATA INPUT CLOCK INPUT LD/ftest A/D INPUT FILTER INPUT TUNING OUTPUT 165 156 147 138 129 1110 M64897GP DC-DCSUPPLY VOLTAGE PEACK CURRENT DETECT VDC Ipk OUTPUT +B SUPPLY SWE SWITCHING OUTPUT VOLTAGE BLOCK DIAGRAM GND ADCVCC2 BS4 BS3 BS2 BS1 Power On Reset AMP 1/32,1/33 OSC f REF DIVIDER SELECTER LATCH LATCH 15bit PROGRAMMABLE DIVIDER PHASE DETECTOR CHARGE PUMP BAIS / BAND SWITCH DRIVER LOCK DETECTOR LATCH 5-LEVEL A/D BUS CONTROLLER ADDRESS SELECT CP TEST OS DIV. Vreg S R Q 7654 2 15 109 ADS SCL fin Xin SDA VCC1 VDC Ipk SWE Vtu Vin LD/ftest

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION OF PIN ABSOLUTE MAXIMUM RATINGS (Ta=-20 C to +75 C, unless otherwise noted) Pin No. Symbol Pin name Function 1 f in Prescaler input Input for the VCO frequency. 2 GND GND Ground to 0V. CC1 Power supply voltage 1 Power supply voltage terminal. 5.0V 0.5V CC2 Power supply voltage 2 Power supply for band switching, Vcc to 10V

5 BS4

PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF .

6 BS3

7 BS2

8 BS1

9 VDC

DC-DC power supply voltage terminal. 5.0V 0.5V

10 Ipk

When potential difference with VDC terminal becomes more than 0.33V by current limiting detector of DC-DC converter, the listing rises with off. 11 SWE Switching output DC-DC converter oscillator output. 12 +B Power supply voltage Power supply voltage for turning voltage. 13 Vtu Tuning output This supplies the tuning voltage. Vin Filter input (Charge pump output) This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (f REF ), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active.

15 LD/ftest Lock detect /Test port

Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" level or unlock. In control byte data input, the programmabule freq. divider output and reference freq. output is selected by the test mode. 16 ADC AD converter input A/D conversion of the input voltage. 17 SCL Clock input Data is read into the shift register when the clock signal falls. SDA Data input Input for band SW and programmable freq. divider set up. In lead mode, itoutputs lock detector output and power down flag and a state of 5 level A/D converter.

19 ADS

Chip address sets it up with the input condition of terminal.

20 X in This is connected to

the crystal oscillator4.0MHz crystal oscillator is connected. Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 6.0 V V CC2 Supply voltage 2 Pin4 10.8 V V I Input voltage Not to exceed Vcc 6.0 V V O Output voltage f REF output 6.0 V V BSOFF Voltage applied when the band output is OFF 10.8 V I BSON Band output current per 1 band output circuit 40.0 mA t BSON ON the time when the band output is ON 40mA per 1 band output circuit 3circuits are pn at same time, 10 sec P d Power dissipation Ta=75 C 255 mW T opr Operating temperature -20 to +75 C T stg Storage temperature -40 to +125 C

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC RECOMMENDED OPERATING CONDITIONS (Ta=-20 C to +75 C, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

(Ta=-20 C to +75 C, unless otherwise noted, Vcc =5.0V, Vcc =9.0V) The typical values are at V CC1 =5.0V, V CC2 =9.0V, Ta=+25 Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 4.5 to 5.5 V V CC2 Supply voltage 2 Pin4 V CC1 to 10.0 V f opr1 Operating frequency (1) Crystal oscillation circuit 4.0 V f opr2 Operating frequency (2) 80 to 1300 MHz Band output current 5 to 8 Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. I BDL 0 to 30 mA Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. V IH Input terminals “H” input voltage 17 to 18 3.0 V CC1 +0.3 V V IL “L ” input voltage 17 to 18 1.5 V I IH “H” input current 17 to 18 V CC1 =5.5V, Vi=4.0V m A I IL “L ” input current 17/18 V CC1 =5.5V, Vi=0.4V -4/-14 -10/-30 m A V OL SDA output “L ” output voltage 18 V CC1 =5.5V, Ic=3mA 0.4 m A I LO Leak current 18 V CC1 =5.5V, Vo=5.5V m A V OH Lock output “H” output voltage 16 V CC1 =5.5V 5.0 V V OL “L ” output voltage 16 V CC1 =5.5V - 0.3 0.5 V V BS Band SW output voltage 5 to 8 V CC2 V I olk1 Leak current 5 to 8 V CC2 =9V, Band SW is OFF Vo=0V -10 m A V toH Tuning output output voltage “H” 13 +B=31V 30.5 V V toL output voltage “L ” 13 +B=31V 0.2 0.4 V I cpo Charge pump “H” output current 14 V CC1 =5.0V, Vo=2.5V 270 370 m A I cpLK Leak current 14 V CC1 =5.0V, Vo=2.5V - - – 50 nA I CC1 Supply current 1 3 V CC1 =5.5V 20 30 mA I CC2A Supply current 2 4 circuits OFF 4 V CC2 =9V 0.3 mA I CC2B 1 circuits ON, Output open 4V CC2 =9V 4.0 6.0 mA I CC2C Output current 30mA 4 V CC2 =9V, Io=-30mA 34.0 36.0 mA DC-DC Converter I CCdc Supply current (action) 9 V CC1 =5.5V 1.3 3.0 mA V do Output voltage 12 V CC1 =5.5V 28 31 35 V f OSC OSC frequency 11 V CC1 =5.5V - 571 - kHz Vipk Current limit detect voltage 10 V CC1 =5.5V - 330 - mV

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V) Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. fopr Prescaler operating frequency 1 VCC1 =4.5 to 5.5V Vin=Vinmin to Vinmax 80 - 1300 MHz Vin Operation input voltage 1 VCC1 =4.5 to 5.5V 850 to 100MHz -24 - 4 dBm100 to 950MHz -27 - 4 950 to 1300MHz -15 - 4 fSCL Clock pulse frequency 17 V CC1 =4.5 to 5.5V 0 - 100 kHz tBUF Bus free time 18 V CC1 =4.5 to 5.5V 4.7 -- m s tHD STA Data hold time 17 V CC1 =4.5 to 5.5V 4 -- m s tLOW SCL low hold time 17 V CC1 =4.5 to 5.5V 4.7 -- m s tHIGH SCL high hold time 17 V CC1 =4.5 to 5.5V 4 -- m s tSU STA Set up time 17, 18 V CC1 =4.5 to 5.5V 4.7 -- m s tHD DAT Data hold time 17, 18 V CC1 =4.5 to 5.5V 0 -- s tSU DAT Data set up time 17, 18 V CC1 =4.5 to 5.5V 250 -- ns tR Rise time 17, 18 V CC1 =4.5 to 5.5V -- 1000 ns tF Fall time 17, 18 V CC1 =4.5 to 5.5V -- 300 ns tSU STO Set up time 17, 18 V CC1 =4.5 to 5.5V 4 -- m s

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC METHOD OF SETTING DATA The input information to consit of 2 or data of 4bytes to lead to Chip Address is received in I2C bus receiver. It shows a definition of bus protocol admitted in the following. 1_STA CA CB BB STO 2_STA CA D1 D2 STO 3_STA CA CB BB D1 D2 STO 4_STA CA D1 D2 CB BB STO STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : BandS.W. data byte D1 : Divider data byte D2 : Divider data byte The information of 5 bytes necessary for circuit operation is chip address and control data, bandS.W. data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data, and "0" goes ahead of divider data, and "1" goes ahead of control data, bandS.W. data. Write mode format Read mode format Byte MSB LSB Address Byte 11000 M A 1 M A 0 0A Devider Byte1 0 N14 N13 N12 N11 N10 N9 N8 A Devider Byte2 N7 N6 N5 N4 N3 N2 N1 N0 A Control Byte1 1 X T2 T1 T0 Rsa Rsb OS A Band SW Byte XXXX B S 4 B S 3 B S 2 B S 1 A Byte MSB LSB Address Byte 11000 M A 1 M A 0 1A Status Byte1 POR FL X X X A2 A1 A0 A ADDRESS CA R/W ACK DATA ACK DATA ACK 1-7 8 9 1-7 8 9 1-7 8 9 SDA SCL S STA P STO

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DATA CORDING EXAMPLE Write mode format example fVCO =N ·8·fREF Read mode format example (Loop locked) Byte MSB LSB Condition in data setting Address Byte 110001101 ADS input VCC1 Devider Byte1 010000001 Divider ratio N=16544Devider Byte2 101000001 Control Byte1 110000101 f REF divider ratio 1/1024 Band SW Byte 000010001 BS4 output ON Byte MSB LSB Condition in device Address Byte 110001111 ADS Applied voltage 0.9*VCC1 to VCC1 Status Byte 011110111 ADS Applied voltage 0.45*VCC1 to 0.6*VCC1 Use data input for "1" so that the data of Read mode and Write mode return ACK signal "0" to micro computer in 9bits of each byte. TEST MODE DATA SET UP METHOD Test Mode Bit Set Up X : Random, 0 or 1. normal "0" MA1 ,MA0 : Programmabule Address Bit N14 to N0 : How to set dividing ratio of the programable the divider Divider ratio=N14(214=16384)+ × × × +N0(20=1) Therefore, the range of divider N is 1,024 to 32,768 Example) fvco=fREF ·8·N =3.90625·8·N =31.25·N (kHz) T2, T1, T0 : Setting up for the test mode RSa, RSb : Set up for the reference Frequency divider ratio OS : Set up the tuning amplifier POR : Power on reset flag. "1" output at reset FL : Lock detector flag. "1" output at locked, "0" output at unlocked Address input voltage MA1 MA0 0 to 0.1*VCC1 00 Always valid 0 1 0.4*V CC1 to 0.6*VCC1 10 0.9*VCC1 to VCC1 11 T2 T1 T0 Charge pump 12 pin condition Mode 0 0 XNormal operation ADC input Normal operation 0 1 X High impedance ADC input Test mode 1 1 0 Sink ADC input Test mode 1 1 1 Source ADC input Test mode 1 0 0 High impedance f REF output Test mode 1 0 1 High impedance f1/N output Test mode RSa RSb Divider ratio 1 1 1/512 0 1 1/1024 X 0 1/640 OS Tuning voltage output Mode

0 ON Normal

1 OFF Test

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC A2, A1, A0 : 5level A/D converter output data The voltage accuracy allowance range : –0.03*VCC1 [V] Power on reset operation (Initial state the power is turned ON) BS4 to BS1 : OFF Charge pump : High impedance Tuning amplifier : OFF Charge pump current : 270mA * Frequency divider ratio : 1/1024 Lock detect : H * Charge pump current is replaced by 70mA when locks it by automatic change facility. ADC input voltage A2 A1 A0 0.6*V CC1 to VCC1 100 0.45*VCC1 to 0.6*VCC1 011 0.3*VCC1 to 0.45*VCC1 010 0.15*VCC1 to 0.3*VCC1 001 0 to 0.15*VCC1 000 TIMING DIAGRAM CRYSTAL OSCILLATOR CONNECTION DIAGRAM SDA SCL tBUF tHD STA tHD DAT tHIGH tSU DAT tSU STA tSU STO tHD STAtFtRtLOW STOP condition START condition STOP condition START condition 18pF 4MHz Crystal oscillator characteristics Actual resistance : less then 300 W Load capacitance : 20pF

MITSUBISHI ICs (TV) M64897GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC APPLICATION EXAMPLE POWER ON Note) Filter constant is 1000pF 4-BAND TUNER UHF VHF V CC1 to 9V +5V 1000pF 1387654 4MHz IF AGC 18pF 100pF 1500pF 0.1 m F 56k 56k OSC DIVIDER LOCK DETECTORSWALLOW COUNTER MAIN COUNTER BAND DRIVER 1/8 1/33 PHASE DETECTOR CHARGE PUMP 11 4 BIAS CIRCUITRESET 22k AMP CHIP SELECT 5LEVEL A/DC Vcc1 S R Q + - Vreg 10 119 1.5 m F Add a capacitor to stabilize MCU SCLADS SDA LD/ftest 17 18 I C RECIEVER 51k V CC1 0.01 m F 0.1 m F m H m H +B BS4 BS3 BS2 BS1 LO VT AFT AGCIF M64897GP BUILT-IN PLL TUNER Units Resistance : W Capacitance : F for reference. the filter circuit.