M64894GP

M64894FP MITSUBISHI | Alldatasheet

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Technical content

S (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

DESCRIPTION

The M64894 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using I C BUS control. It contains the prescaler with operating up to 1.3GHz, 4 band drivers and tuning Amplifier for direct tuning. Built-in 4 band drivers.

FEATURES

4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc to 13.2V) Built-in high-withstanding voltage tuning Amplifier Low power dissipation (Icc=20mA, Vcc=5V) Built-in prescaler with input amplifier (Fmax=1.3GHz) I C bus control (Read and write mode) X’tal 4MHz is used to realize 3 type of tuning steps (Division ratio 1/512, 1/640, 1/1024) Built-in 5-level A/D converter Programmable chip address 16-pin small SOP/SSOP package APPLICATION TV, VCR tuners RECOMMENDED OPERATING CONDITION CC1 =4.5 to 5.5V V CC2 CC1 to 13.2V V CC3 =28 to 35V CC1 =5V V CC2 =12V V CC3 =33V PIN CONFIGURATION (TOP VIEW) FUNCTION 2-modulus prescaler (1/32 and 1/33) Built-in 4MHz crystal oscillator and reference divider Programmable divider (10-bit M counter, 5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op. Amp for direct tuning I C bus receiver 5-level A/D converter Xin ADS SDA SCL ADC V CC3 Vtu Vin CRYSTAL PRESCALER GND SUPPLY SUPPLY BAND OUTPUTS BS4 BS3 BS2 BS1 INPUT fin GND VCC1 VOLTAGE 1 VOLTAGE 2 VCC2 Outline 16P2S-A (FP) 125 116 107 SWITCHING CHIP ADDRESS INPUT OSCILLATOR DATA INPUT CLOCK INPUT A/D INPUT SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT M64894FP/GP 16P2Z-A (GP)

S (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR BLOCK DIAGRAM fin GND V CC1 VCC2 BS4 BS3 BS2 BS1 Xin ADS SDA SCL ADC VCC3 Vtu Vin 1/32,1/33 1/8 BAND DRIVER LOCK CHARGE AMP BIASP.O RESET 10-BIT M COUNTER 5-BIT S COUNTER 16 15 14 13 12 11 10 9 I2C RECEIVER AMP 87654321 DIVIDER PHASE PRESCALER INPUT SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 BAND SWITCHING OUTPUTS CRYSTAL OSCILLATOR CHIP ADDRESS DATA INPUT CLOCK SUPPLY TUNING FILTER INPUTOUTPUTVOLTAGE 3A/D INPUTINPUTINPUT OSC 5-LEVEL A/D C COMPARATOR PUMP DETECTOR

S (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION OF PIN ABSOLUTE MAXIMUM RATINGS (Ta=-20 C to +75 C, unless otherwise noted) RECOMMENDED OPERATING CONDITIONS (Ta=-20 C to +75 C, unless otherwise noted) Pin No. Symbol Pin name Function 1 fin Prescaler input Input for the VCO frequency. 2 GND GND Ground to 0V. CC1 Power supply voltage 1 Power supply voltage terminal. 5.0V 0.5V CC2 Power supply voltage 2 Power supply for band switching, Vcc to 13.2V BS4 BS3 BS2 BS1 Band switching outputs PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF .

9 Vin Filter input

(Charge pump output) This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fref), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. 10 Vtu Tuning output This supplies the tuning voltage. 11 V CC3 Power supply voltage 3 Power supply voltage for tuning voltage 28 to 35V

12 ADC/ftest AD converter input/

A/D conversion of the input voltage. In control byte data input, the programmabule freq. Divider output and reference freq. output is selected by the test mode. 13 SCL Clock input Data is read into the shift register when the clock signal falls.

14 SDA Data input

Input for band SW and programmable freq. divider set up. In lead mode, itoutputs lock detector output and power down flagand a state of 5 level A/D converter. 15 ADS Address switching input Chip address sets it up with the input condition of terminal.

16 Xin This is connected to the

crystal oscillator 4.0MHz crystal oscillator is connected. Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 6.0 V V CC2 Supply voltage 2 Pin4 14.4 V V CC3 Supply voltage 3 Pin11 36.0 V V I Input voltage Not to exceed V CC1 6.0 V V O Output voltage f REF output 6.0 V V BSOFF Voltage applied when the band output is OFF 14.4 V I BSON Band output current Per 1 band output circuit 50.0 mA t BSON ON the time when the band output is ON50mA per 1 band output circuit 3circuit are pn at same time 10 sec P d Power dissipation Ta=+75 C 450 (470) mW T opr Operating temperature -20 to +75 C T stg Storage temperature -40 to +125 C Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 4.5 to 5.5 V V CC2 Supply voltage 2 Pin4 V CC1 to 13.2 V V CC3 Supply voltage 3 Pin11 28 to 35 V f opr1 Operating frequency (1) Crystal oscillation circuit 4.0 MHz f opr2 Operating frequency (2) 80 to 1,300 MHz I BDL Band output current 5 to 8 Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. 0 to 40 mA

S (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

ELECTRICAL CHARACTERISTICS

(Ta=-20 C to +75 C, Vcc =5.0V, Vcc =12V, Vcc =33V, unless otherwise noted) Note. Typical values are measured at V CC1 =5.0V, V CC 2=12V, V CC 3=33V, Ta=+25 SWITCHING CHARACTERISTICS (Ta=-20 C to +75 C, V CC1 =5.0V, V CC2 =12V, V CC3 =33V, unless otherwise noted) Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. V IH Input pin “H” input voltage 13 to 14 3.0 V CC1 +0.3 V V IL “L ” input voltage 13 to 14 1.5 V I IH “H” input current 13 to 14 V CC1 =5.5V, Vi=4.0V m A I IL “L ” input current 13, 14 V CC1 =5.5V, Vi=0.4V -4/-14 -10/30 m A V OL SDA output “H” output voltage 14 V CC1 =5.5V, Io=3mA 0.4 m A V LO “L ” output voltage 14 V CC1 =5.5V, Vo=5.5V m A V BS Band SW Output voltage 5 to 8 V CC2 =12V, Io=-40mA 11.6 11.8 V I OLK1 Leak current 5 to 8 V CC2 =12V band SW is OFF -10 m A V TOH Tuning output Output voltage “H” 10 V CC3 =33V 32.5 -- V VTOL Output voltage “L ” 10 V CC3 =33V - 0.2 0.4 V IOH Charge pump “H” output current 9 V CC1 =5.0V, Vo=2.5V -– 270 –370 mA IOL “L ” output current 9 V CC1 =5.0V, Vo=2.5V - –70 –110 mA ICPLK Leak current 9 V CC1 =5.5V, Vo=2.5V -- –50 nA ICC1 Supply current 1 3 V CC1 =5.5V - 20 30 mA ICC2A Supply current 2 4 circuits: OFF 4 V CC2 =12V -- 0.3 mA ICC2B 1 circuits: ON, Output: OPEN 4V CC2 =12V - 6.0 8.0 mA ICC2C Output current 40mA 4 V CC2 =12V Io=-40mA - 46.0 48.0 mA ICC3 Supply current 3 11 V CC3 =33V Output ON - 3.0 4.0 mA Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. fopr Prescaler operating frequency 1 VCC1 =4.5 to 5.5V Vin=Vinmin to Vinmax 80 - 1300 MHz Vin Operating input voltage 1 VCC1 =4.5 to 5.5V 80 to 100MHz -24 - 4 dBm 100 to 200MHz -27 - 4 200 to 800MHz -30 - 4 800 to 1000MHz -27 - 4 1000 to 1300MHz -18 - 4 tSCL Clock pulse frequency 13 V CC1 =4.5 to 5.5V 0 - 100 kHz tBUF Bus free time 14 V CC1 =4.5 to 5.5V 4.7 -- m s tHDSTA Data hold time 13 V CC1 =4.5 to 5.5V 4 -- m s tLOW SCL low hold time 13 V CC1 =4.5 to 5.5V 4.7 -- m s tHIGH SCL high hold time 13 V CC1 =4.5 to 5.5V 4 -- m s tSUSTA Set up time 13, 14 V CC1 =4.5 to 5.5V 4.7 -- m s tHDDAT Data hold time 13, 14 V CC1 =4.5 to 5.5V 0 -- s tSUDAT Data set up time 13, 14 V CC1 =4.5 to 5.5V 250 -- ns tr Rise time 13, 14 V CC1 =4.5 to 5.5V -- 1000 ns tf Fall time 13, 14 V CC1 =4.5 to 5.5V -- 300 ns tSUSTO Set up time 13, 14 V CC1 =4.5 to 5.5V 4 -- m s

MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR METHOD OF SETTING DATA The input information to consit of 2 or data of 4bytes to lead to Chip Address is received in I2Cbus receiver. It shows a definition of bus protocol admitted in the following. 1_STA CA CB BB STO 2_STA CA D1 D2 STO 3_STA CA CB BB D1 D2 STO 4_STA CA D1 D2 CB BB STO STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : BandS.W. data byte D1 : Divider data byte D2 : Divider data byte The information of 5 bytes necessary for circuit operation is chip address and control data, bandS.W. data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data, and "0" goes ahead of divider data, and "1" goes ahead of control data, bandS.W. data. Write mode format Read mode format Byte MSB LSB Address Byte 11000 M A 1 M A 0 0A Devider Byte1 0 N14 N13 N12 N11 N10 N9 N8 A Devider Byte2 N7 N6 N5 N4 N3 N2 N1 N0 A Control Byte1 1 CP T2 T1 T0 RSa RSb OS A Band SW Byte XXXX B S 4 B S 3 B S 2 B S 1 A Byte MSB LSB Address Byte 11000 M A 1 M A 0 1A Status Byte1 POR FL X X X A2 A1 A0 A ADDRESS CA

0 ACK DATA ACK DATA ACK

S STA P STO

MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DATA CORDING EXAMPLE Write mode format example fVCO =N ·8·fREF =16544·8·(4MHz/1024)=517MHz Read mode format example Byte MSB LSB Condotion in data setting Address Byte 110001101 ADS input VCC1 Devider Byte1 010000001 Dividing ratio N=16544Devider Byte2 101000001 Control Byte1 110000101 C.P . current 270mA fREF division ratio 1/1024 Band SW Byte 000010001 BS4 output ON Byte MSB LSB Condotion in divise Address Byte 110001111 Status Byte1 input 111111111 Status Byte1 output 011110111 F L “1”output at locked ADC input at open TEST MODE DATA SET UP METHOD Test Mode Bit Set Up X : Random, 0 or 1. normal "0" MA1 ,MA0 : Programmabule Address Bit N14 to N0 : How to set dividing ratio of the programable the divider Dividing ratio N=N14(214=16384)+ ××× +N0(20=1) Therefore, the range of division N is 1,024 to 32,768 Example) fvco=fREF ·8·N =3.90625·8·N =31.25·N (kHz) CP: Setting up the charge pump current of the phase comparator T2, T1, T0 : Setting up for the test mode RSa, RSb : Set up for the reference frequency division ratio OS : Set up the tuning amplifier POR : Power on reset flag. “1” output at reset FL : Lock detecter flag. “1” output at locked, “0” output at unlocked A2, A1, A0: 5level A/D converter output data The voltage accuracy allowance range: –0.03*VCC1 (V) POWER ON RESET OPERATION (Initial state the power is turned ON) BS4 to BS1 : OFF Charge pump : High impedance Tuning amplifier : OFF Charge pump current : 270mA Frequency division ratio : 1/1024 Address input voltage MA1 MA0 0 to 0.1*V CC1 00 Always valid 0 1 0.4*V CC1 to 0.6*VCC1 10 0.9*VCC1 to VCC1 11 CP Charge pump current Mode 07 0 mA Test 1 270 mA Normal T2 T1 T0 Charge pump Pin 12 condition Mode 0 0 XNormal operation ADC input Normal operation 0 1 X High impedance ADC input Test mode 1 1 0 Sink ADC input Test mode 1 1 1 Source ADC input Test mode 1 0 0 High impedance f REF output Test mode 1 0 1 High impedance f1/N output Test mode RSa RSb Division ratio 1 1 1/512 0 1 1/1024 X 0 1/640 OS Tuning voltage output Mode

0 ON Normal

1 OFF Test

ADC input voltage A2 A1 A0 0.6*V CC1 to VCC1 100 0.45*VCC1 to 0.6*VCC1 011 0.3*VCC1 to 0.45*VCC1 010 0.15*VCC1 to 0.3*VCC1 001 0 to 0.15*VCC1 000

MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR TIMING DIAGRAM CRYSTAL OSCILLATOR CONNECTION DIAGRAM SDA SCL tBUF tHD STA tHD DAT tHIGH tSU DAT tSU STA tSU STO tHD STAtftrtLOW STOP condition START condition STOP condition START condition 18pF 4MHz Crystal oscillator characteristics Actual resistance: less than 300W Load capacitance : 20pF

MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR APPLICATION EXAMPLE BT BUILT-IN PLL TUNER 1000p 4-BAND TUNER UHF VHFVcc1 to 12V+5V MCU 16 11 4MHz M64894FP/GP IF AGC 18p 1.5n 56k 100p 56k +33V BS4 BS3 BS2 BS1 Vcc2 fIN PD GNDXIN DATA CLK LD/f1/N SW +B Lo BS1 BS2 BS3 BS4 VT IF AGC AFT Units Resistance : W Capacitance : F EN 2.2n 6 87 XOUT TEST1 5 18 47k 47k 47k 47k GND 16 1000pF M5493X series ADC 1000p 10m ADS 0.1m Note) Filter constant is * Add a capacitor to stabilize for reference. the circuit.