M64892AFP

M64892AFP MITSUBISHI | Alldatasheet

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Technical content

S (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

DESCRIPTION

The M64892 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using Bip process. It contains the prescaler with operating up to 1.0GHz, 4 band drivers and Op. Amp for direct tuning.

FEATURES

4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc to 13.2V) Built-in Op. Amp for direct tuning voltage output (33V) Low power dissipation (Icc=20mA, Vcc =5V) Built-in prescaler with input amplifier (Fmax=1.0GHz) PLL lock/unlock status display out put (Built-in pull up resistor ) X’tal 4MHz is used to realize 3 type of tuning steps (Division ratio 1/512, 1/640, 1/1024) Serial data input. (3 wire bus) Software and pin compatible with M64092/M64892 Automatic switching of tuning step according to the number of data bits (62.5kHz at 18bits, 31.25kHz at 19bits) Built-in Power on reset system 16-pin small SOP/SSOP package APPLICATION TV, VCR tuners RECOMMENDED OPERATING CONDITION CC1 =4.5 to 5.5V V CC2 CC1 to 13.2V V CC3 =28 to 35V CC1 =5V V CC2 =12V V CC3 =33V PIN CONFIGURATION (TOP VIEW) FUNCTION 2-modulus prescaler (1/32 and 1/33) Built-in 4MHz crystal oscillator and reference divider Programmable divider (10-bit M counter, 5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op. Amp for direct tuning Xin ENA DATA CLK LD/ftest V CC3 Vtu Vin CRYSTAL PRESCALER GND SUPPLY SUPPLY BAND OUTPUTS BS4 BS3 BS2 BS1 INPUT fin GND VCC1 VOLTAGE 1 VOLTAGE 2 VCC2 Outline 16P2S-A (AFP) 125 116 107 SWITCHING ENABLE INPUT OSCILLATOR DATA INPUT CLOCK INPUT LD/ftest SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT OUTPUT M64892AFP/GP 16P2Z-A (AGP)

S (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR BLOCK DIAGRAM fin GND V CC1 VCC2 BS4 BS3 BS2 BS1 Xin ENA DATA CLK LD/ftest VCC3 Vtu Vin 1/32,1/33 1/8 BAND DRIVER LOCK DETECTOR CHARGE PUMP AMP BIASP.O RESET 10-BIT M COUNTER 5-BIT S COUNTER 16 15 14 13 12 11 10 9 18/19-BIT SHIFT AMP 87654321 DIVIDER REGISTER VCC1 PHASE DETECTOR PRESCALER INPUT SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 BAND SWITCHING OUTPUTS CRYSTAL OSCILLATOR ENABLE DATA INPUT CLOCK LD/ftest SUPPLY TUNING FILTER INPUTOUTPUTVOLTAGE 3INPUTINPUT OUTPUT OSC

S (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION OF PIN ABSOLUTE MAXIMUM RATINGS (Ta=-20 C to +75 C, unless otherwise noted) RECOMMENDED OPERATING CONDITIONS (Ta=-20 C to +75 C, unless otherwise noted) Pin No. Symbol Pin name Function 1 fin Prescaler input Input for the VCO frequency. 2 GND GND Ground to 0V. CC1 Power supply voltage 1 Power supply voltage terminal. 5.0V 0.5V CC2 Power supply voltage 2 Power supply for band switching, Vcc to 13.2V BS4 BS3 BS2 BS1 Band switching outputs PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF .

9 Vin Filter input

(Charge pump output) This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f1/N) is ahead compared to the refer- ence frequency (fref), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. 10 Vtu Tuning output This supplies the tuning voltage. 11 V CC3 Power supply voltage 3 Power supply voltage for tuning voltage 28 to 35V

12 LD/ftest Lock detect/Test port

When 18/19 bit data is input, lock detector is output. When 27 bit data is input, lock detector is output, the programmable freq. Divider output and reference freq. Output is selected by the test mode. 13 CLK Clock input Data is read into the shift register when the clock signal falls. 14 DATA Data input Input for band SW and programmable freq. divider set up.

15 ENA Enable input

This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the enable signal after the 18th signal of the clock signal falls or when the 19th pulse of the clock signal falls.

16 Xin This is connected to the

crystal oscillator 4.0MHz crystal oscillator is connected. Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 Pin3 6.0 V V CC2 Supply voltage 2 Pin4 14.4 V V CC3 Supply voltage 3 Pin11 36.0 V V I Input voltage Not to exceed V CC1 6.0 V V O Output voltage LD output 6.0 V V BSOFF Voltage applied when the band output is OFF 14.4 V I BSON Band output current Per 1 band output circuit 50.0 mA t BSON ON the time when the band output is ON50mA per 1 band output circuit 3circuits are pn at same time 10 sec P d Power dissipation Ta=+75 C (SOP/SSOP) FP: 450 (GP: 470) mW T opr Operating temperature -20 to +75 C T stg Storage temperature -40 to +125 C Symbol Parameter Conditions Ratings Unit V CC1 Supply voltage 1 4.5 to 5.5 V V CC2 Supply voltage 2 V CC1 to 13.2 V V CC3 Supply voltage 3 28 to 35 V f opr1 Operating frequency (1) Crystal oscillation circuit 4.0 MHz f opr2 Operating frequency (2) 80 to 1,000 MHz I BDL Band output current 5 to 8 Normally 1 circuit is ON. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. 0 to 40 mA

S (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

ELECTRICAL CHARACTERISTICS

(Ta=-20 C to +75 C, Vcc =5.0V, Vcc =12V, Vcc =33V, unless otherwise noted) Note. Typical values are measured at V CC1 =5.0V, V CC2 =12V, V CC3 =33V and Ta=+25 SWITCHING CHARACTERISTICS (Ta=-20 C to +75 C, V CC1 =5.0V, V CC2 =12V, V CC3 =33V, unless otherwise noted) Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. V IH Input pin “H” input voltage 13 to 15 3.0 V CC1 +0.3 V V IL “L ” input voltage 13 to 15 1.5 V I IH “H” input current 13 to 15 V CC1 =5.5V, Vi=4.0V m A I IL “L ” input current 13, 15 V CC1 =5.5V, Vi=0.4V -6 -20 m A “L ” input current 14 V CC1 =5.5V, Vi=0.4V -18 -30 m A V OH Lock output “H” output voltage 12 V CC1 =5.5V 5.0 V V OL “L ” output voltage 12 V CC1 =5.5V 0.3 0.5 V V BS Band SW Output voltage 5 to 8 V CC2 =12V, Io=-40mA 11.6 11.8 V I OLK1 Leak current 5 to 8 V CC2 =12V band SW is OFF -10 m A V TOH Tuning output Output voltage “H” 10 V CC3 =33V 32.5 V V TOL Output voltage “L ” 10 V CC3 =33V - 0.2 0.4 V IOH Charge pump “H” output current 9 V CC1 =5.0V, Vo=2.5V -– 270 –370 mA IOL “L ” output current 9 V CC1 =5.0V, Vo=2.5V - –70 –110 mA ICPLK Leak current 9 V CC1 =5.0V, Vo=2.5V -- –50 nA ICC1 Supply current 1 3 V CC1 =5.5V - 20 30 mA ICC2A Supply current 2 4 circuits: OFF 4 V CC2 =12V -- 0.3 mA ICC2B 1 circuits: ON, Output: OPEN 4V CC2 =12V - 6.0 8.0 mA ICC2C 1 circuits: ON, Output current 40mA 4V CC2 =12V Io=-40mA - 46.0 48.0 mA ICC3 Supply current 3 11 V CC3 =33V Output ON - 3.0 4.0 mA Symbol Parameter Test pin Test conditions Limits UnitMin. Typ. Max. fopr Prescaler operating frequency 1 VCC1 =4.5 to 5.5V Vin=Vinmin to Vinmax 80 - 1000 MHz Vin Operating input voltage 1 VCC1 =4.5 to 5.5V 80 to 100MHz -24 - 4 dBm100 to 200MHz -27 - 4 200 to 800MHz -30 - 4 800 to 1000MHz -27 - 4 tPWC Clock pulse width 13 V CC1 =4.5 to 5.5V 1 -- m s tSU (D) Data setup time 14 V CC1 =4.5 to 5.5V 2 -- m s tH (D) Data hold time 14 V CC1 =4.5 to 5.5V 1 -- m s tSU (E) Enable setup time 15 V CC1 =4.5 to 5.5V 3 -- m s tH (E) Enable hold time 15 V CC1 =4.5 to 5.5V 3 -- m s tINT Enable data interval time 15, 14 V CC1 =4.5 to 5.5V 1 -- m s tr Rise time 13, 14, 15VCC1 =4.5 to 5.5V -- 1 ms tf Fall time 13, 14, 15VCC1 =4.5 to 5.5V -- 1 ms tbt Next enable prohibit time 15 V CC1 =4.5 to 5.5V 5 -- m s tbcl Next clock prohibit time 13, 15 V CC1 =4.5 to 5.5V 5 -- m s

MITSUBISHI ICS (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR METHOD OF SETTING DATA The frequency demultiplying ratio uses 15bits. Setting up the band switching output uses 4bits. The test mode data uses 8bits. The total bits used is 27bits. Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal. The program counter data is read into the latch by the fall of the enable signal after the 18th pulse of the clock signal or the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 18th pulse of the enable signal, only the band SW data is updated and other data is ignored. The shift register is equipped with the 18/19 bit automatic decision function. When the 18th bit data is used, the M9 bit of the program counter is reset and the 1/512 division of the reference frequency is set. In case of the 19th bit, 1/1024 division of the reference frequency is set. BS4 BS3 BS2 BS1 2 8 27 26 25 24 23 22 21 20 24 23 22 21 20 ENA DATA CLK BAND SW DATA READ INTO LATCH M COUNTER DIVISION RATIO SETTING S COUNTER DIVISION RATIO SETTING READ INTO LATCH M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 (2) Transfer of the 19th bit data The data is latched at the 19th pulse of the clock signal. At this time, 1/1024 frequency division ratio is used. Clock signals after the above are invalid. Notice) To change reference frequency, set up as ENA in "L" after 19th pulse of clock signal by all means BS4 BS3 BS2 BS1 2 8 27 26 25 24 23 22 21 20 24 23 22 21 20 ENA DATA CLK BAND SW DATA READ INTO LATCH M COUNTER DIVISION RATIO SETTING S COUNTER DIVISION RATIO SETTING READ INTO LATCH M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0M9 (1) Transfer of the 18th bit data Data is latched by the fall of the enable signal after the 18th clock signal. At this time, the division of the 1/512 of the reference frequency is used.

MITSUBISHI ICS (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR METHOD OF SET THE DIVIDING RATIO OF THE PROGRAMMABLE DIVIDER (1) Transfer of the 18th bit data Total division N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 (32M+S) M:9 bit main counter division S:5 bit swallow counter division The M and S counters are binary the possible ranges of division are as follows. 32£M £511 0£S£31 Therefore, the range of division N is 8,192 to 131,064. The tuning frequency f VCO is given in the following equations. fVCO =fREF ·N =7.8125·8·(32M+S) =62.5·(32M+S) [kHz] Therefore, the tuning frequency range is 64MHz to 1023.9375MHz. (2) Transfer of the 19th bit data Total division N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 (32M+S) M:10 bit main counter division S:5 bit swallow counter division The M and S counters are binary the possible ranges of division are as follows. 32£M £1023 0£S£31 Therefore, the range of division N is 8,192 to 262,136. The tuning frequency f VCO is given in the following equations. fVCO =fREF ·N Therefore, the tuning frequency range is 32MHz to 1023,9687MHz. TEST MODE DATA SET UP METHOD The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls. (1) When transferring 3-wire 27bit data ENA T2 T1 T0 RSa RSb OS TEST DATA SETTING CLK S1 CPBAND SW DATA M COUNTER DIVISION RATIO SETTING S COUNTER RATIO SETTING 1 19 20 27 READ INTO LATCH DIVISION

MITSUBISHI ICS (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR (2)Test mode bit set up X :Random, 0 or 1. normal “0” CP :Set up the charge pump current value T0, T1, and T2 :Set up test modes RSa, RSb :Set up for the reference frequency division ratio OS :Set up the tuning amplifier SI :1 only (It is prohibit to “0”) Setting up the charge pump current of the phase comparator Setting up for the test mode * Built-in pull up resistor, and the resistor is unnecessary. Set up for the reference frequency division ratio Set up the tuning amplifier POWER ON RESET OPERATION (Initial state the power is turned ON) BS4 to BS1 : OFF Charge pump : High impedance Tuning amplifier : OFF Charge pump current : 270mA Frequency division ratio : 1/1024 Lock detect : “H” CP Charge pump current Mode 07 0 mA Test 1 270 mA Normal T2 T1 T0 Charge pump 12 pin output Mode 0 0 X Normal operation LD Normal operation 0 1 X High impedance LD Test mode 1 1 0 Sink LD Test mode 1 1 1 Source LD Test mode 1 0 0 High impedance f REF Test mode 1 0 1 High impedance f1/N Test mode RSa RSb Frequency ratio 1 1 1/512 0 1 1/1024 X 0 1/640 OS Tuning voltage output Mode

0 ON Normal

1 OFF TestTIMING DIAGRAM

CRYSTAL OSCILLATOR CONNECTION DIAGRAM ENABLE VIH VIL VIH VIH VIL VIL DATA CLOCK tr tf 90% 1.5V 10% tINT 1.5V 10% 90% tr tf 90% 10% tINT 90% 10% tH(E) tftr 10% 90% 10% 90% tH(D) tSU(E) tSU(D) tPWC 1.5V tBT tBCL 18pF 4MHz Crystal oscillator characteristics Actual resistance: less then 300W Load capacitance : 20pF

MITSUBISHI ICS (TV) M64892AFP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR APPLICATION EXAMPLE BT BUILT-IN PLL TUNER 1000p 4-BAND TUNER UHF VHFVcc1 to 12V+5V MCU 16 11 4MHz M64892AFP/GP IF AGC 18p 1.5n 56k 100p 56k +33V BS4 BS3 BS2 BS1 Vcc2 fIN PD GNDXIN DATA CLK LD/f1/N SW 1000p 0.1m Lo BS1 BS2 BS3 BS4 VT IF AGC AFT Units Resistance : W Capacitance : F EN 2.2n 10m 6 87 XOUT TEST1 5 18 47k 47k 47k 47k GND 16 1000pF M5493X series +5V Note) Filter constant is * Add a capacitor to stabilize for reference. the circuit.