M64403FP

M64403FP MITSUBISHI | Alldatasheet

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Technical content

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change.

DESCRIPTION

The M64403FP performs the decoding for RS (Reed Solomon) code which primitive polynomial:P (X)=X +1 and its generation polynomial:G (X)=P (X-a j M64403FP can set the code length and check byte length, so it is able to be adopted to various systems.

FEATURES

It adopts three stages pipe line operation (Syndrome stage, Euclidean stage, Chen search & error value stage), so it realizes high speed error correction operation. Capable of erasure correcting function and it improves error correction performance.

• Where error counts (e), erasure counts (e) and design distance (d) have followed restriction. 2e + e < d Capable of parameter register programing. (1) Four kinds of code parameter which code length and check byte length are programmable. (Good for the product code that has plural code parameters.)
• Where, maximum code length (L) are 255 bytes and maximum check byte length (d-1) are 16 bytes. (2) Programmable for erasure threshold. (3) Programmable for four kinds of decoding mode. APPLICATION DVD player, DVD-ROM (DVD:Digital Video Disc), DBS (Direct Broadcasting by Satellite), High density floppy disk, Hard disk, CATV (Cable TV), MD (Mini Disc), DVC (Digital Video Cassette), DAT (Digital Audio Cassette), DCC (DIgital Compact Cassette), DVB (Digital Video Broadcast), CD-DA (Compact Disc-Digital Audio), CD-ROM (Compact Disc-Read Only Memory), other communication systems and storage media etc. PIN CONFIGURATION (TOP VIEW ) d-2 j=0 Outline 100P6S-C 100 M64403FP VSSI VDDO ELO0 DAO7 DAO6 DAO5 DAO4 DAO3 DAO2 DAO1 V SSO DAO0 ENM4 ENM3 ENM2 ENM1 ENM0 UNCF SYCR V DDO SBFB OUTR ORDY IRDY EROV TES3 TES1 V SSO VDDI CRDY EREN OTRG VDDO DAM7 DAM6 DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 V SSO ELO7 ELO6 ELO5 ELO4 ELO3 ELO2 ELO1 ADDC PWDN REST DHEF CLKO RES DOEN CLKE ERMF TESTE TESM CLKI VSSO DAI7 DAI6 DAI5 DAI4 V SSI VDDI DAI3 CSEL READ WRTE MOD0 MOD1 MOD2 DIEN LOEN NOEN V DDO VSSO DAI1 ARM3 ARM2 ARM1 ARM0 VDDO RES V SSO CLKM OMD2 OMD1 OMD0 VDDO TES7 ERAF TES2 CORF CRDF DAI2 DAI0

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. BLOCK DIAGRAM INPUT I/F SYNDROME CIRCUIT DIEN DHEF DAI0 – 7 EREN MOD0 – 2 IRDY ELO0 – 7 LOEN DAO0 – 7 DOEN ENM0 – 4 NOEN OMD0 – 2 OUTR CRDY ORDY UNCF EROV CORF ADDC OTRG ERMF REST CLKI CLKE CLKO PWDN CLKM READ WRTE CSEL ARM0 – 3 DAM0 – 7 SYCR ERAF TESTE TESM SBFB OUTPUT I/F CHEN SEARCH ERROR VALUE CIRCUIT CRDF EUCLIDEAN CIRCUIT MICRO COMPUTER I/F CONTROL CIRCUIT

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. IOL =20 IOH =-26 Symbol Unit Parameter ABSOLUTE MAXIMUM RATINGS VDD VSupply voltage VO Output voltage IOK Output parasitic diode current Tstg Storage temperature Ratings VI Input voltage mA -0.3 V IIK Input protection diode current MaxMin. +6.5 -0.3 VDD +0.3 VDD +0.3-0.3 –20 –20 150-55 2200 760 mA mA mA mA V MHz•pF IO Output current IDD VDD supply current ISS VSS supply current PdOUT Output load Output buffer@IOL =4mA Output buffer@IOL =1mA Limits Min. Typ. Max.Symbol Unit RECOMMENDED OPERATING CONDITION VDD Supply voltage Ta Input voltage Input rise & fall time Operating temperature VI tr, tf V nsec -20 VDD Parameter 4.75 5.25 500 +70 msec5 Normal input Schmit input 5.0 +25 ˚C V Limits Min. Typ. Max.Test conditions Unit

ELECTRICAL CHARACTERISTICS

(TTL interface) VDD =5.0V V Parameter 5.25 Symbol VIL V 0.8 2.2 VT+ VT- VH VOH VOL IOL IOH IIH IIL IOZH IOZL RD CI CO CIO IDD Schmitt input voltage (TTL interface) Output voltage Output current Input current Output leak current Pull down resistance Input terminal capacitance Output terminal capacitance I/O terminal capacitance Supply current V DD =5.0V VDD =5.0V VDD =5.0V, œ IO œ <1mA VDD =4.5V, VOL =0.4V VDD =4.5V, VOH =4.1V VDD5 =5.5V, VI=0V VDD5 =5.5V, VI=5.5V VDD5 =5.5V, VI=0V VDD5 =5.5V, VI=5.5V VDD5 =5.0V, VI=5.0V f=1MHz, VDD =0V VDD5 =5.0V, VI=5.0V 1.350.7 2.21.4 1.20.3 0.05 4.95 (*1) 1(*2) -4(*3) -1(*4) -1 +1 -1 +1 -1 +1 -1 +1 31 6 71 5 71 5 71 5 V V V V V mA mA mA mA mA mA mA mA kW pF pF pF mA (* 1) : Rating for 4mA output buffer (* 2) : Rating for 1mA output buffer

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. MICRO COMPUTER INTERFACE Parameter register setting method (write) is described as follows. (See page7 about sequence chart : See below diagram about micro computer I/F and register table.) 1. Perform power on reset. 2. Set various parameters (code length-1, check byte length, erasure correction threshold) to below parameter register table. 3. Set decode operation mode parameters to address-E. (See address-E description) See sequence chart page7 (micro computer I/F sequence) as for read from parameter register, see below table as for register table. Parameter register table address (Hex) R/W Initial (Hex) set data (Hex) description code (0) code length-1£FE00R/W0 00R/W1 00R/W2 00R/W3 00R/W4 00R/W5 00R/W6 00R/W7 00R/W8 00R/W9 00R/WA 00R/WB —RC ——D —R/WE ——F address (Hex) data ED 7 D6 D5 D4 D3 D2 D1 D0 means "0" fixed. D0 (bit0) 0:constrained error correction mode 1:erasure correction priority mode D3 (bit3) 0:error value output mode 1:internal correction mode code (2) code length-1 code (0) check byte length code (2) check byte length code (0) erasure threshold code (2) erasure threshold real erasure counts which is derived from syndrome calculation decode operation mode code (3) code length-1 code (1) check byte length code (3) check byte length code (1) erasure threshold code (3) erasure threshold reserve reserve code (1) code length-1 Address-E description £FE £FE £FE £10 £10 £10 £10 £10 £10 £10 £10

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. DECODE MODE SETTING METHOD Decode mode is able to set at IRDY=H. Decode mode table is as follows. Decode mode should be changed after all operations that are set before changing. Decode mode table CODE WORD INPUT METHOD Code word is able to input at IRDY=H. IRDY changes H to L when head symbol for code word is input. And IRDY changes L to H when the last symbol of code word is input. DHEF should be H and DIEN should be L when the head symbol of code word is input. DIEN is input enable signal for code word and while it's L, input data is recognized as valid data and latched to the internal circuit at rising edge of CLKI. If the syndrome calculation for the 2nd code word finishes while the 1st code word is executed at Euclidean calculation stage, the syndrome data that is latched internally is overwritten (called syndrome collision) and the correcting operation for the 1st code word is impossible. In this case, SYCR changes to H and informs external of its status. (If the last symbol of code word is input at SBFB=H, decoding is operated safely.) SYCR which changes to H is reset by system reset (REST=L). code (0) error correction MOD0 MOD1 MOD2 mode 000 100 010 110 001 101 011 111 ERASURE FLAG INPUT METHOD AND ERASURE CORRECTION MODE Erasure correcting mode is set by the setting of erasure threshold to address 8 to B for parameter register and the setting of MOD2=H for decode mode signal. Erasure flag (EREN) should input H by synchronization with symbol data of code word. Follows are about erasure threshold. (1) Constrained error correction mode is derived when the bit0 (D0) of the parameter register address-E is set to L. If the input erasure count is over the erasure threshold value the operation is adopted ordinary error correction mode by force. (2) Erasure correction priority mode is derived when the bit0 (D0) of the parameter register address-E is set to H. If the error is detected at syndrome calculation and erasure count is over the erasure threshold value, M64403FP regards its operation as uncorrectable and correcting operation doesn't execute. In any cases ( , ), EROV (erasure over flag) changes to H. code (1) error correction code (2) error correction code (3) error correction code (0) erasure correction code (1) erasure correction code (2) erasure correction code (3) erasure correction (*3) (*4) (*3) (*4)

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. OUTPUT CONTROL SIGNAL When OUTR changes to H, CORF (error detected flag), UNCF (uncorrectable flag) and EROV (erasure over flag) are output. CORF changes to L when M64403FP regards input code word as no error. CORF changes to H when M64403FP detects error. UNCF changes to H when M64403FP regards the error correction as impossible. If the input erasure flag count excesses erasure threshold value with erasure correction priority mode, UNCF changes to H also. OMD0 to OMD2 show the current operated code word's decode mode which was set by MOD0 to MOD2. INTERNALCORRECTION MODE The internal correction mode is active when the bit3 (D3) of parameter register address-E is set to H. In this internal correction mode, the code word that was input already and shown by OMD0 to OMD2 input to ELO0 to ELO7. In order to recognize the header symbol of input data, OTRG should be H by synchronization with the header symbol of code word. ADDC should be L while valid code word is input. Corrected data is output from DAO0 to DAO7 after three clocks delay. OUTR changes to H by synchronization with header symbol in order to show the header symbol of corrected code word. CRDY changes to L by synchronization with output code word. CRDF changes to H for corrected portion. In addition, ORDY changes to H while output period of information symbol in order to distinguish from code word from information symbol and check symbol. MISOPERATION FOR ODD CHECK BYTE NUMBER M64403FP have no good operation when check byte number are just d/2 (d=check byte number+1) as UNCF don't to change to H, and misdata is output. But we can judge the misoperation when ENM<4:0> indicates d/2 in error correction mode, and ENM<4:0> indicates d/2 when erasure number=0 or EROV=H in erasure correction mode. CORRECTED DATA OUTPUT METHOD When the decode operation finishes and correction result is able to output to a code word, OUTR changes to H for one period for CLKO. In this case, error location data is shown on ELO0 to ELO7, error value is shown on DAO0 to DAO7 and error correction count or erasure count is shown on ENM0 to ENM7. (Details are described later.) When output enable signals (LOEN, DOEN, NOEN) are set to L (active mode), respective data (error location, error value, error or erasure count) are able to output. When these output enable signals are set to H, respective data bus change to high impedance status. Error location data (ELO0 to ELO7) 00 hex means the location of head data for input code word. Error value data (DAO0 to DAO7) corresponds with error location data (ELO0 to ELO7). ADDC should be L for one period of CLKO in order to output next error location and next error value. (See page10 : Correction data operation sequence chart) ENM0 to ENM4 outputs error correcting count at ERMF=L, erasure count at ERMF=H. This erasure count means real error count at constrained error correction mode, total count for real error and erasure at erasure correction priority mode. And this erasure count includes empty erasure (it means error value is zero). If erasure count excesses 31 dec, ENM0 to ENM4 shows 31 dec. After the external circuit read error count/error location/error value for a code word, OTRG should change L to H only one time by synchronization with CLKO clock. Data shift for internal pipe line circuit is executed by this operation. If this operation is so late, registers in the internal pipe line become full. And data collision may occur if code word is input more and its syndrome data is generated. In this case, M64403FP informs external of its status and SYCR changes to H. (If the last symbol of code word is input at SBFB=H, decoding is operated safely.) SYCR which changes to H is reset by system reset (REST=L).

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. ERROR CORRECTION TIME M64403FP is able to perform consecutive error correction operation by bellowed three stage pipeline architecture. (operation step:A1=code length+20) (operation step:A2=See table.2) (operation step:A1=code length+20) Table. 1 Table. 1 shows the operation flow in pipe line. As for the 1st code, M64403FP output error correction data at pipe4 after 1st stage is operated at pipe1, 2nd stage is operated at pipe2 and 3rd stage is operated at pipe3. Therefore, the error correction has a latency of three stages. The maximum step count for each pipe means the maximum steps among above mentioned 1st stage to 3rd stage. Where, the design distance decides the step count at the 2nd stage. (See Table. 2) Table. 2 1st code 2nd code 3rd code 4th code pipe1 1st stage pipe2 2nd stage pipe3 3rd stage pipe4 correction pipe5 correction pipe6 3rd stage pipe7 correction 1st stage 2nd stage 1st stage 3rd stage 2nd stage 1st stage 3rd stage 2nd stage correction (Ex.1) In the case of code length=100, design distance=11 A1=100+20=120, A2=160 A2>A1 So maximum operation step for one pipe is 160. Therefore, correction data is obtained 480 steps (160 x 3) later from the input of 1st code word. Euclidean calculation steps (erasure correction) Design distance Euclidean calculation steps (error correction) 330 290 290 270 260 250 230 220 210 190 190 180 160 150 140 140 120 110 110 100

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. CORRECTING OPERATION STEPS IN PIPE LINE (Ex.1) code length=182, design distance=11 CLKI=CLKE=CLKO=25MHz error correction (no erasure) Correction data is obtained three stages later (In this case, 202*3=606clk 24.24ms) by input of consecutive code words. code word input 1st stage operation2nd stage operation 3rd stage operation correction data access period code word input 1st stage operation2nd stage operation 3rd stage operation correction data access period code word input 1st stage operation2nd stage operation 3rd stage operation correction data access period 1st code word 2nd code word 3rd code word (Ex.2) code length=208, design distance=17 CLKI=CLKE=CLKO=25MHz erasure correction Correction data is obtained three stages later (In this case, 290*3=870clk 34.8ms) by input of consecutive code words. 2nd stage operation 3rd stage operation correction data access period code word input 1st stage operation2nd stage operation 3rd stage operation correction data access period code word input 1st stage operation2nd stage operation 3rd stage operation correction data access period 1st code word 2nd code word 3rd code word code word input 1st stage operation

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. MICRO COMPUTER I/F R/W SEQUENCE CHART Note. READ=0 and WRTE=0 is inhibited at same time address data address data address #1 data #1 address #2 data #2 <WRITE> CSEL WRTE READ ARM [3:0] DMI [7:0] <READ1> CSEL WRTE READ ARM [3:0] DMO [7:0] CSEL WRTE READ ARM [3:0] DMO [7:0] <READ2>

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. CORRECTING DATA OPERATION SEQUENCE CHART (Where necessary parameter is set already.) MOD [2:0] CLKI CLKO UNCF CORF IRDY REST ERMF EROV ‹ Syndrome calculation is enable@IRDY=1:under calculation=0 ENM [4:0] 030 ERASURE COUNT=00 03 OTRG DIEN DHEF DAI [7:0] OUTR ADDC D0 D1 D2 D3 D4 D5 D0 D1 D2 D3D181 ‹ Correction data renewal enable ‹ Correcting data read finish (Renewal trigger to next step) DHEF=1, DIEN=0 are onlyheader symbol for code word. DAO [7:0] P0 P1 P2XX XX Correction data output ready ELO [7:0] L0 L1 L2XX XX OMD [2:0] ‹ Change to 1 after whole code word is input.

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. CONSECUTIVE DECODE SEQUENCE CHART (1) (Only one kind of code exists) DAI [7:0] REST UNCF CORF OUTR EROV ERMF IRDY correcting status no error status uncorrectable status Note. DAO and LOE output first error value/location @ OUTR=H. After all of error value/location for error count are output, they output zero. Error value/location output zero at no error and uncorrectable state. ENM [4:0] ELO [7:0] DHEF 1 3 4 5DAO [7:0] OTRG ADDC 54 3 1 2 3 4 5

7 WORD06 WORD05 WORD04 WORD03 WORD02 WORD01 WORD0

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. CONSECTIVE DECODE SEQUENCE CHART (2) (Ex : Two kinds of code parameter exist (Product code)) Note. DAO and LOE output first error value/location @ OUTR=H. After all of error value/location for error count are output, they output zero. Error value/location output zero at no error and uncorrectable state. REST DAI [7:0] MOD [2:0]

9 WORD m 11 WORD n 12 WORD n 13 WORD n

10 WORD m

ENM [4:0] ERMF EROV n codem code decoding operation mode for m code decoding operation mode for n code DAO [7:0] ELO [7:0] OTRG ADDC OMD [2:0] decoding operation mode for m code decoding operation mode for n code 111098

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. EXAMPLE FLOW CHART FOR GENERAL PRODUCT CODE DECODING In the case of C1fi C2 fi C1 repeat correction as a decoding method START PWDN=0 PWDN=1 REST=L fi H Set decoding mode parameter register address-E. (Example) Set C1's error corection mode for code (0) and C2's erasure correction mode for code (1) Set necessary data to the parameter register address 0 to B No Yes Code word for C1 direction Code word C2 direction -Example for product code constitution-

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. Set decoding mode Set MOD [0:2] for C1 (1st time) Recognition of header symbol for code word DHEF=1? C1 (1) decode C1 (1) decode finish? Set decoding mode Set MOD [0:2] to Recognition of header symbol for code word DHEF=1? C2decode decode finish? Set decoding mode Set MOD [0:2] to C1 (2nd time) C1 (2) decode C1 (2) decode finish? Yes No No Yes No No Yes No No Yes Yes Yes Recognition of header symbol for code word DHEF=1?

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. INPUT TIMING CLKI DAI<7:0> EREN DIEN MOD<2:0> DHEF TESTE tsu (CLKI) th (CLKI) tc (CLKI) tw (CLKI) Limits (Min.)Symbol Unit tc (CLKI) CLKI clock period tw (CLKI) CLKI setup time CLKI clock pulse width tsu (CLKI) ns Parameter CLKI hold timeth (CLKI) 10 ns ns ns CLKO OTRG ADDC ELO<7:0> tsu (CLKO) th (CLKO) tc (CLKO) tw (CLKO) Symbol Unit tc (CLKO) CLKO clock period tw (CLKO) CLKO setup time CLKO clock pulse width tsu (CLKO) ns Parameter CLKO hold timeth (CLKO) 10 ns ns ns ARM<3:0> CSEL WRTE DAM<7:0> tcw tsu (A) tsu (C) trec (W) tw (W) tsu (D) th (D) Symbol Unit tcw Write cycle time tsu (A) Chip select setup time Address setup time tsu (C) ns Parameter Write recovery timetrec (W) 10 ns ns ns tw (W) Data setup time Write ulse width tsu (D) data hold timeth (D) 10 ns 5n s 10 ns Limits (Min.) Limits (Min.)

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. OUTPUT TIMING At output load capacity=50pF Limits (Max.)Symbol Unit td (CKO) CLKO output propagation time ns Parameter CLKO ENM<4:0> DAO<7:0> ELO<7:0> UNCF CORF OUTR OMD<2:0> td (CKO) Symbol Unit td (CKI) CLKI output propagation time ns Parameter CLKI SYCR td (CKI) Symbol Unit ta (OE) Output enable time ns Parameter tdis (OE) Output disable time ns15 LimitsSymbol Unit tcr Read cycle time ns Parameter 40 (min) ta (A) Address access time ns ta (C) Chip select access time ns ta (R) Output enable access time ns tdis (C) Output disable access time (from CSEL) ns tdis (R) Output disable access time (from READ) ns 10 (max) 10 (max) 10 (max) 10 (max) 10 (max) NOEN DOEN LOEN ENM<4:0> DAO<7:0> ELO<7:0> ta (OE) tdis (OE) ARM<3:0> CSEL READ DAM<7:0> tcr ta (A) ta (C) ta (R) tdis (C) tdis (R) Limits (Max.) Limits (Max.)

MITSUBISHI ICs (LSI) ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE PRELIMINARY Notice:This is not a final specification. Some parametric limits are subject to change. Pin No. DESCRIPTION OF PIN 1, 23, 40, 53, 70, 88 Description of functionI/O structure 28, 80 29, 52 6 to 8 Name VSSI VDDI NOEN LOEN DIEN MOD2 to MOD0 WRTE READ CSEL PWDN I/O I TTL schmitt trigger input I/O type T22N TTL input TTL input TTL input TTL input T22N T22N T22N U22N VSSO 2, 38, 45, 61, 79, 97VDDO 16, 39 24 to 27 30 to 33 34 to 37 42 to 44 64 to 68 78, 81 to 87 89 to 96 100 69, 71 to 77 RES REST DHEF CLKO DOEN CLKE ERMF TESTE TESM DAI7 to DAI4 CLKI DAI3 to DAI0 ARM3 to ARM0 CLKM OMD2 to OMD0 TES7 ENM0 to ENM4 ERAF TES2 CORF CRDF CRDY TES1 TES3 EROV IRDY ORDY OUTR SBFB SYCR UNCF DAO0 to DAO7 ELO0 to ELO7 DAM0 to DAM7 OTRG EREN ADDC I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O I/O I/O I I I TTL schmitt trigger input TTL schmitt trigger input TTL schmitt trigger input TTL schmitt trigger input TTL schmitt trigger input TTL input TTL input TTL input TTL input TTL input TTL input TTL schmitt trigger input TTL input TTL output (4mA) TTL3 state output (4mA) TTL I/O (Pull down Rd=2kW ) TTL input U22N U22N U22N U22N T22N U22N T22N T22N T22N T22N T22N U22N T22N T22N O65T O65T O63T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T Z65T Z65T TH2N TH2N T22N O65T T22N fl fl fl GND for output +5V for output reserve GND for input +5V for input output enable for ENM0 to 4 0:Enable 1:HiZ output enable for ELO0 to 7 0:Enable 1:HiZ Symbol data input enable 0:Enable decoding mode setting MOD2:MSB MOD0:LSB micro computer I/F write enable 0:Enable micro computer I/F read enable 0:Enable micro computer I/F chip select 0:Select power save 0:power save system reset 0:Reset symbol data header 1:Data head data output clock (Typ.13.5MHz) output enable for DAO0 to 7 0:Enable 1:HiZ internal operation clock (Typ.13.5MHz) output enable for ENM0 to 7 1:erasure counts 0:correcting counts test mode selection 0:decoding 1:testing symbol data input clock (Typ.13.5MHz) symbol data input bus DAI7:MSB micro computer I/F address bus ARM3:MSB ARM0:LSB CLKI monitor (Typ.13.5MHz) decoded operation mode (relative to MOD0 to 2) test monitor output erasure flag output 1:Enable test monitor output error detection flag 0:No Error 1:detected correction flag 1:corrected data output valid flag 0:valid test monitor output test monitor output erasure over flag 1:over symbol data input ready 1:Ready data flag 0:data output ready 1:Ready/output data header (@ internal correction mode) 1:header syndrome data collision prevention signal syndrome data collision alarm 1:alarm (collision) uncorrectable flag 1:Uncorrect error correction counts/erasure counts output bus ENM4:MSB ENM0:LSB error value output bus DAO7:MSB DAO0:LSB data input (for correction) /error location output bus ELO7:MSB ELO0:LSB micro computer I/F bus DAM7:MSB DAM0:LSB renewal trigger 0fi 1:renewal/input data (@internal correction mode) 1:header erasure flag input 1:@erasure input output data renewal 0:Next/code word valid (@internal correction mode) 0:valid DAI0:LSB test mode selection 0:decoding 1:testing TTL input TTL output (4mA) TTL output (1mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL3 state output (4mA) TTL I/O (Pull down Rd=2kW ) TTL input TTL output (4mA) fl