M62023L MITSUBISHI | Alldatasheet

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MITSUBISHI <Dig./Ana.INTERFACE> SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP M62023L,P,FP PRELIMINARYPRELIMINARYNotice:This is not a final specification. Some parametric limits are subject to change. GENERAL DESCRIPTION The M62023L/P/FP is a system reset IC that controls the memory backup function of an SRAM and an embedded RAM of a microcontroller. The IC outputs reset signals (RES/RES) to a microcontroller at power-down and power failure. It also shifts the power supply to RAMs from main to backup, outputs a signal (CS) that invokes standby mode, and alters RAMs to backup circuit mode.

FEATURES

  • Built-in switch for selection between main power supply and back- up power supply to RAMs
  • Small difference between input and output voltages (IOUT =80mA, VIN=3V) : 0.15V typ
  • Detection voltage (power supply monitor voltage) : 2.57V typ
  • Chip select signal output (CS)
  • Two channels of reset outputs (RES/RES)
  • Power on reset circuit APPLICATION Power supply control systems for memory of microcontroller systems in electronic equipment such as OA equipment, industrial equipment, and home-use electronic appliances and SRAM boards with built-in backup function that require switching between external power supply and battery. 1 4 8 CS

7 RES

6 GND

5 RES

3 VIN

2 VBAT

1 VOUT

PIN CONFIGURATION (TOP VIEW) Outline 8P5 (L) Outline 8P4 (P) 8P2S-A (FP) Com GND RESET CIRCUIT 1.24V R 1 R 2 SW DELAY CIRCUIT7 D 1 VOUT VBAT CS C t VIN RES RES BLOCK DIAGRAM

MITSUBISHI <Dig./Ana.INTERFACE> SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP M62023L,P,FP PRELIMINARYPRELIMINARYNotice:This is not a final specification. Some parametric limits are subject to change. VOL(RES) VOH(RES) Detection voltage Test Conditions Limits VS 2.44 V Hysteresis voltage mV mA Delay time ICC Circuit current Difference between input and output voltages ΔVS 2.70 0.1 0.2 0.15 0.3 ELECTRICAL CHARACTERISTICS (Ta=25°C, unless otherwise noted) ΔVS=VSH -VSL IOUT =0mA 2.57 50 200100 6.5 V ms µs ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted) Input voltage Output current Symbol Parameter Conditions Ratings Unit VIN IOUT mA V 100 Pd Power dissipation 800(L)/625(P)/440(FP) mW Thermal derating mW/°C Topr Tstg Operating temperature Storage temperature -20 to +75 -40 to +125 Ta ≥ 25°C VDROP VOH(C t) VOL(C t) VOH(RES) VOH(CS) VOL(CS) IR VF tpd td VOPL(RES) C t output voltage (high level) Backup Di forward direction voltage Backup Di leak current Response time RES limit voltage of operation VIN=2V VIN=3V IOUT =50mA IOUT =80mAVIN=3V VIN=3V (Note 1) VIN=3V Isink=1mA VIN=0V, VBAT =3V (Note 2) VBAT =3V VIN=0V VIN=3V IF=10µA VIN=0V 3V, Ct=4.7µF VIN=3V 2V (Note 3) V V V V V V V V µA V V Note 1. Regarding conditions to measure VOH and VOL , voltage values are generated by internal resistance only and no external resistor is used. 2. These values are produced inserting an external resistor, RCS =1M Ω , between the CS pin and GND. 3. With no external resistor (10KΩ internal resistance only) 1.5 3.0 2.42.0 0.02 0.1 2.01.5 0.02 0.04 0.2 3.02.5 0.02 0.04 0.2 1.61.3 2.472.40 0.07 0.08 0.3 ±0.5 0.54 0.6 27 5510 5.0 25.0 0.65 K Symbol Parameter UnitMin Typ Max VOL(RES) C t output voltage (low level) RES output voltage (high level) RES output voltage (low level) RES output voltage (high level) RES output voltage (low level) CS output voltage (low level) CS output voltage (high level) VIN (At charge from H L) VIN=2V (Note 1) VIN=2V (Note 1) (Note 1) VIN=2V Isink=1mA VIN=3V (Note 1) (Note 1) VIN=2V (Note 2) VIN=3V Isink=1mA (Note 1) ±0.5 2 4

MITSUBISHI <Dig./Ana.INTERFACE> SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP M62023L,P,FP PRELIMINARYPRELIMINARYNotice:This is not a final specification. Some parametric limits are subject to change. VBAT Com 1.24V R 1 R 2 VIN RES RES MCU or CPU +3V (MAIN POWER SUPPLY) VDD C IN GND RESET CIRCUIT SW DELAY CIRCUIT M62023 D 1 VOUT VBAT CS C t VDDBATTERY CMOS RAM C OUT C t EXPLANATION OF TERMINALS VIN and VBAT are controlled by means of an internal switch and output through VOUT . The pin is capable of outputting up to 100 mA. Use it as VDD of CMOS RAM and the like. Backup power supply is connected to this pin. If a lithium battery is used, insert a resistor in series for safety purposes. +3V input pin. Connect to a logic power supply. A delay capacitor is connected to this pin. By connecting a capacitor, it is possible to delay each output. Connect to the positive reset input of a microcontroller. The pin is capable of flowing 1mA sink current. Reference for all signals Connect to the negative reset input of a microcontroller. The pin is capable of flowing 1mA sink current. Connect to the chip select of RAM. The CS output is at low level in normal state thereby letting RAM be active. Under failure or backup condition, the CS output is set to high level, then RAM enters standby state disabling read/write function. The pin is capable of flowing a 1mA sink current. Power supply output Backup power supply input Pin No. Name Function VIN Power supply input Delay capacitor connection pin Positive reset output Ground Negative reset output Chip select output Symbol VOUT C t RES GND CS RES APPLICATION EXAMPLE Capacitance to be connected: CIN: 10µF; COUT : 4.7µF; Ct: 4.7µF 3 4

MITSUBISHI <Dig./Ana.INTERFACE> SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP M62023L,P,FP PRELIMINARYPRELIMINARYNotice:This is not a final specification. Some parametric limits are subject to change. TIMING CHART V1=VIN-VDROP V2=VIN-VEB(SW Tr.) V3=VBAT -VF VSH VSL ΔVS tpd tpd VIN VOUT V1 V2 V3 VIN(VSL) VOL(CS) VOL(RES) VOL(RES) VIN(VSL) VOH(RES) CS RES RES As the state shifts from a logic high to logic low, the output level becomes VOL(RES) The output level is VOL(CS) with a logic low The output level is VOH(RES) with a logic high In normal operation Input voltage : 3V Input voltage VOUT RES CS RES Output pin With SW Tr. set to ON, a voltage (VIN-VDROP ) is output The output level is VOL(RES) with a logic low In failure (instantaneous drop) Input voltage : 3V 2V Each output varies if the input voltage drops to VSL or underSW Tr. is turned OFF. A voltage (VIN-VEB ) is output by the diode between E and B of SW Tr. As the state shifts from a logic low to logic high, the output level becomes approximately equal to the input voltage Restoration from failure (instantaneous drop) Input voltage : 2V 3V If the input voltage goes higher than VSL by 100mV, each output varies after delay produced by the delay circuit SW Tr. is turned ON after delay and a voltage (VIN-VDROP ) is output A logic high is maintained, and then shifts to a logic low In backup state Input voltage : 0V Backup voltage : 3V VBAT -VF The output is a logic high and the output level is VBAT -VF As the state shifts from a logic low to logic high, the output level becomes the voltage VIN-VEB A logic low is maintained, and then shifts to a logic high A logic high is maintained, and then shifts to a logic low 4 4