M5M82C54P

M5M82C54P MITSUBISHI | Alldatasheet

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. Cy . MITSUBISHI LSIs i oot , ene M5M82C54P,-6 _ Seber 2) = Lasers ach . rey =F as wake SMS ee Ab a ee he CMOS PROGRAMMABLE INTERVAL TIMER oe op f 6249828 MITSUBISHI CMICMPTR/MIPRC) 91D 11984 DO . ae DESCRIPTION - PIN CONFIGURATION (TOP rn ante a. i The MSMB2CS4P,-6 Is @ programmable general-purpose tim- u ( ‘W) 2 | er device developed by using the silicon-gate CMOS pro- H f cess. It offers counter and timer functions in systems using 3 : an 8-bit parallel-processing CPU. The use of the > 7] 24) Voc (SV) rar j MSM&2C54P,-6 frees the CPU from the execution of looped Ds [2] [23] WA write INPUT 3 q programs, count-operation programs and other simple pro- vs ~+[3 [2— AB READ INPUT 5 cessing involving many repetitive operations, thus contribut- BIDIREC- | Ds [4] z [2i-—cs CHIF-SELECT 3 Ing to Improved system throughputs. The MSMB2C54P.-6 } pata sus|O-[5] & [A Jaooness a works on a single power supply, and both Its input and out- of] = Bg JINPUTS 2 put can be connected to a TTL circuit. Dd g [T8]—cLk2 Lock INPUT a -| ia COUNTER a of] D-oure Sonate 2 [ccewok puso wm | gpm | sire | | cuocemeurcuc~{5] —_(j~onrex te nour fs) ‘COUNTER — [lock tow puise with | ean | ttn oureur ov Og Pl CuK! crook hor a Joicck ecto time [eine [tire | OME NPT cared LT ee ere - - f—ourt & : ‘Propagation time one (ovyeno [| T3]—-ourt SOUNTER from read to output 3 Outline 24P4 =m FEATURES r © Single 5V supply voltage u . © TTL compatible FUNCTION wo Pin'connection compatible with M5L8253P-5 Three independent 16-bit counters allow free programming i - @ Clock period : MSMB2C54P-6 -*++-++1-++++-+-+* DO~6MHz based on mode-control instructions from the CPU. When v MBMB2C54P vv-s-v-sseessseeneees DO—BMH2 roughly classified, there are 6 modes (0~8). Mode 0 Is main- @ 3 independent bult-in 16-bit down counters ly used as an interruption timer and event counter, mode 1 3 @ 6 counter modes freely assignable for each counter as a digital one-shot, modes 2 and 3 as a rate generator, e @ Binary or decimal counts mode 4 for a software triggered strobe, and mode 5 for a hy @ Read-back command for monitoring the count and status’ _ hardware triggered strobe. . o . The count can be monitored and set at any time. Besides . + APPLICATION ‘the count, the status of the counter can be monitored by uw Delayed-time setting, pulse counting and rate generation In Read-back command. The counter operates with either the microcomputers. binary or BCD system. = BLOCK DIAGRAM mn WORD (ov) not REGISTER a = CLK 0 CLOCK INPUT : b i COUNTER! (GATE 0 GATE INPUT ed |_—-¢dour» counter oureur by o—| pata: PF? i BIDIF D, - . FBRTABOS) ps eI ots ia PG! etock eur 0:6)-—+| 7+ {CONTER).—(O) GATE 1 GATE INPUT ‘ aQ— | }OUT | COUNTER OUTPUT i READ INPUT RD o- (9cuK 2 CLOCK INPUT ! . + WRITE INPUT RO READ/ 4 b—6 GATE 2 GATE INPUT A CHIP-SELECT INPUT TS o—4 tous (out 2" COUNTER OUTPUT ADDRESS INPUT! INTERNAL | . , ate MirsuBisH _ | : ELECTRIC

MIT: WITSUBISHIAMECNPTR/MIPRC} 4% DE Levsaea cowsas 4 fh SUBISHI LSIs . MSM82CS54P,-6 Sea 8a a r 6249828 MITSUBISHI (MICMPTR/MIPRG) 91D 11985 DT-S/-/7 ars te CMOS PROGRAMMABLE INTERVAL TIMER Hees Sai Hal Se ea heise ees i . DESCRIPTION OF FUNCTIONS CONTROL WORD AND INITIAL-VALUE LOADING Data-Bus Butter : The function of the M5M82C54P,-6 depends on the system | This 3-state, bidirectional, 8-bit buffer is used to interface software. The operational mode of the counters can be spe- 5 the MSM82C54P,-6 to the system-side data bus. Transmis- ified by writing control words (Ao, Ai=1, 1) into the control- i sion and reception of all the data including control words for word registers. i mode designation and values written in, and read from, the The programmer must write out to the MSM82C54P,-6 the ‘ counters are carried out through this buffer. programmed number of count register bytes (1 or 2) prior to - Read/Write Logic actually using the selected counter, The read/write logic accepts control signals (RD, WR) from Fig. 1 shows control-word format, which consists of 4 fields. the system and generates control signals for each counter. It Only the counter selected by the D; and De bits of the con- \\s enabled or disabled by the chip-select signal (CS); if CS__ trol word Is set for operation. Bits Ds and D, are used for Is at the high-level the data-bus buffer enters a floating specifying operations to read values in the counter and to in- (high-impedance) state. itialize, Bits Ds~D; are used for mode designation, and Do Read Input (RD) for specifying binary or BCD counting. When Do=0, binary The count of the counter designated by address inputs Ay counting is employed, and any number from 0000\\¢ to FFFFi¢ . and A; on the low-level is output to the data bus. can be loaded into the count register. The counter Is Write Input (WR) counted down for each clock. The counting of 0000;5 causes Data on the data bus Is written in the counter or control-word the transmission of a time-out signal from the count-output register designated by address inputs Ay and A; on the low- pin. ~ . level. The maximum number of counts is obtained when 0000s Is Address Inputs (Ag, Ay) set as the initial value. When Do=1, BCD counting is em- These are used for selecting one of the 3 internal counters ployed, and any number from 0000j9 to 999910 can be loaded and either of the control-word registers, ‘on the counter. Chip-Select Input (CS) . Neither system resetting nor connecting to the power supply A low-level on this input enables the M5M82C54P,-6. sets the control word to any specific value. Thus to bring the Changes in the level of the CS input have no effect on the counters into operation, the above-mentioned control words operation of the counters, for mode designation must be given to each counter, and Control-Word Register then 1~2 byte initial counter values must be set. The follow- This register stores information required to give instructions _ ing Is an example of this programming step. about operational modes and to select binary or BCD count- To designate mode 0 for counter 1 .with Initial value 8253;¢ ing. It allows reading,using Read back command. set by binary count, the following program Is used: Counters 0,1 and 2 MV A, 70,5 Control word 706 These counters are Identical in operation and independent OUT nm ny Is control-word-register address of each other, Each Is a 16-bit, presettable, down counter, MVI A, 53 Low-order 8 bits, and has clock-input, gate-input and output pins. The counter. OUT nz ny is counter 1 address can operate in either binary or BCD using the falling edge of MVI A, 824, High-order8 bits each cléck. The mode of counter operation and the initial OUT ng nz is counter 1 address value from which to start counting can be designated by Thus, the program generally has the following sequence: ‘software. The count can be read by input instruction at any (1) Control-word output to counter i (i=0,1,2). - time, and there Is a “read-on-the-fly” function which enables (2) {nitialization of low-order 8 counter bits stable reading by latching each instantaneous count to the (3) Initialization of high-order 8 counter bits registers by a special counter-latch instruction. The three counters can be executed in any sequence, It Is . . Possible, for instance, to designate the mode of each coun- ter and then load initial values in a different order. Initializa- | - tion of the counters designated by RL 1 and RL 0 must be ! . executed In the order of the low-order 8 bits and then the : high-order 8 bits for the counter in question, i . i | . i | 6-72 . 9 MITSUBISHI ELECTRIC

MITSUBISHI{MICHPTR/MIPRC} TL DEPP ee4dsea 0011986 & A MITSUBISHI LSIs . M82CS54P,-6 ee . iy 6249828 MITSUBISHI (MICMPTR/MIPRO) 910 11986 © DT-SI-/7 Bae

2 RS 7 CMOS PROGRAMMABLE INTERVAL TIMER eS ae

{ Table 1 Basic Functions . | [es me rete 4 0 1 0 0 0 ‘Deta bus-+Counter 0 q ° 1 0 0 1 ‘Data bus-+Counter 1 ‘| C) 1 ° 1 t) Data bus-+Counter 2 q ° 1 0 1 1 (Data bus-*Control-word register 0 oO 1 0 0 ‘Data bus~-Counter 0 ’ o 0 i 0 1 Data busCounter 1 ° 0° 1 1 o Data bus+-Counter 2 0 oO 1 1 1 3-state - 1 “x x x x 3-state 0 1 1 x x 3-state > —— ©8G(Select Counter) scl sco [oT oJ setest countero [oft J setect counters [tf 0 | sotect counter? [TF rrenitos combination | : @RL(Read/Load) . - . ALI RLO [2 [0 [ecuntertotch command | |9 | 1 [Reaaroadiow-order8 bis ony [1 [0 | Resdrcad tgh-order 8 bts only [-1_[ 1. | Read/ioad low-order @ bts and then high-order 8 bits @M(Mode) M2 MI MO po Joo Joo J Moco | a a ee ee ee ee . ; a = @BCD Dy De Ds yest» [ 1 Bnry-codes docimal counter (4 decodes) | [scr | sco] mur] reo [ we J mi Two [aco : Fig. 1 Control-Word Format . MITSUBISHI : anes 8-78

NITSUBISHI{NICHPTR/MIPRC} 4 DEPfbe49828 0011987 6 I. MITSUBISHI LSIs ‘ SM82C54P,-6 SR 6249528 MITSUBISHI (MICMPTR/MIPRC) 910 11987 DSF Er ee: aa ae : CMOS PROGRAMMABLE INTERVAL TIMER ee tae ae ED ! : | . MODE DEFINITION * started and on the terminal count, the output will go low for | Mode 0 (interrupt on Terminal Count) ‘one Input-clock period and then will go high again. Mode 4 | Mode set and initialization cause the counter output to go differs from Mode 2 in that pulses are not output repeatedly | low-level (see Fig. 2). When the counter is loaded with an with the same set count. The pulse output Is delayed one i + Initial value, it will start counting the clock input. When the clock period In Mode 2, as shown in Fig. 6 . When a new terminal count Is reached, the output will go high and remain Value Is loaded into the count register during its count op- ] high until the selected count register Is reloaded with the eration, It Is reflected on the next pulse output without mode. This mode can be used When the CPU Is to be inter- affecting the current count. The count will be inhibited while . rupted after a certain period or at the time of counting up. the gate input is low-level. Fig. 2 shows a setting of 4 as the initial value. If gate input Mode 5 (Hardware Triggered Strobe) goes low, counting Is inhibited for, the duration of the low- This is a variation of Mote 1. The gate Input provides a trig- level period. Ger function, and the count is started by its rising edge. On Reloading of the initial value during count operation will stop the terminal count, the counter output goes low for on one counting by the loading of the first byte and start the new clock period and then goes high. As In Mode 1, retriggering count by the loading of the second byte. by the gate input is possible. An example of timing in Mode Mode 1 (Programmable One-Shot) 51s shown In Fig. 7. The gate input functions as a trigger input. A gate-input ris- As mentioned above, the gate input plays different roles ing edge causes the generation of low-level one-shot output according to the mode. The functions are summarized in with a predetermined clock length starting from the next Table 3. . clock. Fig. 3 shows an initial setting of 4. While the counter . output Is at the low-level (during one-shot), loading of anew Table 2 Gate Operations . value does not change the one-shot pulse width, which has already been output. The current count can be read at any NR Ee time without affecting the width of the one-shot pulse being | wea Mode 2 (Rate Generator) Low-level pulses during one clock operation are generated ie eee from the counter output at a rate of one per n clock inputs after next clock (where n Is the value Initially set for the counter). When a new value Is loaded during the counter operation, it is re- } Disables coumtoa | {3} riches scemter, flected on the output after the pulses by the current count Immediately have been output. In the example shown in Fig. 4 , n is given as 4 at the outset and is then changed to 3. Hy Disables counting 8 Reloads counter Enablos. In this mode, the gate input provides a reset function. While @) Sels culpa hon 2) Inietes counting | counting it Is on the low-level, the output Is maintained high; the : counter restarts from the initial value, triggered by a rising Enabioe gate-input edge. This gate input, therefore, makes possible ee ‘external synchronization of the counter by hardware. Ls | __[rmtescomins | | After the mode is set, the counter does not start counting un- til the rate n Is loaded into the count register, with the coun- ter output remaining at the high-level. Mode 3 (Square Rate Generator) This Is similar to Mode 2 except that it outputs a square wave with the half count of the set rate. When the set value nis odd, the square-wave output will be high for (n+1)/2 clock-input counts and low for (n—1)/2 counts. When a new ‘ fate Is reloaded into the count register during its operation, it . Is immediately reflected on the count directly following the j output transition (high-to-low or low-to-high) of the current . | count. Gate-input operations are exactly the same as In - ' | Mode 2. Fig. 5 shows an example of Mode 3 operation. Hi i Mode 4 (Software Triggered Strobe) After the mode Is set, the output will be high. By loading a | number on the counter, however, clock-input counts can be i : i 6-74 9 MITSUBISHI | ELECTRIC : |

MITSUBISHI{MICMPTR/MIPRC} 91 re | be4dses 0011986 0 r MITSUBISHI LSIs. . . . MSM82C54P,-6 - igh 6249828 MITSUBISHI (MICMPTR/MIPRO) sip 11988 =D 7-S/-19 cee eave ener : - CMOS PROGRAMMABLE INTERVAL TIMER | SS hee CLK i WR (n=4)) fe 32H ourin=a) cee F OUT(GATES"H") i 4 my pe 2 i OUT(n=5) | wa ; | H i coate - GATE t 7 4 2 42 4 our a en | . Fig, 2 Mode O Fig. 6 Mode 3 ok STULL. uk ULL, a _ WA (n=a) wR Le) GATE 3204 4 3 21 out 1 J OUT a ae y Fi stis our 302 4 32 1 t ou’ Fig. 3 Mode 1 Fig. 6 Mode 4 /euk UPL ULL uk ULL, OUT(GATE="H") OUT(n=4) 4 4 3 21 2 1 OUT ouT(n=4) Fig. 4 Mode 2 . Fig. 7 Mode & COUNTER MONITORING Read-on-the-Fly Operation . Sometimes the counter must be monitored by reading its This method makes it possible to read the current count count or using it as an event counter. The M5SM82C54P,-6 without affecting the count operation at all. A special coun- offers the following two methods for count reading: ter-latch command is first written In the control-word regis- Read Operation ter. This causes latching of all the instantaneous counts to The count can be read by designating the address of the _ the register, allowing retention of stable counts. An example counter to be monitored and executing a simple I/O read of a program to execute this operation for counter 2 is given operation. In order to ensure correct reading of the count, it below. Is necessary to cause the clock input to pause by external mv A, 1000XXXX ---- D5 =D4=0 designates counter fogic or prevent a change in the count by gate input. An ex- latching ample of a program to read the counter 1 count Is shown be- OUT =n, --- n; Is the control-word-register address tow. If RL1, RLO=1, 1 has been specified in the control word, IN Ng *- n3 is the counter 2 address the first IN instruction enables the low-order 8 bits to be read MOV D,A and the second IN instruction enables the high-order 8 bits. IN ns . i IN ‘Ng ** nz is the counter 1 address MOV EA : MOV D,A in this example, the IN instruction is executed twice. Due to : IN nm the internal logic of the M5M82C54P,-6 it is absolutely MOV E,A essential to complete the entire reading procedure. If two The IN Instruction should be executed once or twice by the bytes are programmed to be read, then two bytes must be H RLI and RLO designations in the control-word register. read before any OUT Instruction can be executed to the | . . . same counter.

9 MITSUBISHI ~ 6-75

: ELECTRIC

NITSUBISHI{MICHPTR/MIPRC} 4 DEB beyqaes 0011989 1 ff MITSUBISHI LSIs : MSM82C54P,-6

6240828 MITSUBISHI (MICMPTR/MIPRO)- gin 11989 DSI bens

Se CMOS PROGRAMMABLE INTERVAL TIMER ae | . READ BACK COMMAND . j M5M82C54P,-6 has a function of reading not only the count i but also status (Read Back Command). The read back com- q mand enables the next four functions. : (1) read the current count “on the fly” : 4 (2) monitor the current state of the OUT pin, q (3) monitor the current state of the counter element (whether the count is loaded into the counter element or not) (4) read the control word Read back operation can be specified by writing:read back command into the control word registers (Aa, Ar =1,1). Fig. 8 shows the format of read back command. Bits Dy and Dg are used for specifying read back command and fixed 1 (D, =1, Dy =1). Respectively bits Ds (count) and D, (Status) are used for reading the count and the sta- tus of the counter selected by the Dj~D, bits. Bit Dp must . * be fixed 0. ‘Only the count can be read “on the fly” by setting Ds =0 and D, =1 as well as counter latch command above men- tioned. If Ds~D, are set 1 all, the counts of three counters are simultaneously latched by one read back command. (By counter latch command, it must be latched for each counter.) Next, by read operation, the latched count is read put. Only the status can be latched by setting Ds =1 and D, =0. By read operation, the status shown in Fig. 9 can be read. Bit D; gives the ourrent state of OUT pin. When D; =1, OUT =H", and when D; =0, OUT = “L”, Bit Dg indicates the “current state of counter element. When Ds =1, the initial counter value has not been loaded to counter element. This state Is following. . (1) The contro! word is written, but the initial counter value Is not loaded (2) The initial counter value Is written to count register, and the CLK inputs are_not. When Dg =0, the initial counter value has already been loaded. It Is the state when the CLK falls following the rising . ‘edge after the initial value Is written. Bits Ds~ Do show the current state of the contro! word regsiter. It ls possible to read both the count and the status. By set- ting Ds =0 and D, =0, the status can be read first, and the count next. The count and/or the status are unlatched when read, so by * the next read operation the current counting value can be read, And they are unlatched too when the contro! word is set, so the read back command must be set on all such ‘occasions. if multiple read back commands are written before the read : H ‘operation, only the first one is valid. . ! Thus, the read of the status is effective when the state of : ‘output and the timing of count reading can be monitored by | software, i | 6-76 on % MITSUBISHI | . ELECTRIC

MITSUBISHI{MICMPTR/MIPRC} FL DEM be418es GOLA & ; | MITSUBISHI LSIs MSM82CS54P,-6 ae 6249828 MITSUBISHI C(MICMPTR/MIPRO) 91D 11990 DT-51-19 aes ts ee ., . CMOS PROGRAMMABLE INTERVAL TIMER Sa, i Read Back Command q (D7=1, De=1 | fixed) q { @COUNT=0 : Latch Count @STATUS=0 : Latch Status CNT2=1 : Select Counter 2 e {enti =I: Select Counter! CNTO=1 : Select Counter 0 : [7 @Fixed on 0 : Dy De Ds Dy Ds Dy Dr Do Ls [+ Jeount [srarus | onre T onrs ] onto [0] Fig. 8 Read Back Command Format @State of OUT pin our : f 1 Tour pinis"Htever [0] outpinis t= tever_ State of counter element ont . [1 J tniuat value unioaded [oT intatvatwotoadeg gate of contro! word register 4 ‘cf. Table 2) mM Dy Ds Ds. De Ds Dr Dp Do [our [ont [ mur [reo [ me [ mi Two | aco | . Fig. 9 Status Byte . ! —— ee | - , MITSUBISHI ~ | ; wr ERS 67 pp

MITSUBISHI{MICMPTR/MIPRC} 42 DEg}b247a2a OOLLI91 O MITSUBISHI LSIs - SM82C54P,-6 ‘sid 6249828 MITSUBISHI (MICMPTR/MIPRC) 91D 11991 0 TSI-/F Pi ge Bars a : CMOS PROGRAMMABLE INTERVAL TIMER Bea «i ; ABSOLUTE MAXIMUM RATINGS i [-symbot [Parameter conctions TT atings Tt] { [vi [rout vatege | ot respctto ano ] | Topr | Overaiog weo-ortonpertrerenge | ange [torg [stage enperstre range emcee RECOMMENDED OPERATING CONDITIONS (te=-20~75¢., unless cnerwise noted) | wie] nem [won| . | veo | Poverswppivvetage ae Ps [oe Tv | [veo [suse vote (ono) Te Pv ELECTRICAL CHARACTERISTICS (ta=-20~78t , Voo=5v10% , unless otherwise noted) . a ec | von [Hihiovelinpatvotage Po fects] | | va [eowioverinoutvonege 0 os oe P| Ce ee a ES | to Paantevetpateurent | Mawrovevins.sov Tf io [aa | | ta Lewovtnpteument Wawra vinoy io Tea | | tox [orate cuputewnent | vawrovsvirtmveg to Ta Power supply curent ma | to | Power sup curen during sranD BY | asOv arin are Vezeeves ||| | cr | wutcapectance furan tins 2omvine tasaste [to [oe WoW tmimieainvme Tanase | [| 20 | pF | | - i { : { . | . ge . MITSUBISHI , : | 6-78 . : ae SUES

MITSUBISHI{MICMPTR/MIPRC} FL vey 6249828 OOLLA2 1 Tr MITSUBISHI LSIs be 6249628 MITSUBISHI (MICMPTR/MIPRC) 91D 11992 OT-S5/I-19 Baten 20a re . CMOS PROGRAMMABLE INTERVAL TIMER ee OEE | TIMING REQUIREMENTS | (to=—20~750 . Voom 6V210%, Vae™0V, unloss otherwise noted) - | Read cycle : | symibat [min [tye | Mox_| | [tm | Read puise was | tn cs | teucs-n) |€Seeuptimevetvaread | ten re ee ce Address hold time ater read [amr a [trecen _| Read recovery time [zo [ne | Write cyole : symbel [in| we [wo | | twcwr [waite puso wa tw [so [Te rs [of fe I © Lneway [Aadoss aide atorwite | twa | cams = fo Tne [ tauco.w» | Dataset tine before wite | tow | [r2otion (Wotet) | | ns | tnew.or | Datahoid time aterwite | two j of| [ns | [roc [wrterecoveytime ty [200 [| ns I Note 1 : M5M82C54P/P-6 Is also invested with the extended specification showed in the bracket. Clock and gate timing Aternative [tims Test condtion _[ Mawie2cseP [waMezcs4r-6 symbal | win [ sax | tin [ a | [tery | Clooknigh puse wih | tows [eo | fs] [ne | [twcens | Clookiow puse wa tem |o[ [nol | ns | [tory | Ctockeyootime tee a [tec [Ctookrisotime [| 100 || t00 | ne | [tury [euoktnume |, amt §= ft | tc | ne [two | Gatorigh pucoway | tow | [sof | sol | ns | . [sof | so] = | ns | | teuca-) | Gate setup time botowctock | tos [so] [sol [ne | [tnce-ar | Geteoig time aterciook | tow [sof [sof [ns | i . i ! . j i . . MITSUBISHI 6-79 2 he MiTsuBis

MITSUBISHI{MICMPTR/MIPRC} Fh ve 6249826 0021993 3 J mrsusisn Lsis a : MSM82CS54P,-6 er 6249828 MITSUBISHI (MICMPTR/MIPRO) 91D 11993 DT-SI-/9 Peta Resid CMOS PROGRAMMABLE INTERVAL TIMER THe | SWITCHING CHARACTERISTICS (te=-20~751. Veom5:t10%6, Ves=OV, unless ohorwise noted) (Note2) | : : a | trevee-e»| repapsiontme trom eadioautpat | to | [| _|izo] [iz | ns | | trvacric» | Propagstin tie tom read io ouput eating Ntes) | tor | mtetwr «= | | 80 | 5 | a0 | ne | | texvie-an| Prevagstion time tom gate tocupt | tooo | [azo [| iz [ns | [ tn eay [Propagation tine tom clock output | too | [ [iso [iso [ns] * Wolo 2? AG Testing waveform 2a Input pulse level 0, 45~2, 4V ” Input pulse fall time 10ns Reference level input Vin=2V, Vic=0. BV . ‘Output Vou=2V, Vor=0. 8 3 5 Tost conlton isnot applied i . | | MITSUBISHI | 6-80 ae ese

NITSUBISHICMICHPTR/MIPRCY 92 DEBee49828 0011954 S B wirsusisu vsis MSM82C54P,-6 — ‘ 6249528 MITSUBISH ICMICMPTR/MIPRC) 91D 11994 DT-5/-19 Benne 1. TIMING DIAGRAMS (Reterence votage: Hign=20V, Low=08v)

7 Read Cycle

. \\ 7 aD Se Se | exces Erne tein) Write Cycle = . ™ _ [| : [twa thow-0 fo | me To} a = thw oo es (Recovery Time) trocta_trootw _ oF OOH*Ee Clock and Gate Cycle - - twiaw twian) ~ a CoG rd H twcon0 texto) : i Peel fe Sine i | - : texvis-0) . i 9% MITSUBISHI . 6-81 | ELECTRIC