M5M465405BTP-5

M5M467405BTP-5 MITSUBISHI | Alldatasheet

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Technical content

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Standard 32 pin SOJ, 32 pin TSOP Standard 50 pin SOJ, 50 pin TSOP Single 3.3 0.3V supply Low stand-by power dissipation 1.8mW (Max) LVCMOS input level Low operating power dissipation M5M467405Bxx-5,5S / M5M467805Bxx-5,5S 360.0mW (Max) M5M467405Bxx-6,6S / M5M467805Bxx-6,6S 324.0mW (Max) M5M465405Bxx-5,5S / M5M465805Bxx-5,5S 468.0mW (Max) M5M465405Bxx-6,6S / M5M465805Bxx-6,6S 432.0mW (Max) M5M465165Bxx-5,5S 504.0mW (Max) M5M465165Bxx-6,6S 468.0mW (Max) Self refresh capability* Self refresh current 400µA (Max) EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities Early-write mode , OE and W to control output buffer impedance All inputs, outputs LVTTL compatible and low capacitance :Applicable to self refresh version(M5M467405/465405/467805/465805/465165BJ,BTP-5S,-6S:option) only APPLICATION Main memory unit for computers, Microcomputer memory, Refresh memory for CRT

DESCRIPTION

The M5M467405/465405BJ,BTP is organized 16777216-word by 4-bit, M5M467805/465805BJ,BTP is organized 8388608-word by 8-bit, and M5M465165BJ,BTP is organized 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are suitable for large-capacity memory systems with high speed and low power dissipation. The use of double-layer aluminum process combined with CMOS technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. ADDRESS M5M465405Bxx M5M467405Bxx Part No. XX=J,TP

FEATURES

M5M467405BXX-5,5S M5M467805BXX-5,5S M5M467405BXX-6,6S M5M467805BXX-6,6S M5M465405BXX-5,5S M5M465805BXX-5,5S M5M465405BXX-6,6S M5M465805BXX-6,6S access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycle dissipa- (typ.mW) Power tion 104 300 250 390 access time (max.ns) OE 60 15 30 104 32515 Type name access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycleaccess time (max.ns) OE M5M465165BXX-6,6S M5M465165BXX-5,5S 50 104 dissipa- (typ.mW) Power tion 420 390 (M5M467405Bxx/M5M465405Bxx/M5M467805Bxx/M5M465805Bxx) (M5M465165Bxx) M5M465805Bxx M5M467805Bxx M5M465165Bxx A0-A12 Row Add Col Add Refresh Refresh Cycle RAS Only Ref,Normal R/W CBR Ref,Hidden Ref RAS Only Ref,Normal R/W CBR Ref,Hidden Ref A0-A10 A0-A11 A0-A11 8192/64ms 4096/64ms 4096/64ms 8192/128ms 4096/128ms 4096/128ms Normal S-version A0-A12 RAS Only Ref,Normal R/W CBR Ref,Hidden Ref RAS Only Ref,Normal R/W CBR Ref,Hidden Ref A0-A9 A0-A11 A0-A10 8192/64ms 4096/64ms 4096/64ms 8192/128ms 4096/128ms 4096/128ms RAS Only Ref,Normal R/W CBR Ref,Hidden RefA0-A11 A0-A9 4096/64ms 4096/128ms

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6SM5M465405BJ M5M467405BJ Outline 32P0N (400mil SOJ) Vcc DQ 2 W RAS A11 A10 Vcc Vss DQ 4 DQ 3 CAS OE A6A5 Vss NC NC NC NC A12/NC(Note) DQ 1 NC NC NC NC NO CONNECTION M5M465405BTP M5M467405BTP Outline 32P3N (400mil TSOP Normal Bend) Vcc DQ 2 W RAS A11 A10 Vcc Vss DQ 4 DQ 3 CAS OE A6A5 Vss NC NC NC NC A12/NC(Note) DQ 1 NC NC NC PIN CONFIGURATION (TOP VIEW) PIN DESCRIPTION Pin Name A 0-A12 DQ1-DQ4 RAS CAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Power Supply (+3.3V) Ground (0V) Output Enable Input NC No Connection Pin Name A 0-A11 DQ1-DQ16 RAS UCAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Power Supply (+3.3V) Ground (0V) Output Enable Input NC No Connection Upper byte control LCAS Column Address Strobe Input Lower byte control Pin Name A 0-A12 DQ1-DQ8 RAS CAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Power Supply (+3.3V) Ground (0V) Output Enable Input NC No Connection M5M467405Bxx / M5M465405Bxx M5M467805Bxx / M5M465805Bxx M5M465165Bxx XX=BJ,BTP M5M467400/465400BJ,BTP

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S NC NO CONNECTION M5M465805BJ M5M467805BJ Outline 32P0N (400mil SOJ) Vcc DQ 2 W RAS A11 A10 Vcc Vss DQ 8 DQ 7 CAS OE A6A5 Vss A12/NC(Note) DQ 1 NC DQ 4 DQ 3 DQ 6 DQ 5 Vss Vcc M5M465805BTP M5M467805BTP Outline 32P3N (400mil TSOP Normal Bend) Vcc DQ 2 W RAS A11 A10 Vcc Vss CAS OE A6A5 Vss A12/NC(Note) DQ 1 DQ 8 DQ 7 NC DQ 4 DQ 3 DQ 6 DQ 5 Vss Vcc NC : NO CONNECTION Outline 50P0G (400mil SOJ) NC UCAS OE A6A5 NC A11 A10 LCAS DQ 9 DQ 1 DQ 2 DQ 3 DQ 4 Vss DQ 8 DQ 7 DQ 6 DQ 5 DQ 15 DQ 14 DQ 13 DQ 10 DQ 11 DQ 12 DQ 16 NC NC 12Vcc 14 37

39 Vss

W RAS NC NC NC NC NC M5M465165BJ Vcc Vcc Vcc Vss Vss Outline 50P3G (400mil TSOP Normal Bend) NC UCAS OE A6A5 NC A11 A10 LCAS DQ 9 DQ 1 DQ 2 DQ 3 DQ 4 Vss DQ 8 DQ 7 DQ 6 DQ 5 DQ 15 DQ 14 DQ 13 DQ 10 DQ 11 DQ 12 DQ 16 NC NC 12Vcc 14 37 W RAS NC NC NC NC NC M5M465165BTP Vss VssVcc Vcc Vcc PIN CONFIGURATION (TOP VIEW)M5M465165BJ,BTP PIN CONFIGURATION (TOP VIEW)M5M467805/465805BJ,BTP

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S FUNCTION The M5M467405(805)/465405(805,165)BJ, BTP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Operation RAS CAS OE Inputs Input/Output Refresh Remark W Row address address Column Input Output Read Write (Early write) Write (Delayed write) Read-modify-write ACT ACT ACT ACT ACT ACT ACT ACT NAC ACT ACT ACT ACT DNC DNC ACT APD APD APD APD APD APD APD APD OPN VLD OPN IVD VLD EDO mode identical Standby Hidden refresh ACT ACT NAC ACT ACT DNC DNC NAC DNC ACT DNC DNC DNC DNC DNC DNC DNC DNC OPN DNC DNC VLD OPN OPN YES YES NO CAS before RAS refresh NO NO NO NO VLD VLD VLD M5M467405Bxx / M5M465405Bxx / M5M467805Bxx / M5M465805Bxx Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open Operation RAS Inputs UCAS Lower byte read Lower byte write Word write Stand-by Hidden refresh ACT ACT ACT ACT NAC ACT ACT DNC OEW NAC DNC DNC ACT DNC RAS-only refresh CAS before RAS refresh ACT ACT DNC LCAS Upper byte read NAC NAC NAC ACT Word read ACT ACT ACT NAC ACT Upper byte write ACT ACT ACT ACT NAC NAC ACT ACT ACT NACACT NACACT NACACT NAC NAC DNC NAC ACT ACT ACT ACT DNC DNC Input/Output DQ1~DQ8 OPNVLD OPN OPN DQ9~DQ16 VLD VLDVLD DIN DNC DINDNC DIN DIN OPN VLDVLD OPN OPN OPN OPN M5M465165Bxx Row address address Column APD APD APD APD APD APD APD APD DNC DNC DNC DNC DNC DNC DNC APD APD APD APD Refresh Remark YES YES NO EDO mode identical NO NO NO NO NO NO YES RAS-only refresh ACT NAC DNC DNC APD DNC OPN OPN YES APD

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S BLOCK DIAGRAM A10 A11 ADDRESS INPUTS CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER ROW & COLUMN ADDRESS BUFFER MEMORY CELL (67108864 BITS) (4) DATA IN BUFFERS (4) DATA OUT BUFFERS Vcc (3.3V) Vss (0V) DQ1 OE DQ2 DQ3 DQ4 DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT CAS RAS W A0~A11 A0~ A12 (Note) (Note) Note Refer to Page 1 (ADDRESS): A12 (Note) BLOCK DIAGRAM A10 A11 ADDRESS INPUTS CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER ROW & COLUMN ADDRESS BUFFER MEMORY CELL (67108864 BITS) (8) DATA IN BUFFERS (8) DATA OUT BUFFERS Vcc (3.3V) Vss (0V) DQ3 OE DQ4 DQ5 DQ6 DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT CAS RAS W A0~A10 A0~ A12 DQ2 DQ1 DQ7 DQ8 (Note) (Note) Note Refer to Page 1 (ADDRESS): A12 (Note) M5M467405Bxx / M5M465405Bxx M5M467805Bxx / M5M465805Bxx

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S LOWER BYTE CONTROL COLUMN ADDRESS STROBE INPUT UPPER BYTE CONTROL COLUMN ADDRESS STROBE INPUT BLOCK DIAGRAM CLOCK GENERATOR CIRCUIT VCC (3.3V) VSS (0V) ROW ADDRESS STROBE INPUT RAS W A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 ADDRESS INPUTS COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER ROW & COLUMN ADDRESS BUFFER MEMORY CELL (67108864BITS) DQ 1 OE DQ 2 DQ 8 OUTPUT ENABLE INPUT A 0~A 9 A 0 ~ A11 UCAS (8)LOWER DATA IN BUFFERS (8)LOWER DATA OUT BUFFERS (8)UPPER DATA IN BUFFERS (8)UPPER DATA OUT BUFFERS LOWER DATA INPUTS / OUTPUTS DQ 9 DQ 10 DQ 16 LOWER UPPER A 11 A 10 LCAS UPPER DATA INPUTS / OUTPUTS M5M465165Bxx WRITE CONTROL INPUT

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI Pd Topr Tstg Parameter Conditions Ratings Unit V V V mA mW C C -0.5 4.6 -0.5 4.6 -0.5 4.6 1000 0 70 -65 150 With respect to Vss Ta=25 C Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature RECOMMENDED OPERATING CONDITIONS UnitLimits Min Nom Max V V V V 3.6 Vcc+0.3 0.8 3.3 3.0 2.0 -0.3 Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Vcc Symbol Vss VIH VIL (Ta=0 70 , unless otherwise noted) (Note 1)C Note 1 : All voltage values are with respect to Vss. ELECTRICAL CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) (Note 2)C Symbol VOH VOL IOZ I I ICC1 (AV) High-level output voltage Parameter Limits Min Max Unit TypTest conditions Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) M5M467405B-5,5S M5M467805B-5,5S M5M467405B-6,6S M5M467805B-6,6S IOH =-2mA IOL =2mA Q floating 0V ≤ VOUT ≤ Vcc 0V≤VIN ≤ Vcc+0.3V, Other input pins=0V RAS, CAS cycling tRC =tWC =min. output open Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. V V mA Vcc 0.4 100 2.4 -10 -10 [M5M467405B / M5M467805B] ~ ± µA µA RAS= CAS =V IH, output open 1 M5M467405B-5,5S -6,6S RAS= CAS ≥Vcc -0.2V,output open mA 0.5M5M467405B-5,6 M5M467805B-5,6 M5M467405B-5S,6S M5M467805B-5S,6S 0.3 ICC2 (AV) Average supply current from Vcc stand-by ICC4 (AV) (Note 3,4,5) Average supply current from Vcc EDO-Mode M5M467405B-5,5S M5M467805B-5,5S RAS=V IL, CAS cycling tHPC =min. output open mA mA 100 M5M467405B-6,6S M5M467805B-6,6S 90 ICC6 (AV) (Note 3,5) Average supply current from Vcc CAS before RAS refresh mode M5M467405B-5,5S M5M467805B-5,5S 130 M5M467405B-6,6S M5M467805B-6,6S 120 CAS before RAS refresh cycling tRC =min. output open (Note 6) M5M467805B-5,5S -6,6S

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S ELECTRICAL CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) (Note 2)C [M5M465405B / M5M465805B] Symbol VOH VOL IOZ I I ICC1 (AV) High-level output voltage Parameter Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) M5M465405B-5,5S M5M465805B-5,5S M5M465405B-6,6S M5M465805B-6,6S M5M465405B-5,5S -6,6S M5M465405B-5,6 M5M465805B-5,6 M5M465405B-5S,6S M5M465805B-5S,6S ICC2 (AV) Average supply current from Vcc stand-by ICC4 (AV) (Note 3,4,5) Average supply current from Vcc EDO-Mode M5M465405B-5,5S M5M465805B-5,5S M5M465405B-6,6S M5M465805B-6,6S ICC6 (AV) (Note 3,5) Average supply current from Vcc CAS before RAS refresh mode M5M465405B-5,5S M5M465805B-5,5S M5M465405B-6,6S M5M465805B-6,6S (Note 6) M5M465805B-5,5S -6,6S Limits Min Max Unit TypTest conditions IOH =-2mA IOL =2mA Q floating 0V ≤ VOUT ≤ Vcc 0V≤VIN ≤ Vcc+0.3V, Other input pins=0V RAS, CAS cycling tRC =tWC =min. output open V V mA Vcc 0.4 130 2.4 -10 -10 µA µA RAS= CAS =V IH, output open 1 RAS= CAS ≥Vcc -0.2V,output open mA 0.5 0.3 RAS=V IL, CAS cycling tHPC =min. output open mA mA 100 130 120 CAS before RAS refresh cycling tRC =min. output open 120 [M5M465165B] Symbol VOH VOL IOZ I I ICC1 (AV) ICC2 (AV) High-level output voltage Parameter Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) Average supply current from Vcc stand-by M5M465165B-5,5S M5M465165B-6,6S ICC4 (AV) ICC6 (AV) Average supply current from Vcc EDO-Mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh mode (Note 3,5) M5M465165B-5,5S M5M465165B-6,6S M5M465165B-5,5S M5M465165B-6,6S Limits Min Max UnitTypTest conditions IOH =-2mA IOL =2mA RAS= CAS =V IH, output open V V mA mA Vcc 0.4 140 130 0.5 2.4 -10 -10 RAS, CAS cycling output open tRC =tWC =min. Q floating 0V VOUT Vcc≤ ≤ 0V VIN Vcc+0.3V, Other input pins=0V≤ ≤ RAS= CAS Vcc -0.2V, output open≥ mA mA 120 110 140 130 CAS before RAS refresh cycling tRC =min. output open RAS=V IL, CAS cycling output open tHPC =min. µA µA 0.3 M5M465165B-5,5S -6,6S M5M465165B-5,6 M5M465165B-5S,6S(Note 6)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S SWITCHING CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)C ParameterSymbol Limits Unit M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S Access time from CAS Access time from RAS Column address access time tCAC ns ns ns ns ns 50tRAC tAA tCPA tOEA Access time from CAS precharge (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7)Access time from OE 1513 Min Max Min Max 55tCLZ tOEZ (Note 12)Output disable time after OE high 1513 ns ns tWEZ Output disable time after W high tOFF Output disable time after CAS high tREZ Output disable time after RAS high ns ns ns (Note 12) (Note 12,13) (Note 12,13) Output low impedance time from CAS low (Note 7) nstOHC Output hold time from CAS nstOHR Output hold time from RAS (Note 13) 55 ~ ± Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for measuring of output signals are VOH=2.0V and VOL=0.8V. 8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOEZ(max), tWEZ(max) , tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT 10 A) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high. ≥ ≥ ≤ ≤ ≤ ± µ CAPACITANCE (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) C Limits Min Max Unit Typ pF pF pF pF pF pF Input capacitance,address inputsC I (A) C I (OE) C I (RAS) C I (W) C I (CAS) C I / O Symbol Parameter Test conditions Input capacitance, OE input Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports VI=Vss f=1MH Z Vi=25mVrms ~ ±

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles) (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 14,15)C Read and Refresh Cycles ParameterSymbol Limits Unit Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Read cycle time RAS low pulse width CAS low pulse width tRC tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low Read Setup time before CAS low Read hold time after CAS high (Note 22)tRCH tRRH (Note 22) tRAL tORH RAS hold time after CAS low Read hold time after RAS high Column address to RAS hold time RAS hold time after OE low 10000 10000 10000 10000 104 tCAL Column address to CAS hold time 13 18 ns ns ns ns ns ns ns ns Min Max Min Max ns ns ns tOCH 13 15 nsCAS hold time after OE low Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD or tWED must be satisfied. 21: tT is measured between VIH(min) and VIL(max). ≥ ≥ ParameterSymbol Limits UnitM5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S Refresh cycle timetREF 6464 ms Min Max Min Max RAS high pulse width Delay time, RAS low to CAS low tRP tRCD tCRP tRPC tCPN Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width (Note21) (Note16) (Note17) (Note18) tRAD tASR tASC tRAH tCAH tT Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Transition time (Note19) (Note20) (Note19) (Note20) Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data tDZC tDZO tCDD tODD 1513 1513 (Note20)Delay time, RAS high to datatRDD 1513 ns ns ns ns ns ns ns ns ns 128128 msRefresh cycle time (S-version only)tREF ns ns ns ns ns ns ns ns1513(Note20)Delay time, W low to datatWED M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Write Cycle (Early Write and Delayed Write) ParameterSymbol Read-Write and Read-Modify-Write Cycles Limits ParameterSymbol Limits Unit M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S OE hold time after W low Read write/read modify write cycle time RAS low pulse width CAS low pulse width tRWC tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note23) (Note24) 109 tCWD tRWD tAWD Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low (Note24) (Note24) 10000 10000 10000 10000 133 ns ns ns ns ns ns ns ns ns Min Max Min Max ns 1513tOEH Write cycle time RAS low pulse width CAS low pulse width tWC tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 24) tWCH tCWL tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low 10000 10000 10000 10000 104 8 10tDH RAS hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width ns ns ns ns ns ns ns ns Unit Min Max Min Max ns ns ns ns 8 10 8 10 Note 23: tRWC is specified as tRWC(min) =tRAC(max) +tODD(min) +tRWL(min) +tRP(min)+4tT. 24: tWCS , tCWD , tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi- nate. ≥ ≥ ≥ ≥ M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S CAS before RAS Refresh Cycle (Note 28) Note 28: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25) ParameterSymbol Limits Unit ParameterSymbol Limits Unit CAS setup time before RAS lowtCSR tCHR tRSR tRHR CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low ns ns ns ns Min Max Min Max EDO mode read/write cycle time RAS low pulse width for read write cycle CAS high pulse width tHPC tRAS tCP tCPRH tCPWD RAS hold time after CAS precharge (Note26) (Note27) 43Delay time, CAS precharge to W low (Note24) 100000 100000 13 16 tHPRWC EDO Mode read write / read modify write cycle time 55 66 tCHOL Hold time to maintain the data Hi-Z until CAS access 7 7 tOEPE tWPE OE Pulse Width (Hi-Z control) 7 7 W Pulse Width (Hi-Z control) 7 7 ns ns ns ns ns ns ns ns Min Max Min Max ns ns55tDOH Output hold time from CAS low Delay time, CAS low to W low after read 28 32tHCWD Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read tHAWD tHPWD tHCOD tHAOD tHPOD 40 47 43 50 13 15 25 30 28 33 ns ns ns ns ns ns 65 77 Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle. 26: tRAS(min) is specified as two cycles of CAS input are performed. 27: tCP(max) is specified as a reference point only. If tCP tCP(max) , access time is controlled exclusively by tCAC.≥ M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S ELECTRICAL CHARACTERISTICS (Ta=0 70 , Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted) (Note 2) Symbol Parameter Limits ParameterSymbol M5M46X405B-5S M5M46X805B-5S M5M465165B-5S M5M46X405B-6S M5M46X805B-6S M5M465165B-6S Unit Min Max Self Refresh RAS low pulse widthtRASS Min Max µS ns ns tRPS tCHS 100 104 - 50 100 - 50 Self Refresh RAS high precharge time Self Refresh CAS hold time SELF REFRESH SPECIFICATIONS BURST REFRESH < 128 ms > BURST REFRESH < 128 ms > tNS tSN DISTRIBUTED REFRESH < 128 ms > DISTRIBUTED REFRESH < 128 ms > tNS tSN (1) In case of CBR distributed refresh SELF REFRESH ENTRY & EXIT CONDITIONS The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 128 ms and tSN 128 ms. (2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 16 ms and tSN 16 ms. Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics and requirements than the below are same as normal devices. C (Ta=0 70 , Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted See notes 14,15)TIMING REQUIREMENTS Self refresh period Self refresh period ~ ± ~ ± ≤ ≤ ICC8 (AV) Average supply current from Vcc Extended - Refresh cycle (note 5,6) ICC9 (AV) Average supply current from Vcc Self - Refresh cycle (note 6) C Limits Min Max UnitTypTest conditions CAS before RAS refresh cycling tRAS = tRAS(min) 500 µA RAS = CAS 0.2V output = OPEN 400 µA≤ input high level Vcc-0.2V≥ input low level 0.2V≤ output = OPEN , tRC = 31.25µs ~ 300ns M5M46X405B-5S,6S M5M46X805B-5S,6S M5M465165B-5S,6S M5M46X405B-5S,6S M5M46X805B-5S,6S M5M465165B-5S,6S

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Timing Diagrams (Note 29) Read Cycle tRC tRAS tRP tRCD tCSH tRSH tCRP tCAHtRAHtASR tCDDtDZC tCLZ tAA tOFF Hi-Z tRAC tOEA tOEZ tCAC Hi-Z tCAS tRAD tRAL tASR tORH tOCH tODD tDZO tRCS tASC tRCH tRRH ROW ROW ADDRESSADDRESS COLUMN ADDRESS tREZ tCAL tOHR tWEZ tRDD VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCRP Hi-ZDATA VALID tRPC tCPN Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max)Note 29: Indicates the invalid output. Indicates the skew of the two inputs. (at M5M465165Bxx only) ≤ ≤ ≤ ≤ DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) tOHC CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Write Cycle (Early Write) tWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tCRP tWCS tWCH tDHtDS tASR tRAH tASC tCAH Hi-Z tASR ROW ADDRESS DATA VALID COLUMN ADDRESS ROW ADDRESS VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRPC DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Write Cycle (Delayed Write) VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tCRP tASR tRAH tASC tCAH Hi-Z tRCS tCWL tRWL tWP tDZC tDS tWCH tCLZ Hi-Z tDZO tODD tOEZ tOEH tDH tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS Hi-Z DATA VALID tRPC DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Read-Write, Read-Modify-Write Cycle VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tCRP tASR tRAH tASC tCAH Hi-Z tRCS tCWL tRWL tWP tDZC tDS tDZO tODD tOEZ tOEH tCWD tAWD tRWD tAA tOEA tRAC tRAD tASR tDH tCLZ COLUMN ADDRESS ROW ADDRESS DATA VALID tCAC Hi-Z DATA VALID ROW ADDRESS Hi-Z tRPC DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Read Cycle tCRP tASR tRAH tRAD tRCD tRAS tCP tCAC tAA tRAC tASR Hi-Z ADDRESS ROW ADDRESS tCAS ROW tRCS Hi-Z tDZC tDZO tOEA tOCH DATA VALID-1 tCSH tHPC tCAS tCP tCAS tRSH tCAHtASC tCAHtASC tCPRH tRCH tRRH tCDD tCPA tODD tREZ tOFF tCLZ tDOH tRDD tCAC tAA tCPA tDOH tCAC DATA VALID-3 tAA tCAL tCAL tCAL tOHC tOHR tWEZ VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCAHtASC COLUMN ADDRESS-3 COLUMN ADDRESS-2 COLUMN ADDRESS-1 DATA VALID-2 tCRP tRPC tRP tOEZ tRAL DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Write Cycle (Early Write) tCRP tASR tRAH tRCD tCAH tRAS tCP tASR ADDRESS ROW ADDRESS tRP tCAS ROW tASC tWCS tCSH tHPC tCAS tCP tCAS tRSH tCAH tCAHtASC tASC Hi-Z tWCH tWCS tWCH tWCS tWCH DATA VALID-1 DATA VALID-2 DATA VALID-3 tDS tDH tDS tDH tDS tDH tCAL tCAL tCRP VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL COLUMN ADDRESS-1 COLUMN ADDRESS-2 COLUMN ADDRESS-3 tRPC tCAL DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Read-Write, Read-Modify-Write Cycle tDZO tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tHPRWC tCAS tRWL ROW ADDRESS tCAHtASC tRCS tRWD tDZC tDS tCWL tWPtRCStWP tCWL Hi-Z Hi-Z tDH tDS tDZC tCPWD DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tDZO tOEZ tODD tOEZ tOEH tRAD tCWD tAWD tAWD tCWD tAA tCAC DATA VALID tAA tCAC DATA VALID tCLZ tRAC tOEA tCPA tOEA tODD DATA VALID-1 tCRP VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL COLUMN ADDRESS-1 COLUMN ADDRESS-2 ROW ADDRESS tRPC tOEH DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Mix Cycle (1) (Note 30) DATA VALID-2 tDZO tWCH tDH tCRP tASR tRAH tRAD tCAH tRAS tCP tCAC tAA tRAC Hi-Z ROW ADDRESS tRP tCAS tASC tRCS tDZC tDZO tOEA tOCH DATA VALID tCSH tHPC tCAS tCP tCAS tCAHtASC tCAHtASC tHPRWC tCPWD tWP tWCS tDS tCLZ tCPA DATA VALID tAA tCAL tCAL tCWD tOEZ tODD tWEZ tOEHtOEZ tCLZ tOEA tASR tCRP tCAC tODD tDH tDS tRWL tCWL tDZC tAWD VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL COLUMN ADDRESS-2 COLUMN ADDRESS-3 COLUMN ADDRESS-1 ROW ADDRESS DATA VALID-3 tRPC Note 30: OE=L; W Hi-Z control OE=H; OE Hi-Z control tWED tRCD DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Mix Cycle (2) (Note 30) tCPA DATA VALID-1 tCAHtASC tHPC DATA VALID-3 tAA tCAC tOEZ tDS tODD DATA VALID-2 Hi-Z tDH tDZC Hi-Z tCAHtASC tCAHtASC tAA tWCH tCAC tOEA tCLZ Hi-Z tCPA tCAL tCP tCAS tRCH tWCS tWEZ tCAL tDZC tCAS tHCOD tHAOD tHPOD tHCWD tHAWD tHPWD VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL COLUMN ADDRESS-1 COLUMN ADDRESS-2 COLUMN ADDRESS-3 tWED Note 30: OE=L; W Hi-Z control OE=H; OE Hi-Z control DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Read Cycle (Hi-Z control by OE) tCRP tASR tRAH tRAD tRCD tCAH tRAS tCP tCAC tAA tRAC tASR Hi-Z tRP tCAS tASC tRCS Hi-Z tDZC tDZO tOEA DATA VALID-1 tCSH tHPC tCAS tCP tCAS tRSH tCAHtASC tCAHtASC tCPRH tRAL tRCH tRRH tCDD tCPA tOEZ tODD tREZ tOFF tCLZ tDOH tRDD tCAC tAA DATA VALID-2 tCPA tOEZ tCAC DATA VALID-3 tAA tCLZ Hi-Z tOEPE tCHOL tOEPE tOEZ tOEA tOCH DATA VALID tOHR tOHC tCRP tWEZ VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL COLUMN ADDRESS-1 ROW ADDRESS COLUMN ADDRESS-2 COLUMN ADDRESS-3 ROW ADDRESS tRPC DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Read Cycle (Hi-Z control by W) tCRP tASR tRAH tRAD tCAH tRAS tCP tCAC tAA tRAC tASR Hi-Z ROW ADDRESS tRP tASC tRCS Hi-Z tDZC tDZO tOEA tOCH DATA VALID-1 tCSH tHPC tCAS tCP tCAS tRSH tCAHtASC tCAHtASC tCPRH tRAL tRCH tCDD tCPA tOEZ tODD tREZ tOFFtCLZ tDOH tRDD tCAC tAA DATA VALID-2 tCPA tWEZ tAA tCAC DATA VALID-3 tWPE tRCH tRCS tCLZ Hi-Z tOHR tOHC tRRH tCRP VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCAStRCD ADDRESS COLUMN ADDRESS-1 ROW COLUMN ADDRESS-2 COLUMN ADDRESS-3 tWEZ tRPC DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S RAS-only Refresh Cycle tCRP tASR tRAH tRAS tRC tASR tCRP tRPC tRP ROW ADDRESS Hi-Z ROW ADDRESS VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S CAS before RAS Refresh Cycle tRAS tRC tASR tCRP tRPC tRP ROW COLUMN ADDRESSADDRESS tRC tRAS tCSR tCHR tCSRtRPC tCPN tRCH tRCS Hi-Z tOEZ tRP tCHR tREZ tRPC tRRH tOFF tOHR tOHC VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCDD tRSR tRHR tRHRtRSR tODD DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Hidden Refresh Cycle (Read) (Note 31) Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. tCRP tASR tRAH tRAD tRCD tCAH tRCS tRAS tRC tCHR tCAC tAA tCLZ tRAC tASR tRP Hi-Z COLUMN ROW ADDRESS DATA VALID tRAS tRC tRP tRSH tASC ADDRESS tRAL Hi-Z tDZC Hi-Z tDZO tOEA tORH tODD tOEZ tREZ tCDD tRDD tOHR tOHC tOFF VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS tCRP tRPC tRRH tRSR tRHR DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165xx only)B

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Self Refresh Cycle tASR tCRP tRPC tRPS ROW ADDRESS tRASS tCSR tCPN tRCH Hi-Z tOEZ tRP tREZ tRPC tRRH tOFF tOHR tOHC VIH VIL VOH VOL RAS W OE Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCDD tCHS tRSR tRHR DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Upper / (Lower) Byte Read Cycle ROW ROW ADDRESSADDRESS COLUMN ADDRESS tCAC DATA VALID tRC tRAS tRP tRCD tCSH tRSH tCRP tCAHtRAHtASR tCDD tCLZ tAA tOFF Hi-Z tRAC tOEA tCAS tRAD tRAL tASR tORH tOCH tODD tDZO tASC tRCH tRRH tREZ tCAL tOHR tWEZ tRDD tCRP RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL Hi-Z Hi-Z Hi-Z tDZC tRCS tOEZ tRPC tRPC tCPN DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ tOHC (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Upper / (Lower) Byte Write Cycle (Early Write) RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tWCS tWCH tASR tRAH tASC tCAH tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS Hi-Z Hi-Z tDHtDS DATA VALID tCRPtRPC tCRPtRPC DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Upper / (Lower) Byte Write Cycle (Delayed Write) RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tOEZ Hi-Z tWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tASR tRAH tASC tCAH tRCS tCWL tRWL tWP tWCH tDZO tODD tOEH tASR COLUMN ADDRESS ROW ADDRESS ROW ADDRESS Hi-Z tDZC tDS tDH tCLZ Hi-Z DATA VALID Hi-Z tCRPtRPC tCRPtRPC DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Upper / (Lower) Byte Read-Write, Upper / (Lower) Byte Read-Modify-Write Cycle. DATA VALID RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL Hi-Z tDZO tOEZ tOEH tASR tRAH tASC tCAH tASR tRWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tRCS tCWL tRWL tWP tODD tCWD tAWD tRWD COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tDZC tDS tDH tCLZ tCAC tOEA Hi-ZHi-Z Hi-Z DATA VALID tRAD tAA tRAC tCRPtRPC tCRPtRPC DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Byte Read Cycle tASR tRAH tRAD tCAH tASR ROW ADDRESS tASC tRCS tCAHtASC tCAHtASC tCPRH tRCH tRRH tCRP tRCD tRAS tCP tRP tCAS tCSH tHPC tCP tCAS tRSH tCAL tCAL tCAL tCAC tAA tRAC Hi-Z Hi-Z tDZC tDZO tOEA tOCH DATA VALID-1 tODD tREZ tOFF tCLZ tRDD tCPA tDOH tCAC DATA VALID-3 tAA tOHC tOHR tDZC Hi-Z tCAC tAA tCPA DATA VALID-2 tCLZ Hi-Z tCDD tOEZ tWEZ RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tCAS ADDRESS COLUMN ADDRESS-1 ROW COLUMN ADDRESS-2 COLUMN ADDRESS-3 tCRPtRPC tCRPtRPC DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ tRAL (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Byte Write Cycle (Early Write) tASR tRAH tCAH tASR ADDRESS ROW ADDRESS ROW tASC tCAH tCAHtASC tASC Hi-Z tCRP tRAS tRP tCSH tHPC tRSH tCAL tCAL tRCD tCPtCAS tCAS tCP tCAS RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL DATA VALID-2 tDS tDH VIH VIL tDS DATA VALID-1 DATA VALID-3 tDH tDS tDH VIH VIL COLUMN ADDRESS-2 Hi-Z tCRPtRPC tCRP tRPC DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ tWCS tWCH tWCS tWCS tWCH VIH VIL tWCH tCAL (at M5M465165Bxx only) COLUMN ADDRESS-1 COLUMN ADDRESS-3

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S EDO Mode Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle tASR tRAH tCAH tASRtASC tCWL ROW ADDRESS tCAHtASC tRCS tRWD tCRP tRAS tCP tRP tCSH tRWL tWP tRCS tWP tCWL tCPWD tRAD tCWD tAWD tAWD tCWD Hi-Z tDZC tDS Hi-Z Hi-Z tDH tDS tDZC DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tDZO tOEZ tODD tOEZ tOEH tAA tCAC DATA VALID tAA tCAC DATA VALID tCLZ tRAC tOEA tDZO tCPA tOEA tODD DATA VALID-1 tRCD tCAS tHPRWC tCAS Hi-Z RAS W VOH VOL OE LCAS (or UCAS) UCAS (or LCAS) VIH VIL Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL COLUMN ADDRESS-1 COLUMN ADDRESS-2 ROW ADDRESS tCRP tRPC tRPC tCRP DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ tOEH (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Upper / (Lower) CAS before RAS Refresh Cycle RAS OE tRP tRC tRAS tRAS tRP tRC tASR ROW ADDRESS tODD tRCH UCAS (or LCAS) LCAS (or UCAS) Address tOEZ Hi-Z tOFF tOEZ Hi-Z tCDD VOH VOL VIH VIL tCPN tRPC tCSR tCHR tRPC tCRP tCSR tCHR tRPC VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL W tRPCtRPC tCRPtCRPtCRPtRPC VIH VIL tREZ tOFF tOHR tOHC tRSR tRHR tRSR tRHR tRCS Å Å Å Å DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Upper / (Lower) Hidden Refresh Cycle (Byte Read) (Note 31) RAS W OE tRC tRAS tRP tASR tRAH tASC tCAH tRCS tRAL tRRH tRAD tRAS tRP tRC tASR tRPC COLUMN ADDRESS ROW ADDRESS UCAS (or LCAS) LCAS (or UCAS) Address tCDD tAA tCLZ tCAC tRAC tOEA tOEZ tODD Hi-Z Hi-Z DATA VALID tORH tDZO Hi-Z tDZC ROW ADDRESS VOH VOL VIH VIL tRPC tCRP tRCD tCHR tRSH tCRP VIH VIL tCRP tCRP VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tOHR tOHC tOFFtREZ tOFF DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Å Å Å Å tRSR tRHR (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Byte Self Refresh Cycle OE tASR ROW ADDRESS tODD tRCH UCAS (or LCAS) Address tOEZ Hi-Z tOFF tOEZ Hi-Z tCDD VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL W tRPC tCRPtCRPtRPC VIH VIL tREZ tOFF tOHR tOHC tRPStRASStRP VIH VIL RAS tCRP tRPC tCSR tCPN tRPC VIH VIL tCHS LCAS (or UCAS) DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Å Å Å Å tRSR tRHR (at M5M465165Bxx only)

Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S Keep safety first in your circuit designs!

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