M5M465160DTP-5

M5M467400DTP-5 MITSUBISHI | Alldatasheet

Document overview

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Technical content

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) Standard 32 pin SOJ, 32 pin TSOP Standard 50 pin SOJ, 50 pin TSOP Single 3.3 0.3V supply Low stand-by power dissipation 1.8mW (Max) LVCMOS input level Low operating power dissipation M5M467400Dxx-5,5S / M5M467800Dxx-5,5S 360.0mW (Max) M5M467400Dxx-6,6S / M5M467800Dxx-6,6S 324.0mW (Max) M5M465400Dxx-5,5S / M5M465800Dxx-5,5S 468.0mW (Max) M5M465400Dxx-6,6S / M5M465800Dxx-6,6S 432.0mW (Max) M5M465160Dxx-5,5S 504.0mW (Max) M5M465160Dxx-6,6S 468.0mW (Max) Self refresh capability* Self refresh current 400µA (Max) Fast-page mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities Early-write mode and OE to control output buffer impedance All inputs, outputs LVTTL compatible and low capacitance :Applicable to self refresh version(M5M467400/465400/467800/465800/465160DJ,DTP-5S,-6S:option) only APPLICATION Main memory unit for computers, Microcomputer memory, Refresh memory for CRT ADDRESS M5M465400Dxx M5M467400Dxx Part No. XX=J,TP

FEATURES

M5M467400DXX-5,5S M5M467800DXX-5,5S M5M467400DXX-6,6S M5M467800DXX-6,6S M5M465400DXX-5,5S M5M465800DXX-5,5S M5M465400DXX-6,6S M5M465800DXX-6,6S access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycle dissipa- (typ.mW) Power tion 110 300 250 390 access time (max.ns) OE 60 15 30 110 32515 Type name access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycleaccess time (max.ns) OE M5M465160DXX-6,6S M5M465160DXX-5,5S 50 110 dissipa- (typ.mW) Power tion 420 390 (M5M467400Dxx/M5M465400Dxx/M5M467800Dxx/M5M465800Dxx) (M5M465160Dxx) M5M465800Dxx M5M467800Dxx M5M465160Dxx A0-A12 Row Add. Col. Add. Refresh Refresh Cycle RAS Only Ref,Normal R/W CBR Ref,Hidden Ref RAS Only Ref,Normal R/W CBR Ref,Hidden Ref A0-A10 A0-A11 A0-A11 8192/64ms 4096/64ms 4096/64ms 8192/128ms 4096/128ms 4096/128ms Normal S-version A0-A12 RAS Only Ref,Normal R/W CBR Ref,Hidden Ref RAS Only Ref,Normal R/W CBR Ref,Hidden Ref A0-A9 A0-A11 A0-A10 8192/64ms 4096/64ms 4096/64ms 8192/128ms 4096/128ms 4096/128ms RAS Only Ref,Normal R/W CBR Ref,Hidden RefA0-A11 A0-A9 4096/64ms 4096/128ms

DESCRIPTION

The M5M467400/465400DJ,DTP is a 16777216-word by 4-bit, M5M467800/465800DJ,DTP is a 8388608-word by 8-bit, and M5M465160DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are suitable for large-capacity memory systems with high speed and low power dissipation. PRELIMINARY Some of contents are subject to change without notice.

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) M5M465400DJ M5M467400DJ Outline 32P0N (400mil SOJ) Vcc DQ 2 W RAS A11 A10 Vcc Vss DQ 4 DQ 3 CAS OE A6A5 Vss NC NC NC NC A12/NC(Note) DQ 1 NC NC NC NC NO CONNECTION M5M465400DTP M5M467400DTP Outline 32P3N (400mil TSOP Normal Bend) Vcc DQ 2 W RAS A11 A10 Vcc Vss DQ 4 DQ 3 CAS OE A6A5 Vss NC NC NC NC A12/NC(Note) DQ 1 NC NC NC PIN CONFIGURATION (TOP VIEW) PIN DESCRIPTION Pin Name A 0-A12 DQ1-DQ4 RAS CAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Power Supply (+3.3V) Ground (0V) Output Enable Input NC No Connection Pin Name A 0-A11 DQ1-DQ16 RAS UCAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Power Supply (+3.3V) Ground (0V) Output Enable Input NC No Connection Upper byte control LCAS Column Address Strobe Input Lower byte control Pin Name A 0-A12 DQ1-DQ8 RAS CAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Power Supply (+3.3V) Ground (0V) Output Enable Input NC No Connection M5M467400Dxx / M5M465400Dxx M5M467800Dxx / M5M465800Dxx M5M465160Dxx XX=J, TP M5M467400/465400DJ, DTP

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) NC NO CONNECTION M5M465800DJ M5M467800DJ Outline 32P0N (400mil SOJ) Vcc DQ 2 W RAS A11 A10 Vcc Vss DQ 8 DQ 7 CAS OE A6A5 Vss A12/NC(Note) DQ 1 NC DQ 4 DQ 3 DQ 6 DQ 5 Vss Vcc M5M465800DTP M5M467800DTP Outline 32P3N (400mil TSOP Normal Bend) Vcc DQ 2 W RAS A11 A10 Vcc Vss CAS OE A6A5 Vss A12/NC(Note) DQ 1 DQ 8 DQ 7 NC DQ 4 DQ 3 DQ 6 DQ 5 Vss Vcc NC : NO CONNECTION Outline 50P0G (400mil SOJ) NC UCAS OE A6A5 NC A11 A10 LCAS DQ 9 DQ 1 DQ 2 DQ 3 DQ 4 Vss DQ 8 DQ 7 DQ 6 DQ 5 DQ 15 DQ 14 DQ 13 DQ 10 DQ 11 DQ 12 DQ 16 NC NC 12Vcc 14 37

39 Vss

W RAS NC NC NC NC NC M5M465160DJ Vcc Vcc Vcc Vss Vss Outline 50P3G (400mil TSOP Normal Bend) NC UCAS OE A6A5 NC A11 A10 LCAS DQ 9 DQ 1 DQ 2 DQ 3 DQ 4 Vss DQ 8 DQ 7 DQ 6 DQ 5 DQ 15 DQ 14 DQ 13 DQ 10 DQ 11 DQ 12 DQ 16 NC NC 12Vcc 14 37 W RAS NC NC NC NC NC M5M465160DTP Vss VssVcc Vcc Vcc PIN CONFIGURATION (TOP VIEW)M5M465160DJ, DTP PIN CONFIGURATION (TOP VIEW)M5M467800/465800DJ, DTP

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) FUNCTION The M5M467400(800)/465400(800,160)DJ, DTP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, CAS before RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Operation RAS CAS OE Inputs Input/Output Refresh Remark W Row address address Column Input Output Read Write (Early write) Write (Delayed write) Read-modify-write ACT ACT ACT ACT ACT ACT ACT ACT NAC ACT ACT ACT ACT DNC DNC ACT APD APD APD APD APD APD APD APD OPN VLD OPN IVD VLD FAST PAGE mode identical Standby Hidden refresh ACT ACT NAC ACT ACT DNC NAC DNC ACT DNC DNC DNC DNC DNC DNC DNC DNC OPN DNC DNC VLD OPN OPN YES YES NO CAS before RAS refresh NO NO NO NO VLD VLD VLD M5M467400Dxx / M5M465400Dxx / M5M467800Dxx / M5M465800Dxx Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open Operation RAS Inputs UCAS Lower byte read Lower byte write Word write Stand-by Hidden refresh ACT ACT ACT ACT NAC ACT ACT DNC OEW NAC DNC DNC ACT DNC RAS-only refresh CAS before RAS refresh ACT ACT DNC LCAS Upper byte read NAC NAC NAC ACT Word read ACT ACT ACT NAC ACT Upper byte write ACT ACT ACT ACT NAC NAC ACT ACT ACT NACACT NACACT NACACT NAC NAC DNC NAC ACT ACT ACT ACT DNC DNC Input/Output DQ1~DQ8 OPNVLD OPN OPN DQ9~DQ16 VLD VLDVLD DIN DNC DINDNC DIN DIN OPN VLDVLD OPN OPN OPN OPN M5M465160Dxx Row address address Column APD APD APD APD APD APD APD APD DNC DNC DNC DNC DNC DNC DNC APD APD APD APD Refresh Remark YES YES NO FAST PAGE mode identical NO NO NO NO NO NO YES RAS-only refresh ACT NAC DNC DNC APD DNC OPN OPN YES APD NAC

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) BLOCK DIAGRAM A10 A11 ADDRESS INPUTS CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER ROW & COLUMN ADDRESS BUFFER MEMORY CELL (67108864 BITS) (4) DATA IN BUFFERS (4) DATA OUT BUFFERS Vcc (3.3V) Vss (0V) DQ1 OE DQ2 DQ3 DQ4 DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT CAS RAS W A0~A11 A0~ A12 (Note) (Note) Note Refer to Page 1 (ADDRESS): A12 (Note) BLOCK DIAGRAM A10 A11 ADDRESS INPUTS CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER ROW & COLUMN ADDRESS BUFFER MEMORY CELL (67108864 BITS) (8) DATA IN BUFFERS (8) DATA OUT BUFFERS Vcc (3.3V) Vss (0V) DQ3 OE DQ4 DQ5 DQ6 DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT CAS RAS W A0~A10 A0~ A12 DQ2 DQ1 DQ7 DQ8 (Note) (Note) Note Refer to Page 1 (ADDRESS): A12 (Note) M5M467400Dxx / M5M465400Dxx M5M467800Dxx / M5M465800Dxx

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) LOWER BYTE CONTROL COLUMN ADDRESS STROBE INPUT UPPER BYTE CONTROL COLUMN ADDRESS STROBE INPUT BLOCK DIAGRAM CLOCK GENERATOR CIRCUIT VCC (3.3V) VSS (0V) ROW ADDRESS STROBE INPUT RAS W A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 ADDRESS INPUTS COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER ROW & COLUMN ADDRESS BUFFER MEMORY CELL (67108864BITS) DQ 1 OE DQ 2 DQ 8 OUTPUT ENABLE INPUT A 0~A 9 A 0 ~ A11 UCAS (8)LOWER DATA IN BUFFERS (8)LOWER DATA OUT BUFFERS (8)UPPER DATA IN BUFFERS (8)UPPER DATA OUT BUFFERS LOWER DATA INPUTS / OUTPUTS DQ 9 DQ 10 DQ 16 LOWER UPPER A 11 A 10 LCAS UPPER DATA INPUTS / OUTPUTS M5M465160Dxx WRITE CONTROL INPUT

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI Pd Topr Tstg Parameter Conditions Ratings Unit V V V mA mW C C -0.5 4.6 -0.5 4.6 -0.5 4.6 1000 0 70 -65 150 With respect to Vss Ta=25 C Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature RECOMMENDED OPERATING CONDITIONS UnitLimits Min Nom Max V V V V 3.6 Vcc+0.3 0.8 3.3 3.0 2.0 -0.3 Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Vcc Symbol Vss VIH VIL (Ta=0 70 , unless otherwise noted) (Note 1)C Note 1 : All voltage values are with respect to Vss. ELECTRICAL CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) (Note 2)C Symbol VOH VOL IOZ I I ICC1 (AV) High-level output voltage Parameter Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) M5M467400D-5,5S M5M467800D-5,5S M5M467400D-6,6S M5M467800D-6,6S Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. [M5M467400D / M5M467800D] ~ ± M5M467400D-5,5S -6,6S M5M467400D-5,6 M5M467800D-5,6 M5M467400D-5S,6S M5M467800D-5S,6S ICC2 (AV) Average supply current from Vcc stand-by ICC4 (AV) (Note 3,4,5) Average supply current from Vcc Fast-Page-Mode M5M467400D-5,5S M5M467800D-5,5S M5M467400D-6,6S M5M467800D-6,6S ICC6 (AV) (Note 3,5) Average supply current from Vcc CAS before RAS refresh mode M5M467400D-5,5S M5M467800D-5,5S M5M467400D-6,6S M5M467800D-6,6S Limits Min Max Unit TypTest conditions IOH =-2mA IOL =2mA Q floating 0V ≤ VOUT ≤ Vcc 0V≤VIN ≤ Vcc+0.3V, Other input pins=0V RAS, CAS cycling tRC =tWC =min. output open V V mA Vcc 0.4 100 2.4 -10 -10 µA µA RAS= CAS =V IH, output open 1 RAS= CAS ≥Vcc -0.2V,output open mA 0.5 0.3 RAS=V IL, CAS cycling tPC =min. output open mA mA 100 130 120 CAS before RAS refresh cycling tRC =min. output open (Note 6) M5M467800D-5,5S -6,6S

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) ELECTRICAL CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) (Note 2)C [M5M465400D / M5M465800D] ~ ± Symbol VOH VOL IOZ I I ICC1 (AV) High-level output voltage Parameter Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) M5M465400D-5,5S M5M465800D-5,5S M5M465400D-6,6S M5M465800D-6,6S M5M465400D-5,5S -6,6S M5M465400D-5,6 M5M465800D-5,6 M5M465400D-5S,6S M5M465800D-5S,6S ICC2 (AV) Average supply current from Vcc stand-by ICC4 (AV) (Note 3,4,5) Average supply current from Vcc Fast-Page-Mode M5M465400D-5,5S M5M465800D-5,5S M5M465400D-6,6S M5M465800D-6,6S ICC6 (AV) (Note 3,5) Average supply current from Vcc CAS before RAS refresh mode M5M465400D-5,5S M5M465800D-5,5S M5M465400D-6,6S M5M465800D-6,6S (Note 6) M5M465800D-5,5S -6,6S Limits Min Max Unit TypTest conditions IOH =-2mA IOL =2mA Q floating 0V ≤ VOUT ≤ Vcc 0V≤VIN ≤ Vcc+0.3V, Other input pins=0V RAS, CAS cycling tRC =tWC =min. output open V V mA Vcc 0.4 130 2.4 -10 -10 µA µA RAS= CAS =V IH, output open 1 RAS= CAS ≥Vcc -0.2V,output open mA 0.5 0.3 RAS=V IL, CAS cycling tPC =min. output open mA mA 100 130 120 CAS before RAS refresh cycling tRC =min. output open 120 [M5M465160D] Symbol VOH VOL IOZ I I ICC1 (AV) ICC2 (AV) High-level output voltage Parameter Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) Average supply current from Vcc stand-by M5M465160D-5,5S M5M465160D-6,6S ICC4 (AV) ICC6 (AV) Average supply current from Vcc Fast-Page-Mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh mode (Note 3,5) M5M465160D-5,5S M5M465160D-6,6S M5M465160D-5,5S M5M465160D-6,6S Limits Min Max UnitTypTest conditions IOH =-2mA IOL =2mA Q floating 0V VOUT Vcc 0V VIN Vcc+0.3V, Other input pins=0V RAS, CAS cycling RAS= CAS =V IH, output open RAS= CAS Vcc -0.2V, output open V V mA mA Vcc 0.4 140 130 0.5 2.4 -10 -10 output open tRC =tWC =min. ≤ ≤ ≤ ≤ RAS=V IL, CAS cycling CAS before RAS refresh cycling tRC =min. output open mA mA 105 140 130 output open tPC =min. µA µA 0.3 M5M465160D-5,5S -6,6S M5M465160D-5,6 M5M465160D-5S,6S(Note 6)

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) SWITCHING CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)C ParameterSymbol Limits Unit M5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S Access time from CAS Access time from RAS Column address access time tCAC ns ns ns ns ns 50tRAC tAA tCPA tOEA Access time from CAS precharge (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7)Access time from OE 1513 Min Max Min Max tOEZ (Note 12)Output disable time after OE high 1513 ns tOFF 13 15 ns(Note 12)Output disable time after CAS high 55tCLZ nsOutput low impedance time from CAS low (Note 7) ~ ± Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for measuring of output signals are VOH=2.0V and VOL=0.8V. 8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT 10 A) and is not reference to VOH(min) or VOL(max). ≥ ≥ ≤ ≤ ≤ ± µ C Limits Min Max Unit Typ pF pF pF pF pF pF Input capacitance,address inputsC I (A) C I (OE) C I (RAS) C I (W) C I (CAS) C I / O Symbol Parameter Test conditions Input capacitance, OE input Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports VI=Vss f=1MH Z Vi=25mVrms CAPACITANCE (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) ~ ±

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles) (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 13,14)C Read and Refresh Cycles ParameterSymbol Limits Unit Note 21: Either tRCH or tRRH must be satisfied for a read cycle. Read cycle time RAS low pulse width CAS low pulse width tRC tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low Read Setup time before CAS low Read hold time after CAS high (Note 21)tRCH tRRH (Note 21) tRAL tORH RAS hold time after CAS low Read hold time after RAS high Column address to RAS hold time RAS hold time after OE low 10000 10000 10000 10000 110 ns ns ns ns ns ns ns ns Min Max Min Max ns ns tOCH 13 15 nsCAS hold time after OE low ParameterSymbol Limits UnitM5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S Refresh cycle timetREF 6464 ms Min Max Min Max RAS high pulse width Delay time, RAS low to CAS low tRP tRCD tCRP tRPC tCPN Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width (Note15) (Note16) (Note17) tRAD tASR tASC tRAH tCAH Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low (Note18) (Note18) Delay time, data to CAS low Delay time, data to OE low tDZC tDZO ns ns ns ns ns ns ns ns ns 128128 msRefresh cycle time (S-version only)tREF ns ns ns (Note19) (Note19)Delay time, CAS high to data Delay time, OE high to data tCDD tODD 1513 1513 ns ns (Note20) 501501tT Transition time ns Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 2.0V and 0.8V respectively. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tT+tASC(min). 16: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max). VIH(min) and VIL(max) of the switching characteristics are ≥ ≥ M5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) Write Cycle (Early Write and Delayed Write) ParameterSymbol Read-Write and Read-Modify-Write Cycles Limits ParameterSymbol Limits Unit Read write/read modify write cycle time RAS low pulse width CAS low pulse width tRWC tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note22) (Note23) 126 tCWD tRWD tAWD Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low (Note23) (Note23) 10000 10000 10000 10000 150 ns ns ns ns ns ns ns ns Min Max Min Max ns OE hold time after W low ns1513tOEH Write cycle time RAS low pulse width CAS low pulse width tWC tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 23) tWCH tCWL tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low 10000 10000 10000 10000 110 8 10tDH RAS hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width ns ns ns ns ns ns ns ns Unit Min Max Min Max ns ns ns ns 13 15 13 15 Note 22: tRWC is specified as tRWC(min) =tRAC(max) +tODD(min) +tRWL(min) +tRP(min)+4tT. 23: tWCS , tCWD , tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi- nate. ≥ ≥ ≥ ≥ 13 15tOEH OE hold time after W low ns tCWL tRWL tWP tDS 8 10tDH Write pulse width Data hold time after CAS low or W low CAS hold time after W low RAS hold time after W low 13 15 13 15 Data setup time before CAS low or W low ns ns ns ns ns M5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S M5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) (Note 24) ParameterSymbol Limits Unit tCPRH tCPWD RAS hold time after CAS precharge Delay time, CAS precharge to W low (Note23) tCP 8(Note26)CAS high pulse width 10 12 15 ns ns ns ns ns Min Max Min Max nstRAS (Note25)RAS low pulse width for read write cycle 125000 12500085 100 Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only. If tCP tCP(max) , access time is controlled exclusively by tCAC.≥ CAS before RAS Refresh Cycle (Note 27) Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. ParameterSymbol Limits Unit CAS setup time before RAS lowtCSR tCHR tRSR tRHR CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low ns ns ns ns Min Max Min Max tPC Fast page mode read/write cycle time tPRWC Fast page mode read write/read modify write cycle time 35 40 70 75 M5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S M5M46X400D-5,5S M5M46X800D-5,5S M5M465160D-5,5S M5M46X400D-6,6S M5M46X800D-6,6S M5M465160D-6,6S

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 MITSUBISHI LSIs(Rev. 1.0) ELECTRICAL CHARACTERISTICS (Ta=0 70 , Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted) (Note 2)C Symbol Parameter Limits Min Max UnitTypTest conditions Limits ParameterSymbol M5M46X400D-5S M5M46X800D-5S M5M465160D-5S M5M46X400D-6S M5M46X800D-6S M5M465160D-6S Unit Min Max Self Refresh RAS low pulse widthtRASS Min Max µS ns ns tRPS tCHS 100 110 - 50 100 - 50 Self Refresh RAS high precharge time Self Refresh CAS hold time SELF REFRESH SPECIFICATIONS BURST REFRESH < 128 ms > BURST REFRESH < 128 ms > tNS tSN DISTRIBUTED REFRESH < 128 ms > DISTRIBUTED REFRESH < 128 ms > tNS tSN (1) In case of CBR distributed refresh SELF REFRESH ENTRY & EXIT CONDITIONS The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 128 ms and tSN 128 ms. (2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 16 ms and tSN 16 ms. Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics and requirements than the below are same as normal devices. C (Ta=0 70 , Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted See notes 13,14)TIMING REQUIREMENTS Self refresh period Self refresh period ~ ± ~ ± ≤ ≤ ICC8 (AV) Average supply current from Vcc Extended - Refresh cycle (note 5,6) CAS before RAS refresh cycling tRAS = tRAS(min) 500 µA ICC9 (AV) Average supply current from Vcc Self - Refresh cycle (note 6) RAS = CAS 0.2V output = OPEN 400 µA≤ input high level Vcc-0.2V≥ input low level 0.2V≤ output = OPEN , tRC = 31.25µs ~ 300ns M5M46X400D-5S,6S M5M46X800D-5S,6S M5M465160D-5S,6S M5M46X400D-5S,6S M5M46X800D-5S,6S M5M465160D-5S,6S

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 Timing Diagrams (Note 28) Read Cycle RAS W OE Address Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max)Note 28: Indicates the invalid output. Indicates the skew of the two inputs. (at M5M465160xx only) ≤ ≤ ≤ ≤ DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only) tRC tRAS tRP tCSH tRSH tCRPtRPC VIH VIL tCRP tRCD tCAS tCPN VIH VIL tCAH tASCtRAHtASR tRCH tRRH tRAD tRAL tASR ROW ADDRESS ROW ADDRESS COLUMN ADDRESS tRCS VIH VIL VIH VIL tCDDtDZC tCLZ tAA tOFF Hi-Z tRAC tOEA tOEZ tCAC Hi-Z tORH tOCH tODDtDZO VOH VOL VIH VIL VIH VIL Hi-Z DATA VALID

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 Write Cycle (Early Write) RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only) tWC tRAS tRP VIH VIL tCRP tCAS tRCD tCSH tRSH tCRP tRPC tWCS tWCH tDHtDS Hi-Z DATA VALID VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL tASR tRAH tASC tCAH tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS VIH VIL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199916 Write Cycle (Delayed Write) RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only) tWC tRAS tRP VIH VIL tCRP tCAS tRCD tCSH tRSH tCRP tRPC VIH VIL tRCS tCWL tRWL tWP tWCH VIH VIL tDZC tDS tCLZ Hi-Z tDZO tDH DATA VALID VIH VIL tODD tOEZ tOEH VIH VIL tASR tRAH tASC tCAH tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS VIH VIL Hi-ZVOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199917 Read-Write, Read-Modify-Write Cycle RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only) tRWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tCRP tRPC tASR tRAH tASC tCAH Hi-Z tRCS tCWL tRWL tWP tDZC tDS tDZO tODD tOEZ tOEH tCWD tAWD tRWD tAA tOEA tRAC Hi-Z tRAD tASR tDH tCLZ COLUMN ADDRESS ROW ADDRESS DATA VALID tCAC Hi-Z DATA VALID ROW ADDRESS VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 Fast Page Mode Read Cycle RAS tRRH tRAS tRP tPCtCSH tRSH tCPRH tAA tAA VIH VIL CAS LCAS / UCAS (at M5M465160Dxx only) tCRP tRCD tCAS tCP tCAS tCP tRPC tCRP VIH VIL Address tCAH tRAD tRAHtASR tASRtASC tCAH tASC ROW ADDRESS tASC tCAH tRAL COLUMN ADDRESS-2 COLUMN ADDRESS-1 VIH VIL W tRCH tRCH tRCS tRCH tRCStRCS VIH VIL DQ 1 DQ4 (8,16) (INPUTS) tCDDtDZCtCDD Hi-Z tCDD tDZC tDZC VIH VIL DQ 1 DQ4 (8,16) (OUTPUTS) ~ Hi-Z tOFF tOFF tCAC tCLZ tAA tCPA tCAC tCLZ tOFF tCPA tCLZ DATA VALID-3 tCAC VOH VOL tRAC tORH OE tDZO tOEZ tOEA tOCH tODD tDZO tOEA tOCH tOEZ tODD tDZO tOEA tOCH tOEZ tODD VIH VIL ROW ADDRESS tCAS DATA VALID-2 DATA VALID-1 COLUMN ADDRESS-3

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199919 Fast Page Mode Write Cycle (Early Write) RAS CAS LCAS / UCAS (at M5M465160Dxx only) tRAS tRP tPCtCSH tRSH tRPC VIH VIL tCRP tRCD tCAS tCP tCAS tCP tCAS tCRP VIH VIL Address tCAHtASCtRAHtASR tASRtASC tCAH tASC tCAH ROW ADDRESS ROW ADDRESS COLUMN ADDRESS-1 COLUMN ADDRESS-2 COLUMN ADDRESS-3 VIH VIL W tWCS tDS tDH tWCS tWCH tWCS tWCH tDS tDH tDS tDH DATA VALID-3DATA VALID-1 DATA VALID-2 tWCHVIH VIL VIH VIL OE Hi-ZVOH VOL VIH VIL ~DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS)

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 Fast Page Mode Write Cycle (Delayed Write) tRAS tRP tCRP tRCD tPCtCSH tCAS tCP tRSH tCAS tCRP tRPC VIH VIL VIH VIL RAS tCAH tRAD tRAHtASR tASC tCAH tASR ROW ADDRESS ROW ADDRESS tRWLtASC COLUMN ADDRESS-2 COLUMN ADDRESS-1 VIH VIL Address tRCS tWCH tCWL tWP tRCS tWP tWCH tCWL VIH VIL W tDZC Hi-Z tCLZ tDS tDH tDZC tDS tDH tCLZ tDZO DATA VALID-1 VOH VOL VIH VIL tDZO tOEH tODD tOEZ tODD tOEH tOEZ VIH VIL OE DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only) DATA VALID-2

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 Fast Page Mode Read-Write, Read-Modify-Write Cycle RAS tRAS tRP tCSH tRSH tRAD VIH VIL CAS LCAS / UCAS (at M5M465160Dxx only) tCRP tRCD tPRWC tCAS tCP tCAS tCRP tRPC VIH VIL tRWL Address tCAHtRAHtASR tCAH tASR ROW ADDRESS tASC COLUMN ADDRESS-1 VIH VIL tASC W OE DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) tWCH tDZO tOEH tCWL tWP tWP tWCH tDZC Hi-Z tDS tDH tDZC tDS tDH tCLZ tODD tDZO tOEZ tODD tOEH tOEZ tOEAtOEA tAA tRAC tCAC tCAC tRCS tCLZ tCWL tAWD tCWD DATA VALID-1 DATA VALID-2 tAWD tCWD DATA VALID-2 DATA VALID-1 VOH VOL VIH VIL VIH VIL VIH VIL tRWD tCPWD tAA tCPA ROW ADDRESS COLUMN ADDRESS-2 tRCS

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 RAS-only Refresh Cycle Hi-Z tRP tRPC tCRP tASR tRAH tCRP tRAS tRC ROW ADDRESS ROW ADDRESS tASR VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only)

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199923 CAS before RAS Refresh Cycle RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) LCAS / UCAS CAS (at M5M465160Dxx only) tRP tRC tRAS tCPN tRPC tCSR tCHR tOEZ tRPC tCRP tCSR tCHR tRAS tRP tRC tASR tRPC tOFF Hi-Z ROW ADDRESS tODD tCDD VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRCH tRSR tRHR tRHRtRSR tRCS

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199924 Hidden Refresh Cycle (Read) (Note 29) Note 29: Early write, delayed write, read write, or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) LCAS / UCAS CAS (at M5M465160Dxx only) tRC tRAS tRP tRAS tRP tRC VIH VIL tCRP tRCD tCHRtRSH tCRP tRPC VIH VIL tASR tRAH tCAH tRAD tASR ROW ADDRESS tASC COLUMN ADDRESS VIH VIL tRCS tRAL tRRH VIH VIL tRSR tRHR tDZC Hi-Z Hi-Z tRAC tAA tCAC tCLZ tCDD tOFF DATA VALID VOH VOL VIH VIL tORH tOEAtDZO tOEZ tODD VIH VIL Hi-Z ROW ADDRESS

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199925 Self Refresh Cycle RAS W OE Address DQ 1 DQ4 (8,16) (INPUTS) DQ 1 DQ4 (8,16) (OUTPUTS) CAS LCAS / UCAS (at M5M465160Dxx only) tASR tCRP tRPC tRPS ROW ADDRESS tRASS tCSR tCPN tRCH Hi-Z tOEZ tRP tRPC tOFF VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCHS tRSR tRHR

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199926 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ Upper / (Lower) Byte Read Cycle (at M5M465160Dxx only) tCRP tRC tRAS tRP tCAStRCD tCSH tRSH tCPN tCRPtRPC tCAH tASCtRAHtASR tRCS tRCH tRRH tRAD tRAL tCRP tASR tRPC tCRP ROW ADDRESS COLUMN ADDRESS Hi-Z tOEZ tODD tORH tOCH tOEAtDZO tCDDtDZC tCLZ tAA tCAC tOFF Hi-Z Hi-Z tRAC DATA VALID ROW ADDRESS VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199927 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ Upper / (Lower) Byte Write Cycle (Early Write) (at M5M465160Dxx only) tWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tCRPtRPC tWCS tWCH tASR tRAH tASC tCAH tCRP tCRPtRPC tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS Hi-Z Hi-Z tDHtDS DATA VALID VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Upper / (Lower) Byte Write Cycle (Delayed Write) (at M5M465160Dxx only) tOEZ Hi-Z tCRP tWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tRPC tASR tRAH tASC tCAH tRCS tCWL tRWL tWP tWCH tDZO tODD tOEH tCRP tRPC tCRP tASR COLUMN ADDRESS ROW ADDRESS ROW ADDRESS Hi-Z tDZC tDS tDH tCLZ Hi-Z DATA VALID VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199929 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle (at M5M465160Dxx only) DATA VALID Hi-Z tDZO tOEZ tOEH tAA tRAC tASR tRAH tASC tCAH tASR tRWC tRAS tRP tCRP tCAS tRCD tCSH tRSH tCRP tRPC tRCS tCWL tRWL tWP tODD tCWD tAWD tRWD tCRP tRPC tCRP COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tDZC tDS tDH tCLZ tCAC tOEA Hi-ZHi-Z Hi-Z DATA VALID VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Fast Page Mode Upper / (Lower) Byte Read Cycle (at M5M465160Dxx only) tCDDtDZC tCDDtDZC Hi-Z Hi-Z tOFFtOFF tCAC tCLZ tAA tRAC tCPA tCDD tDZC tCAC tCLZ tOFF tCPA tCLZ tORH Hi-Z tRCS tRRH tRAS tRP tCRP tRCD tPCtCSH tCAS tCP tRSH tCAHtASC tRAD tRAHtASR tCPRH tRAL tDZO tOEZ tOEA tOCH tRCH tCAS tCP tRPC tCRP tASRtASC tCAH tASC tRCH tRCS tRCH tRCS tODD tDZO tAA tOEA tOCH tOEZ tODD tDZO tOEA tOCH tOEZ tODD ROW ADDRESS tAA tCAH tCAS tCRP tRPCtCRP tCAC DATA VALID-3 COLUMN ADDRESS-3 ROW ADDRESS COLUMN ADDRESS-1 COLUMN ADDRESS-2 DATA VALID-2 DATA VALID-1 VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199931 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ (at M5M465160Dxx only) Fast Page Mode Upper / (Lower) Byte Write Cycle (Early Write) tRAS tRP tCRP tRCD tPCtCSH tCAS tCP tRSH tCAS tCP tCAS tRPC tCRP VIH VIL VIH VIL tCRP tRPC tCRP VIH VIL tCAHtASCtRAHtASR tASRtASC tCAH tASC tCAH ROW ADDRESS ROW ADDRESS VIH VIL tWCS tWCH tWCS tWCH tWCS tWCH tDS tDH Hi-Z tDS tDH tDS tDH DATA VALID-3DATA VALID-1 DATA VALID-2 Hi-Z VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL COLUMN ADDRESS-1 COLUMN ADDRESS-2 COLUMN ADDRESS-3

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 (at M5M465160Dxx only) Fast Page Mode Upper / (Lower) Byte Write Cycle (Delayed Write) RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ tRAS tRP tCRP tRCD tPCtCSH tCAS tCP tRSH tCAHtASC tRAD tRAHtASR tRCS tWCH tOEH tCAS tCWL tWP tRCS tWP tASC tCAH tASR tWCH tCRP tRPC tODD tODD tOEH ROW ADDRESS ROW ADDRESS tOEZ Hi-Z tCRP tCRP tRPC tRWL tCWL tDZO tDZC Hi-Z tCLZ tDS tDH tDZC tDS tDH tCLZ tDZO tOEZ COLUMN ADDRESS-2 COLUMN ADDRESS-1 DATA VALID-2 DATA VALID-1 VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 RAS W OE LCAS (or UCAS) UCAS (or LCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Fast Page Mode Upper / (Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modefy-Write Cycle (at M5M465160Dxx only) tRAS tRP tPRWC tCSH tRSH tCAHtASC tRAD tRAHtASR tRCS tWCH tOEH tCWL tWP tRCS tWP tASC tCAH tASR tWCH tODD tOEZ tODD tOEH ROW ADDRESS tCRP tRCD tCAS tCP tCAS tCRP tRPC Hi-Z tCWL tCRP tCRPtRPC tAWD tCWD tAA tAWD tCWD tAA tDZC tDS tDH tDZC tDS tDH tOEZ Hi-Z tCLZ tDZO tOEA tOEA tDZO tRAC tCLZ tCAC DATA VALID-1 DATA VALID-2 tCAC ROW ADDRESS COLUMN ADDRESS-1 COLUMN ADDRESS-2 DATA VALID-2 DATA VALID-1 VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tRWL tRWD tCPWD tCPA

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199934 RAS OE UCAS (or LCAS) LCAS (or UCAS) Address W DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Upper / (Lower) CAS before RAS Refresh Cycle (at M5M465160Dxx only) tRP tRC tRAS tCPN tRPC tCSR tCHR tRPC tCRP tCSR tCHR tRAS tRP tRC tASR tRPC tRPCtRPC tCRPtCRPtCRP ROW ADDRESS tRCH tRPC VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tOEZ Hi-Z tOFF tOEZ tOFF Hi-Z tCDD VOH VOL VIH VIL VIH VIL tODD VIH VIL VOH VOL tRCStRHRtRSRtRSR tRHR

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 RAS W OE UCAS (or LCAS) LCAS (or UCAS) Address DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Upper / (Lower) Hidden Refresh Cycle (Byte Read) (Note 29) (at M5M465160Dxx only) tRC tRAS tRP tCRP tRCD tCHR tASR tRAH tASC tCAH tRCS tRAL tRRH tRAD tRSH tRAS tRP tRC tASR tCRP tCRP tRPC tCRP tRPC COLUMN ADDRESS ROW ADDRESS tCDD tOFF tAA tCLZ tCAC tRAC tOEA tOEZ tODD Hi-Z Hi-Z DATA VALID tORH tDZO Hi-Z tDZC ROW ADDRESS VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tRSR tRHR

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 199936 OE tASR tRPC tCRPtCRP ROW ADDRESS tODD tRCH UCAS (or LCAS) Address tOEZ Hi-Z tRPC tOFF tOEZ Hi-Z tCDD VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL W tREZ tOFF tOHR tOHC tCRP tRPC tRPStRASS tCSR tCPN tRP tRPC VIH VIL RAS VIH VIL tCHS LCAS (or UCAS) DQ 9 DQ16 (or DQ1 DQ8) (INPUTS) ~ ~ DQ 9 DQ16 (or DQ1 DQ8) (OUTPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (INPUTS) ~ ~ DQ 1 DQ8 (or DQ9 DQ16) (OUTPUTS) ~ ~ Å Å Å Å tRSR tRHR Byte Self Refresh Cycle (at M5M465160Dxx only)

FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs(Rev. 1.0) M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S MITSUBISHI ELECTRIC Aug. 1999 Keep safety first in your circuit designs!

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