M5M44400BRT-7

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FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM

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M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM DESCRIPTION WIVEW) This is a family of 1048576-word by 4-bit dynamic RAMS, PIN CONFIGURATION (TIO febricated with the high performance CMOS process, and is | 4,1, veyre,J00' ==] a] vsscovs ideal for large-capacity memory systems where high speed, ‘OUTPUTS pa? « fa] [25]++ 006 \\oata weuts/ low power dissipation, and low costs are essential. WATE Cone WL] fa]+» 003 }oOTARs The use of quadruple-layer polysilicon process combined [ROW ADDRESS axe ray [e]—cAS SRS ou, with silicide technology and a single- transistor dynamic |STO8E 20H je—ce GuTeuT storage stacked capacitor cell provide high circuit density at Raa reduced costs. Ao A Multiplexed address inputs permit both a reduction in pins NNbUTS at Fy ae and an increase in system densities. afi] [elas PNpOTS Self or extended refresh current is small enough for battery wd Fe]<— As back-up application. sv) veo [3] fa}«— a4 FEATURES Outline 26P0J(300mil SOU) RAS access | CAS access | Addross Type name per i big ) (max. rs) OUTPUT (max. ns) | (max. ns) +f coun, | msMaaaooexx-6-6s| 60 [15 30 Moves fet = Et. Ot }eorauagre” | Menaaaooaxx7,-75| 70 [20 [35 | ara gtreses ooe ++f7 BHA" OP" ware conrao. | waaooaxx-a-es|__ 80 [2040 Ree ied CE a al anes aoe 3 Fale ar OE sccess Cycle Power INPUTS| a2—ofil B Tal A3 | spores Type name time time dissipation «sv)veo fist HA ay [INPOTS (max. ns) (min. ns) (typ. mW) anpress As [itt file AS | Msmaaaooexx-5-ss] 13 | 90 500 INPUTS| ar—list Bole as | meMeaaooexx-6-6s[ 15 [110 [400 ~ | Msmaaaooexx-7.-75[ 20 [130 [350 | Outline 20PSL-B (ZIP) Lwsmaaaooaxx-8-as] 20 [150 | 300_ | XX =J,L, TP, RT APPLICATION @ Standard 26pin SOJ, 20pin ZIP, 26pin TSOP (11) Main memory unit for computers, Microcomputer memory, @ Single 5V + 10% supply Refresh memory for CRT ® Low stand-by power dissipation CMOS Input level -srestescesceseenenenneees5 SmW (max) CMOS Input level-vssrsstesssessseentenenee() 65m (mmax)® © Low operating power dissipation MSM44400BXX~5,- 5S verveeeseeeee 6B7.5mW (max) M5M44400BXX-6,-6S v--reessesesee 550,0mW (max) MBM44400BXX-7,-7S sss 4B7.SmW (max) M5BM44400BXX-8,-BS vss 412.5mW (max) Self refresh capability* Self refresh current <---reseeeeeeeeeees 150 pA (max) @ Extended refresh capability Extended refresh current sss 150 AC max) © Fast-page mode( 1024-bit random access), Read-modify- write, RAS-only refresh, CAS before RAS refresh, Hidden refresh, CBR Self Refresh (-5S, -6S, -78, -8S) capabilities. @ Early write mode and OE to contro! output buffer impedence © All inputs, output TTL compatible and low capacitance © 1024 refresh cycles every 16.4ms(Ao~As) © 1024 refresh cycles every 128ms(Ao~As) * © 4-bit parallel test mode capability * : Applicable to self refresh version (MSM44400BJ, L. TP. RT-5S,-6S, - 7S, -8S : option) only. M5M44400BU, L, TP, RT-5,-SS : Under development MITSUBISHI WM 62494625 0025133 Secs re MISES 3-27

read, write, and read-modify-write operations, @ number of | delayed-write. The inout conditions for each are shown in Table 1. Table 1. Input condition for each mode

8 O16 (as | Co eee BOTAN

M5M44400BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM ___FAST PAGE MODE 4194304 BIT(1048576-WORD BY 4-BITDYNAMIC RAM ABSOLUTE MAXIMUM RATINGS With respect to Vss [ie [Output eurent i 8 [Ps | Power dssivaton —=S—S~S~dCTw wT] C*L em [Toor | Operating temperature | TO [tse [Storage temperature | 150 | RECOMMENDED OPERATING CONDITIONS (Ta = 0~70°C, unless otherwise noted) (Note 1) [Sem] renee Fe] | ['Voo_| Suoply voltage ——SSSCSCSC~sCS | TY [vss | Supply voltage SSS | | OT | High-level input vokage, at mpute | 24[ | 68 |v _| pease feta} Frag | | = v Nu | bowrlevel input voltage others [= 20 [08 | Note 1. All voltage values are with respect to VSS. ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Voc = 5V + 10%, Vss = OV, unless otherwise noted) (Note 2) ; ; ee Tigh level cutout voltage [w=-Sma S| eo | [ Vo. | Low-level output voltage Sidi = a2mA ST OT | OT | [oz | Off-state output curent | Q floating OVavorseev | -10; | 10] uA _| [i inout current Sn 6. SV. Other inputs pine] —10 || 10 | uA | WOMAAODE-5, 55 i a ee Average supply current RAS, CAS cycling ° : [F100] Icc1¢ay) | from Voc, operating tre = two = min. mA eee 9,4, 5) esmnons. 15 | ee [85 | : a ee [RAS=CAS= Vin cutout open | | | _2 | locacay | SUPY coment from Noe. [asuaiis | RAS = CASE Ver — 05 [7m " output open a 1W5444008-5, -5S , Average supply current =e] RAS cycling — [100 | Icca(av) | from Vcc, refreshing TAS = Vin, tac = min. mA ee 3.8) OS ee lote S 9) T psna4008-8, -8 ee WSH444008-5, 55 oe a ‘Average supply current Seve re ao locacay) | from Voc, Fast-Page-Mode * TAS cycling mA (Note 3, 4,5) ‘trc = min, output open. 8 14:9) Paton 5 | Tverage sueply Sorent [ISMUOOES. 5 | [ios] leacay | for Voor CAS before CAS eatere AS rotesh ay Sc8AN) | AS refresh mode | weaaatscr, 75 | SVN te = min oe ee (Note 3)| wewasao0e-8, -85 [os | RAS 2 Voc - 0.2V TKS z Vc - 0.2V or CAS 5 0.2V Average ‘supply current from Voc TAS store FAS ety or lecscav) | Extended-Refresh cycle TAS before RAS refresh cycling HA (Note 6) WS0.2V or 2 Voc - 0.2V OE S0.2V or 2VCC-0.2V Ao~A9 $0.2V or BVOC -0.2V. DO = open, tac = 125 us RAS = CAS 5 0.2V Pt [iso a | ‘Note 2. Current flowing into an IC is positive. out is negative. 3. lect (AV), ICC3(AV) and ICC4(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4. Ioc1 (AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open. 5. Column Address can be changed once or less while RAS= Vi and CAS = Vin. MITSUBISHI @@® 62459825 0025135 378 oe ies 3-29

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM ee (CAPACITANCE (Ta = 0~70°C, Voc = 5V + 10%, Vss = OV. unless otherwise noted) i i ee Gu | Put capacitance, ee | adress inouts ween er ee Gea] nowt capacitance, dock anes ee a inputs Vie 25m [| Gra | lout Suto capacance i 25mvers ee a data ports re a ‘SWITCHING CHARACTERISTICS (Ta = 0~70°C, Voc = 5V + 10%, Vss = OV, unless otherwise noted) (Notes 6, 13, 14) Symbol [wsncaanoe-s,-55[wsue44oon-6,-6s [wsw4ao08-7,-75 [WN444008-6 85] Unit | Min [Max [Min [Max [Min | Max [ Min | Max | Access time from CAS (ote 7.8) [13 [is [20 [20 Fas | tac | Access time from RAS (Note 7.9)[ [50 | {60 [70 | [a0 [ns Column Address ecoess time (Note 7.10)[ [25 | [30 | [36 | 40 [ns | Access time from TAS (Note 7,11) precharge : | toca | Access time from OF (Note 7) [ia [is [20 [20 [as Output low impedance from jes [orcen mre ee owl s TPs] Ts] [et [i | = [ae el Taf ofele [alo fal | [= [age owl Telefe [eof « | Note 6. An initial pause of 500 us is required atter power-up followed by @ minimum of eight initialization cycles (any combination of cycles containing a RAS clock such as RAS-only refresh). Note the RAS may be cycled during the initial pause. And any 8 RAS or RAS/TAS cycles are required after prolonged periods (greater than 16.4 ms) of RAS inactivity before proper device operation is achieved. 7. Measured with a load circuit equivalent to 2TTL loads and 100pF. 8 Assumes that tAcDz tACD(max) and tascz tasc(max). 9 Assumes that taco S trcD(max) and tRADS tRaD (max). If tRCO or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tACD or tRAD exceeds the value shown. 10. Assumes that tRADz tra (max) and tasc s tasc (max). 11, Assumes that tcp S tcP (max) and tasc & tasc(max). 12, toFF (max) and toc (max) defines the time at which the output achieves the high impedence state (lours | +10uA1) and is not reference to VoH (min) or VOL (mex). M@@ 6249825 0025136 234 MITSUBISHI 3-30 ELECTRIC

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read- Modify- Write, Refresh, and Fast Page Cycles) (Ta = 0~70%, Voc = 5V + 10%, Vss = OV, unless otherwise noted) (Notes 13, 14) i [ Min [Max | Min [Max [Min [Max | Min | Max | Rotresh cycle time [MeMaaaoos |" fie [tea] tea P16. | [memaaaoon(s)[ | ize { [ize {| aaa] | 128 | [te [RAS high pulse width Ff 30 | | ao | fo feo | ts | | taco | Delay time, RAS low to CAS low(Note 15) 18 [37 |"20 [45 [20 | so [20 [60] ns | | tore | Delay time, CAS high to RAS low [|S [ [ s{ [st fs | [ns | [ treo | Delay time, RAS high to CAS low [| 0 | [of | of fo tt ns | [ten [CAS igh puso width to | to fo | to Ff ns | Se A ee (Note 16) | tasn | Row address setup time before FAS tow [0 { [0 | | o | fo Tas Column address setup time before CAS low: [ae _ [Coen ates ee Hoe Eee | O | vol of vol of vol of we] ow | | tess | Row address hold time after FAS tow | @ | [to [fo [0 [ns [ tea | Column address hold time after CAS iow | 13[ [is | ts [is || ns | tozc “| Delay time, data to CAS fow (Note TO | [of fo | fo [ns | tozo | Delay time, data to OF low (Note |_| [of | off of | ns | | tcoo | Delay time, CAS high to deta (Note 19) 13 [fis | | 20 | | 20 || ns | tooo | Delay time, OE Figh to data (Note 19)[ 13-[ [is || 20 [20 | ns | [ax [Transition time (Note 200) TsO T 1 ToT a | sot tT sot ns | Note 13. The timing requirements are assumed tT = Sns. 14, Vi4(min) and Vi (max) are reference levels for measuring timing of input signals. 15. tacD (max) is specified as @ reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tACD is greater than tRCD (max), access time is controlled exclusively by tcAC or taa. ‘trcD (min) is specified as tho (min) = thax (min) + 2tT + tasc (min). 16. Ao ima) is specified as a reference point only. If tRAD 2 tRAD(max) and taSc & tac (max), access time is controlled exclusively 7 Tess (nex) is specified as a reference point only. It tacd 2 tacD (max) and tasc 2 tasc(max), access time is controlled exclusively 18. Enter toze ‘or t0Z0 must be satisfied. 19. Either tcDd or toDD must be satisfied. 20. tT is measured between VIH (min) and Vi (max). Read and Refresh Cycles [ Min | Max | Min [ Mex [Min | Max | Min [ Max | [tc [Read cycle time oT fo ff izo | iso f {ns | | tzss__| RAS low pulse width | 50 [T0000] 60 [T0000] "70 [10000] “80 [10000/" ns _| | teas [CAS low pulse width 13 [10000] 15 [10000] “20 [10000] 20 10000] ns | [ tes [CAS hold time after RAS tow | sO | | eo | [off eo | ns | [ tes [RAS hold time after CAS iow | 13 | | 1s || a0 [| 20 | ns | | tacs "| Read setup time before CAS low | OT | ot | of | of ns | | tecn [Read hold time after CAS high (Note 21/0 [| o| | of | oft ns [ tem | Read hold time after RAS high (Note 21) 10 || ro [wo [| of [ns | [ tw. | Column address to RAS hold time [25 | [a0 {fas {| ao [ns | tocx [CAS hold time after OF low | 13 | is || 20 [20 Fos [toms [RAS hold time after OF tow ts [Tis | 20 | | 20 TP ns Note 21, Either tRCH or tRRH must be satisfied for a read cycle. MITSUBISHI MH 6249825 0025137 170 mm aie MTSUBS: 3-31

M5M44400B,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Write Cycle (Early Write and Delayed Write Cycles) [min [Mx Min [Max [Min Max [Min Max | [ae Wate et ipo] [tas RAS low pulse wath “80-1080. [To000]— 70” [ro6G0|— Bo T6600] — ns —| [tes CAS low bulse-wiath———| 1 T0000) 18 [10000|—20"[Hooo0| 20 [T0000] — ne] [cot CAS hal tine ater RAS Tow 80] Peo | to] eo] ts | [asi RAS hold tie oftr CAS low [18s | 20 | [ines | Wits set tine before ORS low thew 25] 0} fof ot ot | Peet Wteeld tine afer CAS bow | eo te} ee] [on [CAS old ne attr W lew | tes |e fat] [et RAS hold tine aftr Wotow ts tis | oo P| [we Wits pose width te to] [os | Osta sou tine below OAS tow or Wow] 0 [Jot oot] [ior oste old tw afte CAS tow or Wow | eo} as is || [ean LOE fete tne ater Wow pe pis} | 0 | Read- Write and Read- Modify- Write Cycles parameter [Min | Max Min | Max | Min Mix] Min Max | = wna tel fel tml tel | = | (Note 22) [eas | FAS Tow pul wath] T0000) rooeR|T Beal 00661 —s—| [teas | CAS tow bulse_wieth | a8 [T0000] 80 [r0000]— 6 T0000]—65 [T0000] —rs—] [toot | CAS hal tine ater FAS Tow as] [tsi [RAS fold tine efter CAS low | 4 [soos os | | [acs | Reod setup tine before OFS ow To Jo} —}- ot Pot | [toro | Belo tine, ORS Tow to W tow” CNote 230] 35 [as ae a] [te Dsiay tine, BAS low to W low” (Note 23) | ~131—T-80- [60-100] | [tino | Dsay tine. seress te W low (Note 23) | “a8 [80s | es | [om [CAS Folie after W tow [13] 1s} ee [20s | ee a [ie | Write lee width to is is [os | Osta sous tne bales Wow | of] oop oY [tor Ost ol tne aftr Ww a Hess TOF ha ite aise W los boasts ot Ps] Note 22. tRWC is specified as tawc (min) = tRac (max) + tooD (min) + tAWL (min) + tRP (min) + 4tT. 23. twes, tcwo, trwD and tawO and tCPWD are specified as reference points only. If twcsZ twcs(min) the cycle is an early write cycle and the 00 pins will remain high impedance throughout the entire cycle. It tcwo 2 tcw (min), tawd 2 tawD (min), taw0 2 tawD (min), and tcPwD 2 tcPwD(min) (for fast page mode cycle only), the cycle is a read-modity-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed-write) of the DQ (at access time and until TAS or OF goes back to VIH) is indeterminate. . Fast- Page Mode Cycle (Read, Write, Read- Write, and Read-Modify- Write Cycles) (Note 24) Cin [ Wor [win T-Max [Win [Max Win Tox [i Rat ange de eTocs Se te [Ba a [wom | Fare Raa pase vead wrterrmnd mesty | an] [ze] | os] [too] |e write cycle time [i [CAS ich ale with (Note 28)| 8 | 12 | 10 -18-[ To] 18-10] 20-[ ns] [ism RAS hold tine after OAS prehare [303s aa |] [tonne —[ boay tine CAS pecire tw W iow (Note ZS] 30 [ 3} [ao as |] Note 24. All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25. tras(min) is specified as two cycles of CAS input are performed. 26. tcp (max) is specified as a reference point only. mB 6249825 0025138 007 mm

4 MITSUBISHI

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta = 0~70°C, Voc = SV + 10%, Vss = OV, unless otherwise noted) (Notes 6, 13, 14) Symbol | wswaao0e-s,-55 [ws9444008-6, 6S [sw444008-7, -7S [wsMA440OB-8,-85} Unit | Min [Max |"Min [Max | Min [Max | Min | Max | Access time from CAS Woe7@| [is | [20 [| 25 | 25 ns | Access time from RAS. Note 7.9 jf 65 [| Pes [| 75 | 85 | ns | Column Address access time (Note 7,10| [30 | [35 | | 40 fT 45 | ns | | tora | ‘Access time from CAS precharge Note 1D[ | 35 [ [40 [fas [60 | ns | [toca | Access time from OF Note MT te | 20 TT as | 25 | ns | TIMING REQUIREMENTS (Te = 0~70°C, Vcc = 5V + 10%, Vss = OV, unless otherwise noted) (Notes 13, 14) Read and Refresh Cycles Symbol Parameter | wswaado0s-s,-58 | Unit | Min | Max | Min [Max | Min [ Max | Min | Max | [tic | Read ovele time | OSH | IS | ae | ee | Tons | tas [RAS low pulse width | 85 [10000] 65 [10000] 75 [iooo0] 85 [10000[ ns | [teas | CAS low pulse width «| 18 [10000] 20 [10000] 25 [10000] 25 [10000] ns _ | CAS hold time after RAS low js {| est ft | est [ns | RAS hold time after CAS low 2 | tear | Column address to RAS hold time | 30 [| 36 [| aot | a5] Tons | | toch | CAS hold time after OE low 18 | | 2of | a5 | as | ns | [toni [RAS hold time after OE low 8 TT 20 25 TT 5 Ts | Read- Write and Read- Modify- Write Cycles Symbol {sw444008-5,-5S | wan444008-6, 6S [W5N444008-7, -75 | WENAAAOOB-8,-BS]} Unit [Min [Max | Min | Max [ Min [Max | Min [ Max | Read Write/read modify write cycle time | 15 185 (Note 22)| ns | tras | RAS low pulse width |" 91 |10000] 100 [10000] 120 [10000] "130 [10000 ns | | teas | CAS low pulse width | 84 [10000] 55 [10000] 70 [10000] _70 [10000] ns__| TAS hold time after RAS low [orf [oot izof P30 ns [ tas | RAS hold time CAS low | aT ee TT ol ToT [ons | Delay time, CAS low to W iow (Note 23)| 40 {| 4o{ [| as] Tas | ons | Delay time, RAS low to W low (Note 23)| 78 [ [es [ | os | | 105 | ns [[tawo [Delay time, address to W low (Note 23) s3] | ssf | eof es} ns | Fast- Page Mode Cycle (Read, Write, Read- Write, and Read-Modify- Write Cycles) (Note 24) Symbol Parameter | wswaa4008-s,-55 [wsw444008-6, -65 | WEMA44008-7, -75[WSM644008-8, 8S] Unit [Min | | Min [Max | Min [Max | Min | Max | Fast page mode read/write cycle time | 40 | | 4] Tt sof { ss{ | ns | teawe | Fast page mode read write/read modify 76 write cycle time | teas | RAS low pulse width for read write cycle | 90 [100000] 110 [100000 125 [100000] 145 [io0000|__ns_| | tcers | RAS hold time after CAS precharoe | 35} | 40] | a5] | 0] | ns | [tcewo [Belay time, CAS precharge to W low (Note 28/35 [| 40[ | 45] | sof ns | Test Mode Set Cycle Symbol Parameter Unit | Min T Max | Min [Max | Min | Max | Min | Max | | twsa | Write setup time before RAS tow | 10 | To TT to Tf io fT ns | [evnin | Write hold time after RAS low | to | Po | is Ts TT ns | M@™ 6249825 0025140 765 a MIS: BISHI 3-34 ELECTRIC

M5M44400BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM ee Note 29. Self refresh sequence ‘Two refreshing ways shoud be used properly depending on - the low pulse width(trass) of RAS signal during self refresh period. 1. In case of trass < 300ms

1.1 Distriduted refresh during Read/Write operation

(A) Timing Diagrams Read/Write Cycle Self Refresh Cycle Read/Write Cycle —_—___—Fead/Write Gyele___Self Refresh Cyclo Read/Write Cycle tnsD trass < 300ms SND last refresh cycle first refresh cycle Table 2

1.1.1 CBR distribated Refresh

‘i Read/Write> | Seif Refresh—> ‘© Switching from read/write operation to self refresh operation. Read/Write Cycle | Seif Refresh Read/Write The time interval from the falling edge of RAS signal CBR distributed in the last CBR refresh cycle during read/write operation refresh {nso + tso $ 16.4ms period to the falling edge of RAS signal at the start of RAS only self refresh operation should be set within tnso (shown distributed refresh| ‘80S 16 HS in table 2). ‘© Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of (8) Definition of refresh RAS signal in the first CBR refresh cycle during read/ Definition of CBR distributed refresh write operation period should be set within tsxo (shown The CBR distributed refresh performs more then in table 2). 1024 discrete CBR cycles within 16.4 ms. Definition of RAS only distributed refresh 1.1.2 RAS only distributed refresh All combination of nine row address signals(Ao~As) © Switching from read/write operation to self refresh operation. are selected during 1024 discrete RAS only refresh The time interval tus from the falling edge of RAS signal cycles within 16.4 ms. in the last RAS only refresh cycle during read/write ‘operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16 us. © Switching from self refresh operation to read/write operation. The time interval tsno from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/ write operation period should be set within 16 us. MITSUBISHI MB 6249825 0025141 bTL eas 3-35

M5M44400BU,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM eee

1.2 Burst refresh during Read/Write operation

(A) Timing diagram Read/Write Self Retresh Read/Write tNSB. trass < 300ms. ‘tSNB- i mUaUs tne ee aWantat a first refresh cycles refresh cycles: last refresh cycles 1023 cycles 1023 cycles refresh cycles Table 3 7 1.2.1 CBR distributed Refresh ; Read/Write | Self Refresh—> Read/Write Cycle | "Sat Refresh Read/Write ‘© Switching from read/write operation to self refresh operation. CBR The time interval tse from the falling edge of RAS signal tuse S 16.4ms tsna S 16.4ms in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of PAS only burst tnss + tsne S 16.4ms self refrash operation should be set within 16.4 ms. ‘© Switching from self refresh operation to read/write operation. The time interval tsva from the rising edge of RAS sional at the end of self refresh operation to the falling edge (B) Definition of burst refresh of FAS signal in the last CBR refresh cycle during read Definition of CBR burst refresh /write operation period should be set within 16.4 ms. The CBR burst refresh performs more then 1024 continuous CBR cycles within 16.4ms. 1.2.2 RAS only distributed refresh Definition of RAS only burst refresh © Switching from read/write operation to self refresh operation. ‘All combination of ten row address signals (Ao~As) The time interval from the falling edge of RAS signal ‘are selected during 1024 continuous RAS only in the first RAS only refresh cycle during read/write refresh oycles within 16.4 ms, operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tnss (shown in table 3). © Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/ write operation period should be set within tsvs (shown in table 3). Mi 6249825 0025142 538 4 MITSUBISHI 3-36 ELECTRIC

M5M44400BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM 2. In case of trass 2 300ms (A) Timing diagram Self Refresh Read/Write tRass & 300ms. REF “ Laer refresh cycle 1024 cycle Table 4 ‘CBR distributed refresh RAS only distributed refresh CBR burst ter & 16.4ms RAS only burst_refresh (B) Definition of refresh The same as 1.1-(B) and 1.2-(B) Regardless of the refresh (CBR distributed refresh, RAS only distributed refresh, CBR burst refresh, RAS only burst refresh) during Read/Write operation the minimum of 1024 cycles refresh should be preformed within 16.4 ms from the rising edge of RAS signal at the end of self refresh operation. M™ 6249825 0025143 474 aie Misuasee 3-37

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Timing Diagrams (Note 30) Read Cycle ‘trac ‘tRAS tre View — RAS Vie ~ ‘tere treo tRSH | tRP tore a [rs YT | Vis ~ PRBS Roy sectatete® RS CAS secenreee, ee, Vin — REY ey ~, SR ROW | ESR COLUMN ERRKKKK RRR RE RR iL — SR3e5eoe5e5g teretetere’ eateletereereee NOOO OOO OO teen : tre tcDo} RRR RRR RRR OG Satetacanecaroneesces CINPUTS) Vi — SSSXQe0SSPS SNS SR tetetetetetateteteted Dai~Da.VoH — J ' 1~DO Hi-Z VM Hi-Z (QuTPUTS) ¢ Ys. ATA VALID Vis ~ QOS Om oe Saseresezes iSececeneterecetereceneretecereres Vi. = SRS Sebo eS eS eS SC RR CCC BERR SPS I I: Note 30. retatonatatenete indicates ‘the don’t care input. BKK RK VIN (min) $ Vins VIE (max) or VA. (min) & VIN & Vib (max) QUE: Indicates the ivald output

M5M44400BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM _—_ FAST PAGE MODE 4194304-6IT(1040576- WORD BY 4-SIT)OYNANC RAM Write Cycle (Early write) two Vin = { | Vi = ‘tORP. tRCD tRSH | [tre _ toRP | i: Vu - SOSRRy RERy TAS tT eR Ry Vin — SSS) 90 ‘tasR. A Vin — RRR BES PRR nro Vie — ROSY ROSY OS OY tyes, wc Vid — REBT ERR w OA [ESS Vit. — RRS RR FRI KIS ts ton DQi~DOa Vik = BERR RRR Niserisonrrrnnn ora rome (INPUTS) eeetatatetatatatataneonrseseestees DATA VALID asasescatansseeetatstareetetetatatetseenneeesssoeteeetts Vie = BSR SSSR RRS | iatetecateteretatetetecacereretereterereteeeee esterases DQ;~Da.VoH — Hi-Z (OUTPUTS) og = Vit — RQ RK IIHT OE seiueeeneeumesnmmneneemeneemme mre SES Vib — SRS SSIS IK IKK II KIKI IOI IN eSeSeSSSSsSSSSSsseSeSeeeSSSSSsSSSSSSsSsssssSeeSSSSSSSSSee mm 6249825 00 Palins 3-39

M5M44400ByJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Write Cycle (Delayed Write) twe FAS a | Vi = tone a ne tepe| | Sn Tl See, ORR oS eee By Vic — EESSEy 1S tASR, | aa | Vai — SRR ROW LO SESS < Poco, COLUMN: teteheteteteteteteteh Seheta tetetetete. ROW, Ao~Ag acececec® ) esezesere,| ) aaeacetetatatetetatat eteta Matetetets | Vu ~ S355 7%_ ADDRESS __ ARES ADDRESS BESSY p_ADDRESS tres rea | | ~ Vid = SRR oovoocrocooecoce ooo CCF Setseteteeeteeet eet et tehtceectete Ww ssitneeeeeaseerrreeesnrceenneeenst See Vit — RESIS SESS OSES E OOOO LOIS wor || | itoz¢| 4 tou ~l Vin — BBBSSSBSSoopro rrr ey ESO ESR (INPUTS) Vie — 232259825050s059505 sos See ee, stetatatatatetececetataratetetetere' DQi~Da4 Vou ~ Hi-Z. GG; Hi-Z (OUTPUTS) Vou ~ Vy oe toe OE soceceeococosoresesesererereseresesereseerrmnernnerererenen sssatetetenetececececececocerenecoreceret Vi = SoS CH Watatetetaratateterererererererereereres 3-40 ae ELECTRIC

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Read- Write, Read- Modify- Write Cycle tRwe, tras the Vin = RAS Vi tex — | tare tone Vin — SOOO sa CHS BOIYy | RO tRAD taASA, {RAH Si Vu. - SSSSSa,_ ADDRESS a ADDRESS RRR oon p_ADDRESS MAME corevorscarccnconetn seocecaconnconssonee’ PRRRR RRR RRR RRR RRR W See eee | PI VIL ~ BERS RSS SPSS PKR FSS RR. ° tos| tOH DQi~DQx Viv — EE. Hi-Z, SS sesensnanazenenecececenenanen aeereareereat eneereeaetne EMF DATA VAUD Weerseseeneaes Senos eee ee ieacereneoretene (INPUTS) Vi, - SESSESSECOR SCOTS 5) CESSES ONSS Dai~pa.¥o4 — Hi-Z ny paral Hi-Z mma [ | toon Vir ~ SRS Oooo mono oT Porooromraocom rere rceeeaneenennenommeneemeemee! eaten OE va ~ Baebeatapeeeesspees epee eckkiccosiesenesseee WM 6249825 0025147 OLT fetes 3-41

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM ee RAS- only Refresh Cycle tC ' — ve Po AS we tAPC _tCAP. Vu — SERED | J oS SR Roy Vu. — SRR Ry tASR Vin — RRR PRR oo TT OTN Vi ~ SEY RSS NNR ADDRESS Vi — FORRES NID Ww Seersrenreesororsrererorseeeorsereeieoeereseeeeeete eee meee Vi. — BERRI RII I NN IIIS Bibescscscersanananscsccatanarstaecatananarotecanananeeseranansnsetunanensetetenanarstcenatansteeeatatarseeatatatatanaesesetatatatetstste4 DQ ~DQe Vir — SE (INPUTS) oesesesasenenoesssenmronecsesesnnereessemneronoreesnanneneessennereeseeeeeneneeeeemeneeeeeseueneeeeeseemmeeenseeesneeeemeneeeeeeseett BMaasatatateetatatatatetetatatatatettatatatatetstatateteetatatateetatatatateetetstatattstatatetetettetetatetstsitetatetatetetetetetetetntn Da:~Da.VoK ~ Hi-Z (OUTPUTS) Vou — Vit — SERRE Roroorrere oreo OE searoreerunerseereres ee S55 5 Vin. = SR OR ORIN INI I RA ERNNI 3-42 ate MES

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM CAS before RAS Refresh Cycle, Extended Refresh Cycle* tre » tre tRP_ tRAS tre RAS ve || | . Vie —. te tec esa tec toe cas YM me Rh Ry Vie -. A sotece, KY Vis — RRYRRR RR oO NN PO | +tRHA tres| ~ ONY RENEE RE CENEL ELEN Vii - YW RRR eeasatatatataatatetatatetatetattate (INPUTS) Vi ~ 952A SRI OIRO IR OI LI IIH IN OI OND tore Da:~payeH — } » Hi-Z (OUTPUTS) Yo. — tocz = LERNER TO TOT TOTS MUD SS cee SS Vit — BRR OIRO? MB 6249825 0025149 992 me pees 3-43

M5M44400BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Self Refresh Cycle" (Note 29) te tras tres pas (VET Vi - tree tAPC, tcsR tore Pp Vin = get 62 oA Roy Ke Se Sy : oy Ves — SERIE RR I RP oe TT TTY ROW. Ao~wAs RRR LR OSORIO RROR ADDRESS CoOL VIL I OO trac, || tren trcs| | a Via — oy aasesesecacesesecegasecesecacenesecanacexecocazezecenanelecenaseteranane Tec eneceTecsnacecacatete" Ww Roy Rsxrrorxerrrcmmncenronuceoermreemee ey ey _seseesoreereereemeoeeemeoeeoemeem mem NTT Vu- oy estesetittatatateteteattatetateetattettetatetaete teteeteteteteeteteet to00 Vu ~ stasstasseretattateetatotteetatoetotoetetotsetote ottoetetretoeemetetme emt eet Vox — Hi-Z D0:~Dd ) (OUTPUTS) You — toez topo Vin — sguetatehahctetetetatchchcctctrhntctchctcect cere tcictcirecicich crac tctct rice china ccecicich chet cicectcectciee cicicictcinh cect eet hetcictcirte SO S55 £25 sg eS "0 SSS sees Vie BSS SS SSS SR IR RII IK I IR IK IRI IIIS 3-44 wales

. MITSUBISHI LSIs M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 31) tRC trc tRAS. {RP tRAS. tre Vin = RAS Vi- ‘toRP) ‘tRCO tRSH Vi - Bey tast Vin — BA I esasasn a aacaeueuecerenenerenacacacacecerecetetet estetetatatatatete Vn - By ia: ——— ODRESS Vin ~ REISER agasasacecerererenenesecesesecececesess eetseststsintstatatstststststetat Ww eeeteiareeres reeees sieeateeeeneneneneens eee Ww etstetetetanatat uasetesete™ Stanecececotatetecotatenesosoneretoren ecerounsecesonasssonentceeetets Vi. — BEEBE IY ‘Seeneeareoeeeeeeeet meee : coo _ SESRRSER REESE ERERREEER DQ1~Ds Vis ~ FRE A _ |} SO (INPUTS) seen eee seeseetetatetetse Vin — SRR ens iectattatat ~DQ.VOH ~ 7 i i ee G,. DATA VALID ly HZ toz0 tOEA, Vin — RRR Kero SATOeeeaeeececceecatctatee OE eseceatanestctatatetststetataceetetetetete sctaterseestetaratereeettetere Vi. — SERIO LRRD . ly write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. oO beuqees 0025351 540 AE 3-48

: MITSUBISHI LSIs M5M44400BU,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM $$$ BAS TPACE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Fast Page Mode Read Cycle tRAS {RP View — RAS Vi — tes tec tRSH tor [tec teas | ter Vin — SOY sete Ve - RRR pow VSS con EER EXTIER yall ~, RN stores’ UMN BERR PERS COLUMN MSsosbsisoscl” COLUMN ‘NAbSKo<bS ROW v Pt eT Ty rir_| IT Vi. ~ SSSI ORY Y 3) weet tDZzC tcoo, } | toad i fn | fia | | He | | fore Pal DQ:~Da.VoH ~ Hi-Z CMF vata lS DATA | DATA env. = Cm A — (ac TL NA — | Vit — SSSI SR OOOOH geal eect EES RCO ERP RK KKK RK KN PSAP SSeS exert Setets, eetets Setetecace Or soy, - BA Lesson PES Loseepsees tog [ozo] ozo] jon a eeeeSSSSSSSeSSSSSSSSSSSSSSSSSSSSSSSSSSSeeeee mm 6249825 0025152 437 3-46 Ja iees

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Fast Page Mode Write Cycle (Early Write) tas tre eee Vi = tosu tre tas tore] tRCD tcas tor, Vin - SOF \\ Sy a — BEES ‘tASE) Ves — SRF Row ARSE coun VERA EEE co LEIA f \\ AF conus WARS ROW. Ao~As soatetece’ seesesens Neeesxrscesecd COLUMN Mixocor coe i gecesesens Vin ~ SESSA ADDRESS PRN, ADORESS Ie ACO ESS SSF f ADORE SSS PRES YADORESS twes| twoH Vid — RRR PRETTY ROBES PEER Ww semen [percent Poseren freee Vi. — EEE Seeeressers Setar Setanta DO1~DO4 Vir — SRR ERR DATA WASSA DATA “ASEH DATA BRSRERRERS aeereereereareeneerereetts Wesco Neo Wereseis (INPUTS) i, ~ SSSR RRS VALIOI PRS. VALID2 FREER VALIDS _ARSESS RNS Da1~Da.V — Hi-Z (QUTPUTS) yo, Ves — OD OE seuseeeeuneecronrerermromnemnemctenee eee ON Nie scsereoreoroeoerereroen erence tere eee eee cee ees 6249825 0025153 313 eles 3-47

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM $$$ $$$ EAS TARE MODE A1OKSO8 BIT (1048576-WORD BY 4-BIT)DYNAMIC RAM Fast Page Mode Write Cycle (Delayed Write) - tRAS tRP. Vin = Vi = tege| [ests [we os Vit — SOROH Sy Vu - Ey Vu~ SRF now SASSAL coLumn WESREEY column AASSRSESEAS Row o~ AS Setenene® (| setecete | ) Setatetetecetatete: siete: ) Shake etetecatecete. A Vie — SSS9, ADDRESS JNSSSIA. ADDRESS! JUS COA. ADDRESS2 RSs SSA ADDRESS | I ve Ww Vi OS RS Bey Access Vic — BERRI, i Esy } PSR twon || | tozc ! tog | tOH DQi~Dd4 Vou - Hi-Z Wi) U7} Hi-Z (OUTPUTS) Yo, — LA, -/ UT sooel to TE VM” SERS SEERA ESR —— SSSSSSSSSsSsSSSSSSSsSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSFese 3-48 oe iteee

M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Fast Page Mode Read- Write, Read- Modity-Write Cycle {RAS tRP vi a RAS Vi Fi Vu ~ BEESY i 1 ! oS ee Vu - Sy tasAl {ASR Aow~he YE” BRRRA f aS BSE COLUMN, YRSSSREESSISEO COLUMN, NESSES ROW. Vi. — SBSa7¥, ADDRESS PREY = CESAR Te CEERI, ADDRESS = al Tp |. ve Vt ~ SRR RRR PRER ERY as essere Ww seteeeerentes testers, ee esctesneestts [| | | tcrwe ph tes ny ten D0:~DQs Vi ~ a Hi-Z AF pata | EM Toata VWeSeEe See Rees SY & gS WEES (INPUTS) Vi. ~ SESSESER RS SENS | | 7 VALIO! Ter VALID2_ FRSSSSee5 ~| Vou — Eze) Li: i i= "a | "ppm — tne FT Le tRAC — [tooo I toez v2 | toez [tek ~ BESREPASKSKS SESE NRERS EREREREERE OE Ma sso RES Vie — RRR eretsestsestatat MITSUBISHI @® 6249825 0025155 1b ae SES 3-49

MITSUBISHI LSIs . M5M44400By,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM ——__ FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM Test Mode Set Cycle (Note 32) tAC tRE tras tre. Vin = Va = Vie — “a8 Kor Vi = Wer. 0% w se) BESO ~l Vie — BERR acon OS (INPUTS) yy — SRS KI KICK RS KI I I I I 80 1 I 8 8 8 9H I torr i. DQ1~D0.VoH — \\ Hi-Z (OUTPUTS) You — toEz Vit ~ FEO TTS TE vu - ERR RR RRR RRR Note 32. The cycle is also available for the initialization cycle, but in this case device enters test mode. The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram. ‘The test mode function is terminated by either a TAS betore RAS(CBR) refresh or a RAS only retresh cycle. During the test mode, the device is intemally organized as 4 bits wide (256 kilobytes deep) for each DQ (input/output) port. No addressing of A0,A1(column only) is required. During @ write cycle, data on the each DQ (input) pin is written in parallel into all 4 bits for each DQ port and can be written independently for each DQ port. During @ read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4 bits are equal, and a LOW ‘state if any bits differ, During the test mode operation, a WCBR cycle is used to perform refresh. 3-50 eines

Product Information

M5M44400BRT-7 specifications and overview.

Summary

FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM

Description

FAST PAGE MODE 4194304-BIT(1048576-WORD BY 4-BIT)DYNAMIC RAM

Source title M5M44400BRT-7 Datasheet(PDF) - Mitsubishi Electric Semiconductor

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