M5M44265CTP-7

M5M44265CJ MITSUBISHI | Alldatasheet

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EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs

DESCRIPTION

FEATURES

Standard 40pin SOJ, 44 pin TSOP (II) Single 5V±10% supply Low stand-by power dissipation CMOS Input level 5.5mW (Max) CMOS Input level 550µW (Max)* Operating power dissipation M5M44265Cxx-5,-5S 688mW (Max) M5M44265Cxx-6,-6S 605mW (Max) M5M44265Cxx-7,-7S 523mW (Max) Self refresh capability* Self refresh current 150µA (Max) Extended refresh capability Extended refresh current 150µA (Max) Hyper-page mode (512-column random access), Read-modify- write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, OE and W to control output buffer impedance 512 refresh cycles every 8.2ms (A0~A 8) 512 refresh cycles every 128ms (A0~A 8)* Byte or word control for Read/Write operation (2CAS, 1W type) * : Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S : option) only XX=J,TP Type name access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycle dissipa- (typ.mW) Power tion M5M44265CXX-7,-7S M5M44265CXX-6,-6S 60 110 130 550 475 access time (max.ns) OE M5M44265CXX-5,-5S 50 13 25 90 62513 APPLICATION Microcomputer memory, Refresh memory for CRT, Frame Buffer memory for CRT PIN CONFIGURATION (TOP VIEW) DQ 1 (5V)VCC VSS (0V) NC W RAS UCAS OE Outline 40P0K (400mil SOJ) DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 (5V)VCC (5V)VCC NC NC LCAS NC DQ 12 DQ 11 DQ 10 DQ 9 VSS (0V) DQ 16 DQ 15 DQ 14 DQ 13 VSS (0V) DQ 1 (5V)VCC VSS (0V) NC W RAS UCAS OE Outline 44P3W-R (400mil TSOP Nomal Bend) DQ 2 DQ 3 DQ4 DQ 5 DQ 6 DQ 7 DQ 8 (5V)VCC (5V)VCC NC NC LCAS NC DQ 12 DQ 11 DQ 10 DQ 9 VSS (0V) DQ 16 DQ 15 DQ 14 DQ 13 VSS (0V) NC: NO CONNECTION EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7, -5S,-6S,-7S MITSUBISHI LSIs PIN DESCRIPTION Pin name A0~A8 DQ 1~DQ 16 RAS UCAS W OE VCC VSS Function Address inputs Data inputs / outputs Row address strobe input Upper byte control column address strobe input Write control input Power supply (+5V) Ground (0V) Output enable input Lower byte control column address strobe inputLCAS This is a family of 262144-word by 16-bit dynamic RAMs with Hyper Page mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal computer graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs FUNCTION In addition to Hyper page mode, normal read, write and read- modify-write operations the M5M44265CJ, TP provides a number of Table 1 Input conditions for each mode of other functions, e.g., RAS-only refresh and delayed-write. The input conditions for each are shown in Table 1. Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write RAS only refresh Self refresh* Word write CAS before RAS (Extended*) refresh RAS LCAS OE Inputs Input/Output W DQ 1~DQ 8 DQ 9~DQ 16 ACT ACT ACT ACT ACT ACT ACT NAC ACT NAC ACT ACT NAC ACT NAC DNC NAC NAC NAC ACT ACT ACT DNC DNC ACT ACT ACT NAC NAC NAC DNC DNC D OUT OPN D OUT D IN DNC D IN OPN OPN OPN D OUT D OUT DNC D IN D IN OPN OPN ACT ACT DNC DNC OPN OPN Stand-by ACT DNC DNC OPN D OUT UCAS NAC ACT ACT NAC ACT ACT NAC DNC ACT ACT ACT Hidden refresh ACT ACT ACTACT D OUT OPN BLOCK DIAGRAM ADDRESS INPUTS CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECO DER ROW COLU- MN ADD- RESS BUFF- ER MEMORY CELL (4194304 BITS) (8) UPPER DATA IN BUFFER (8)UPPER DATA OUT BUFFER VCC (5V) VSS (0V) DQ 9 OE DQ 10 DQ 16 UPPER DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT LOWER BYTE CONTROL COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT LCAS W RAS A0~A8 A0~ UCAS UPPER BYTE CONTROL COLUMN ADDRESS STROBE INPUT (8)LOWER DATA OUT BUFFER (8)LOWER DATA IN BUFFER LOWER UPPER DQ 1 DQ 2 DQ 8 LOWER DATA INPUTS / OUTPUTS VCC (5V) VSS (0V) VCC (5V) VSS (0V) NAC

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs ABSOLUTE MAXIMUM RATINGS Symbol VCC V I VO I O Pd Topr Tstg Parameter Conditions Ratings Unit V V V mA mW -1~7 1000 0~70 -65~150 With respect to VSS Ta=25 C Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature RECOMMENDED OPERATING CONDITIONS Unit Limits Min Nom Max V V V V 0.8 5.5 2.4 -0.5** Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs VCC Symbol VSS VIH VIL Note 1 : All voltage values are with respect to VSS. 5.04.5 6.0 (Ta=0~70˚C, unless otherwise noted) (Note 1) Note 2: Current flowing into an IC is positive, out is negative. Note 3: ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. Note 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. Note 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC =5V±10%, VSS =0V, unless otherwise noted) (Note 2) Symbol VOH VOL IOZ I I ICC1(AV) ICC2 ICC3(AV) ICC4(AV) ICC6(AV) High-level output voltage Parameter Limits Min Max UnitTypTest conditions Low-level output voltage Off-state output current Input current Average supply current from Vcc, operating (Note 3,4,5) (Note 3,5) (Note 3,4,5) Supply current from VCC , stand-by Average supply current from Vcc, RAS only refresh mode Average supply current from Vcc Hyper page mode Average supply current from Vcc CAS before RAS refresh mode M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S IOH =-2mA IOL =2mA Q floating 0V ≤ VOUT ≤ 5.5V 0V ≤ VIN ≤ +6.0V, Other inputs pins=0V RAS, CAS cycling tRC =tWC =min. output open RAS= CAS =V IH, output open RAS cycling, CAS=VIH tRC =min. output open RAS=V IL, CAS cycling tPC =min. output open CAS before RAS refresh cycling tRC =min. output open V V mA mA mA mA mA VCC 0.4 1.0 115 100 2.4 -10 -10 125 110 (Note 6) 125 110 125 110 M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Average supply current from VCC Extended-refresh mode µA150 Average supply current from VCC Self-refresh mode µA150 (Note 6) RAS= CAS ≥ VCC -0.5V output open 0.1* µA µA ICC8(AV)* ICC9(AV)* * *: VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.) RAS cycling CAS ≤ 0.2V or CAS before RAS refresh cycling RAS ≤ 0.2V or ≥ VCC -0.2V CAS ≤ 0.2V or ≥ VCC -0.2V W ≤ 0.2V or ≥ VCC -0.2V OE ≤ 0.2V or ≥ VCC -0.2V A0~A8 ≤ 0.2V or ≥ VCC -0.2V DQ=open tRC =250µs, tRAS =tRAS min~1µs (Note 3,5) (Note 6) -1~7 -1~7 RAS=CAS ≤ 0.2V output open

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1TTL and 50pF. The reference levels for measuring of output signals are 2.0V(VOH ) and 0.8V(VOL ). 8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥ tCP(max). 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max) . If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max) . 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max) . 12: tOEZ (max), tWEZ(max) , tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10µA ) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high. SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC =5V±10%, VSS =0V, unless otherwise noted, see notes 6,14,15) Limits Min Max Parameter Access time from CAS Access time from RAS Columu address access time Symbol tCAC Unit Min Max Min Max ns ns ns ns ns ns5 60tRAC tAA tCPA tOEA tCLZ Access time from CAS precharge Output low impedance time from CAS low Output disable time after CAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) tOFF tOEZ (Note 12) (Note 7) Output disable time after OE high Access time from OE ns ns M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S CAPACITANCE Limits Min Max UnitTyp pF pF pF Input capacitance, address inputsC I (A) C I (CLK) C I / O Symbol Parameter Test conditions Input capacitance, clock inputs Input/Output capacitance, data ports VI=VSS f=1MHz VI=25mVrms (Ta=0~70˚C, VCC =5V±10%, VSS =0V, unless otherwise noted) Output disable time after WE high Output disable time after RAS high Output hold time from CAS Output hold time from RAS (Note 13) tOHC tOHR tWEZ tREZ (Note 13) (Note 12,13) (Note 12) ns ns ns5 55 ns5 55 (Note 12,13)

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Read and Refresh Cycles Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Limits Min Max Parameter Read cycle time RAS low pulse width CAS low pulse width Symbol tRC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low Read setup time before CAS low Read hold time after CAS high (Note 22)tRCH tRRH ns ns tRAL tOCH tORH RAS hold time after CAS low Read hold time after RAS high Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low ns ns ns 10000 10000 10000 10000 10000 10000 110 130 (Note 22) M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Limits Min Max Parameter Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Symbol tREF Unit Min Max Min Max ms ns ns ns ns ns tRP tRCD tCRP tRPC tCPN Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width (Note 20) (Note 16) (Note 17) (Note 18) ns ns ns ns ns ns tRAD tASR tASC tRAH tCAH tT Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Transition time TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Hyper-Page Mode Cycles) (Note 19) (Note 19)Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data tDZC tDZO tCDD tODD ns ns ns ns Note 14: The timing requirements are assumed tT=2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max) , access time is tRAC . If tRCD is greater than tRCD(max ), access time is controlled exclusively by tCAC or tAA . 17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max ), access time is controlled exclusively by tAA . 18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max) , access time is controlled exclusively by tCAC . 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). (Ta=0~70˚C, VCC =5V±10%, VSS =0V, unless otherwise noted, see notes 14,15) (Note 20) (Note 21) M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S 8.2 8.2 8.2 mstREF Refresh cycle time* 128 128 128 (Note 20)Delay time, RAS high to datatRDD 13 15 ns20 tCAL Column address to CAS hold time ns13 18 23

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Read-Write and Read-Modify-Write Cycles Note 23: tRWC is specified as tRWC(min) =tRAC(max) +tODD(min)+tRWL(min)+tRP(min)+4tT. 24: tWCS , tCWD , tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min) , tRWD ≥ tRWD(min) , tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate. Limits Min Max Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width Symbol tRWC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note 23) (Note 24) ns ns ns tCWD tRWD tAWD Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low OE hold time after W lowtOEH 1513 20 ns 10000 10000 10000 1000010000 133 109 107 161 (Note 24) (Note 24) M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Write Cycle (Early Write and Delayed Write) Limits Min Max Parameter Write cycle time RAS low pulse width CAS low pulse width Symbol tWC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 24) tWCH tCWL ns ns tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low ns ns ns 10000 10000 10000 10000 10000 10000 ns 110 10tDH RAS hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width 130 M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S 10000

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Limits Min ParameterSymbol Unit Min Max Min Max ns ns ns ns ns ns (Note 27) (Note 28) (Note 24) 100000 M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S 100000 Max 100000 CAS before RAS Refresh Cycle (Note 29) Limits Min Max Parameter CAS setup time before RAS low Symbol tCSR Unit Min Max Min Max ns nstCHR 10CAS hold time after RAS low Note 29: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S ns17 17 22tCAS CAS low pulse width CBR self refresh RAS low pulse widthtRASS µs tRPS tCHS 100100 110 -50 100 -50 130 -50 CBR self refresh RAS high precharge time CBR self refresh CAS hold time Self Refresh Cycle* (Note 30) Limits Min Max ParameterSymbol Unit Min Max Min Max ns ns M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tHPC(min) is specified in the case of read-only and early write-only in Hyper page mode. 27: tRAS(min) is specified as two cycles of CAS input are performed. 28: tCP(max) is specified as a reference point only. Hyper page mode read/write cycle time RAS low pulse width for read or write cycle CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low Hyper page mode read write / read modify write cycle time Hold time to maintain the data Hi-Z until CAS access OE pulse width (Hi-Z control) W pulse width (Hi-Z control) Output hold time from CAS low Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD (Note 26) Hyper Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25) ns ns ns ns ns ns ns ns ns ns 5 5

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Timing Diagrams (Note 31) Read Cycle tCRP tASR tRAH tRAD tRCD tCSH tASC tCAH tRCS tRAS tRC tRSH tCAS tRAL tAA tCLZ tRAC tOFF tRCH tRP Hi-Z Note 31 Indicates the don't care input. VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max) Indicates the invalid output. tDZC tOEZ tOEA tOCH tDZO tCDD tORH tRPC tCRP LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS COLUMN ADDRESS Hi-Z Hi-Z tCAC tOEA DATA VALID tODD tOHR tOHC tWEZtREZ tRRH tASRtCAL ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Byte Read Cycle tCRP tASR tRAH tRAD tRCD tCSH tASC tCAH tRCS tRAS tRC tRSH tCAS tRAL tRAC tRCH tASR tRP Hi-Z tODD tOEA tOCH tDZO tORH tCAC tAA tCLZ tOFF Hi-ZHi-Z tDZC Hi-Z tRPC tCRP tCPN UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL ROW ADDRESS DATA VALID COLUMN ADDRESS tCDD tRRH tCAL tOEZ tREZ tOHR tOHC tWEZ ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Early Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tWCS tRAS tWC tRSH tCAS tWCH tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tDS tDH tRPC tCRP LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Byte Early Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tWCS tRAS tWC tRSH tCAS tWCH tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tDS tDH Hi-Z tRPC tCRP UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Delayed Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tWC tRSH tCAS tASR tRP Hi-Z ROW ADDRESS DATA VALID COLUMN ADDRESS tCLZ tWCH tCWL tRWL tDHtDS Hi-Z Hi-Z tWP tDZC tOEZtDZO tODD tOEH tRPC tCRP LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Byte Delayed Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tWC tRSH tCAS tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tCLZ tWCH tCWL tRWL tDHtDS Hi-Z Hi-Z tDZC tOEZtDZO tODD tOEH Hi-Z tRPC tCRP UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWP ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Read-Write, Read-Modify-Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tRWC tRSH tCAS tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tCLZ tCWL tRWL tDHtDS Hi-Z Hi-Z tWP tDZC tOEZ tDZO tODD tOEH tAWD tCWD tRWD DATA VALID tAA tCAC tRAC tOEA tRAD tRPC tCRP LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Byte Read-Write, Read-Modify-Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tRWC tRSH tCAS tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tCLZ tCWL tRWL tDH tDS Hi-Z Hi-Z tWP tDZC tOEZ tDZO tODD tOEH tAWD tCWD tRWD DATA VALID tAA tCAC tRAC tOEA tRAD Hi-Z tRPC tCRP UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL W VIH VIL VIH VIL VIH VIL VIH VIL Hyper Page Mode Read Cycle tCRP tASR tRAH tRAD tRCD tCAH tRAS tCP tCAC tAA tRAC tASR Hi-Z COLUMN-1 ROW ADDRESS tRP tCAS tASC tRCS Hi-Z tDZC tDZO tOEA tOCH DATA VALID-1 tCSH tHPC tCAS tCP tCAS tRSH COLUMN-2 COLUMN-3 tCAHtASC tCAHtASC tCPRH tRAL tRCH tRRH tCDD tCPA tOEZ tODD tREZ tOFFtCLZ tDOH tRDD tCAC tAA DATA VALID-2 tCPA tDOH tCAC DATA VALID-3 tAA tCAL tCAL tCAL tOHC tOHR tWEZ ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL Hyper Page Mode Byte Read Cycle tCAS tASR tRAH tRAD tCAH tASR ADDRESS COLUMN-1 ROW ADDRESS ROW tASC tRCS COLUMN-3 tCAHtASC tCAHtASC tCPRH tRAL tRCH tRRH tCRP tRCD tRAS tCP tRP tCAS tCSH tHPC tCP tCAS tRSH tCAL tCAL tCAL tCAC tAA tRAC Hi-Z Hi-Z tDZC tDZO tOEA tOCH DATA VALID-1 tODD tREZ tOFF tCLZ tRDD tCPA tDOH tCAC DATA VALID-3 tAA tOHC tOHR tDZC Hi-Z tCAC tAA tCPA DATA VALID-2 tCLZ Hi-Z tCDD tOEZ tWEZ tCRP COLUMN-2 W VIH VIL

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Hyper Page Mode Early Write Cycle tCRP tASR tRAH tRCD tCAH tRAS tCP tASR COLUMN-1 ROW ADDRESS tRP tCAS tASC tWCS tCSH tHPC tCAS tCP tCAS tRSH COLUMN-2 COLUMN-3 tCAH tCAHtASC tASC Hi-Z tWCH tWCS tWCH tWCS tWCH DATA VALID-1 DATA VALID-2 DATA VALID-3 tDS tDH tDS tDH tDS tDH tCAL tCAL tCRP ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs tCRP tRCD tRAS tCP Hi-Z tRP tCAS tCSH tHPC tCAS tCP tCAS tRSH ROW ADDRESS tCAH DATA VALID-2 tDS tDH tDS tDH tDS tDH tWCS tWCHtWCH tWCS tWCStWCH ROW ADDRESS Hyper Page Mode Byte Early Write Cycle COLUMN-1 COLUMN-2 COLUMN-3 tCAL tASR tRAH tCAH tASRtASC tCAH tASC tASC tCAL tCRP UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL DATA VALID-1 DATA VALID-3 Hi-Z

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Hyper Page Mode Read-Write, Read-Modify-Write Cycle LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tASR tRAH tRCD tCAH tCP tASR tCAS tASC tHPRWC tCAS ADDRESS ROW ADDRESS ROW tCAHtASC tRWD tCWL tWPtWP tCWL tCPWD tRAD tCWD tAWD tAWD tCWD COLUMN-1 COLUMN-2 tCRP tRAS tRP tCSH tRWL tRCStRCS Hi-Z tDS Hi-Z Hi-Z tDS DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tDZO tOEZ tODD tDZO tOEZ tOEH tCAC DATA VALID-1 tAA tCAC DATA VALID-2 tRAC tOEA tCPA tOEA tODD tDZCtDHtDZC tAA tCRP DATA VALID-1 tCLZ

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Hyper Page Mode Byte Read-Write, Read-Modify-Write Cycle UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tHPRWC tCAS tRWL ADDRESS ROW ADDRESS ROW tCAHtASC tRWD DATA VALID-1 tDS tCWL tWPtWP tCWL Hi-Z Hi-Z tDS tCPWD DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tDZO tOEZ tODD tDZO tOEZ tOEH tRAD tCWD tAWD tAWD tCWD tCAC DATA VALID-1 tAA tCAC DATA VALID-2 tRAC tOEA tCPA tOEA tODD Hi-Z tDZC COLUMN-1 COLUMN-2 tRCStRCS tDHtDZC tAA tCRP tCLZ

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tHPRWC tCAS tRWL tCAHtASC tDZC tDS tCWL tWP tWEZ tDH tDS tCWD tDH tCLZ tDZO tOEZ tODD tDZO tOEZ tOEH tRAD tAWD tCPWD tCAC tCAC DATA VALID-3 tCLZ tRAC tOEA tCPA tOEA tWCH Hyper Page Mode Mix Cycle (1) tAA tCP DATA VALID-1 tHPC tCAHtASC tWCS tCAL tCRP ROW ADDRESS COLUMN-3 tCAS tCAL DATA VALID-2 tOCH tODD tRCS tDZC tAA DATA VALID-3 COLUMN-1 COLUMN-2 ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL DATA VALID-1 tCAHtASC DATA VALID-3 tAA tCAC tOEZ tDS tODD DATA VALID-2 Hi-Z tDH tDZC Hi-Z COLUMN-1 tCAHtASC tCAHtASC COLUMN-2 COLUMN-3 tCPA tAA tWCH tCAC tOEA tCLZ Hi-Z tCPA tCAL tCP tCAS tRCH tWCS tWEZ tCAL Hyper Page Mode Mix Cycle (2) tDZC tCAS tHCOD tHAOD tHPOD tHCWD tHAWD tHPWD

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs tCRP tASR tRAH tRCD tCAH tRAS tCP tRP tCAS tCSH tCAS tRSH tCAHtASC LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Hyper Page Mode Read Cycle (Hi-Z control by OE) tRAD tCAC tAA tRAC tASR Hi-Z COLUMN-1 ROW ADDRESS tRCS Hi-Z tDZC tDZO tOEA DATA VALID-1 tHPC COLUMN-2 COLUMN-3 tCPRH tRAL tRCH tRRH tCDD tCPA tOEZ tODD tREZ tOFFtCLZ tDOH tRDD tCAC tAA DATA VALID-2 tCPA tOEZ tCAC DATA VALID-3 tAA tCLZ Hi-Z tOEPE tCHOL tOEPE tOEZ tOEA tOCH DATA VALID-1 tOHR tOHC tCRP tWEZ tCP tCAS tCAHtASC tASC ROW ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs tCRP tASR tRAH tRCD tCAH tRAS tCP tRP tCAS tCSH tCAS tRSH tCAHtASC LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Hyper Page Mode Read Cycle (Hi-Z control by W) tRAD tCAC tAA tRAC tASR Hi-Z COLUMN-1 ROW ADDRESS tRCS Hi-Z tDZC tDZO tOEA DATA VALID-1 tHPC COLUMN-2 COLUMN-3 tCPRH tRAL tRCH tRRH tCDD tCPA tOEZ tODD tREZ tOFFtCLZ tDOH tRDD tCAC tAA DATA VALID-2 tCPA tCAC DATA VALID-3 tAA tCLZ Hi-Z tOCH tOHR tOHC tCRP tWEZ tCP tCAS tCAHtASC tASC ROW ADDRESS tWEZ tWPE tRCS tRCH

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs RAS-only Refresh Cycle tCRP tASR tRAH tRAS tRC tASR tCRPtRPC tRP ROW ADDRESS Hi-Z ROW ADDRESS LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~ A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs CAS before RAS Refresh Cycle, Extended Refresh Cycle* tRAS tRC tASR tCRPtRPC tRP ROW ADDRESS tRPC tRC tRAS tCSR tCHR tCSRtRPC tCPN tRCS tOFF Hi-Z tOEZ tRP tCHR LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRRH tRCH tOHC tOHR tREZ COLUMN ADDRESS

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Hidden Refresh Cycle (Read) (Note 32) Note 32: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. tCRP tASR tRAH tRAD tRCD tCAH tRCS tRAS tRC tCHR tCAC tAA tCLZ tRAC tRRH tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tRAS tRC tRP tRSH tASC tRAL Hi-Z tDZC tCDD Hi-Z tDZO tOEA tORH tODD tOEZ ROW ADDRESS LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tOFF tOHC tREZ tRDD tOHR

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Self Refresh Cycle* (Note 30) tRPC tRPS tASR tCRP ROW ADDRESS tRASS tCSR tCPN tRCH tRCS tREZ Hi-Z tOEZ tRP tCHS tRPC Hi-Z tRDD tODD LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRRH tCDD tOHR tOFF tOHC

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). Note 30 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width (tRASS ) of RAS signal during self refresh period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram Read / Write Cycle Self Refresh Cycle Read / Write Cycle tNSD tRASS ≥100µs tSND last refresh cycle first refresh cycle Table 2 Definition of CBR distributed refresh (Including extended refresh) Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND (shown in table 2). Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16µs. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. RAS Read / Write Cycle CBR distributed refresh RAS only distributed refresh Self Refresh Read / Write tNSD ≤16µs tSND ≤16µs (B) Definition of distributed refresh tREF tREF / 512 refresh cycle read/write cycles RAS tREF / 512 read/write cycles refresh cycle refresh cycle Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh.

1.1 CBR distributed refresh

1.2 RAS only distributed refresh

The CBR distributed refresh performs more than 512 constant period (250µs max.) CBR cycles within 128 ms. All combinations of nine row address signals (A0~A 8) are selected during 512 constant period (16µs max.) RAS only refresh cycles within 8.2 ms. Definition of RAS only distributed refresh tNSD ≤250µs tSND ≤250µs Read / Write Self Refresh

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs 2. Burst refresh during Read/Write operation (A) Timing diagram Read / Write Self Refresh Read / Write tNSB tRASS ≥100µs tSNB last refresh cycles first refresh cycles Table 3 Read / Write Cycle CBR burst refresh RAS only burst refresh Read / Write Self Refresh Self Refresh Read / Write tNSB +tSNB ≤ 8.2ms Definition of CBR burst refresh Switching from read/write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 8.2 ms. Switching from self refresh operation to read/write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 8.2 ms. Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3). RAS refresh cycles 511 cycles refresh cycles 511 cycles (B) Definition of burst refresh 8.2ms read/write cycles RAS refresh cycles 512 cycles 2.2 RAS only burst refresh2.1 CBR burst refresh The CBR burst refresh performs more than 512 continuous CBR cycles within 8.2 ms. All combination of nine row address signals (A0~A 8) are selected during 512 continuous RAS only refresh cycles within 8.2 ms. Definition of RAS only burst refresh tSNB ≤ 8.2mstNSB ≤ 8.2ms